Conferences in DBLP
Tam Anh Chu , Narayana Mani , Clement K. C. Leung An Efficient Critical Race-Free State Assignment Technique for Asynchronous Finite State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Cho W. Moon , Robert K. Brayton Elimination of Dynamic hazards by Factoring. [Citation Graph (0, 0)][DBLP ] Conf ] Régis Leveugle Optimized State Assignment of single fault Tolerant FSMs Based on SEC Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Alice M. Tokarnia Minimal Shift Counters and Frequency Division. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunwoo Cho , Gary D. Hachtel , Enrico Macii , Bernard Plessier , Fabio Somenzi Algorithms for Approximate FSM Traversal. [Citation Graph (0, 0)][DBLP ] Conf ] Miles Ohlrich , Carl Ebeling , Eka Ginting , Lisa Sather SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Lorenz Ladage , Rainer Leupers Resistance Extraction using a Routing Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Glenn G. Lai , Donald S. Fussell , D. F. Wong HV/VH Trees: A New Spatial Data Structure for Fast Region Queries. [Citation Graph (0, 0)][DBLP ] Conf ] Emil F. Girczyc , Steve Carlson Increasing Design Quality and Engineering Productivity through Design Reuse. [Citation Graph (0, 0)][DBLP ] Conf ] Edmund M. Clarke , Kenneth L. McMillan , Xudong Zhao , Masahiro Fujita , J. Yang Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Polly Siegel , Giovanni De Micheli , David L. Dill Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain Technology Decomposition and Mapping Targeting Low Power Dissipation. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek Tiwari , Pranav Ashar , Sharad Malik Technology Mapping for Lower Power. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy INCREDYBLE-TG : INCREmental DYnamic test generation based on LEarning.Citation Graph (0, 0)][DBLP ] Conf ] Kwang-Ting Cheng , A. S. Krishnakumar Automatic Functional Test Generation Using the Extended Finite State Machine Model. [Citation Graph (0, 0)][DBLP ] Conf ] Jean François Santucci , Anne-lise Courbis , Norbert Giambiasi Speed up of Behavioral A.T.P.G. using a Heuristic Criterion. [Citation Graph (0, 0)][DBLP ] Conf ] Akira Motohara , Toshinori Hosokawa , Michiaki Muraoka , Hidetsugu Maekawa , Kazuhiro Kayashima , Yasuharu Shimeki , Seichi Shin A State Traversal Algorithm Using a State Covariance Matrix. [Citation Graph (0, 0)][DBLP ] Conf ] Seiji Kajihara , Irith Pomeranz , Kozo Kinoshita , Sudhakar M. Reddy Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Prathima Agrawal , Vishwani D. Agrawal , Joan Villoldo Sequential Circuit Test Generation on a Distributed System. [Citation Graph (0, 0)][DBLP ] Conf ] Hoon Chang , Jacob A. Abraham VIPER: An Efficient Vigorously Sensitizable Path Extractor. [Citation Graph (0, 0)][DBLP ] Conf ] Shiang-Tang Huang , Tai-Ming Parng , Jyuo-Min Shyu A Polynomial-Time Heuristic Approach to Approximate a Solution to the False Path Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Masamichi Kawarabayashi , Narendra V. Shenoy , Alberto L. Sangiovanni-Vincentelli A Verification Technique for Gated Clock. [Citation Graph (0, 0)][DBLP ] Conf ] William K. C. Lam , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Ben Jone , Chen-Liang Fang Timing Optimization By Gate Resizing And Critical Path Identification. [Citation Graph (0, 0)][DBLP ] Conf ] Kurt Keutzer What is the Next Big Productivity Boost for Designers? (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Helmut E. Graeb , Claudia U. Wieser , Kurt Antreich Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating Tolerances. [Citation Graph (0, 0)][DBLP ] Conf ] N. S. Nagaraj A New Optimizer for Performance Optimization of Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Dharchoudhury , Sung-Mo Kang Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Edward W. Y. Liu , Henry C. Chang , Alberto L. Sangiovanni-Vincentelli Analog System Verification in the Presence of Parasitics Using Behavioral Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan Rose Logic Emulation: A Niche or a Future Standard for Design Verification? (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Satyamurthy Pullela , Noel Menezes , Lawrence T. Pillage Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Lim , Siu-Wing Cheng , Ching-Ting Wu Performance Oriented Rectilinear Steiner Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Xianlong Hong , Tianxiong Xue , Ernest S. Kuh , Chung-Kuan Cheng , Jin Huang Performance-Driven Steiner Tree Algorithm for Global Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth D. Boese , Andrew B. Kahng , Gabriel Robins High-Performance Routing Trees With Identified Critical Sinks. [Citation Graph (0, 0)][DBLP ] Conf ] Ing-Yi Chen , Geng-Lin Chen , Fredrick J. Hill , Sy-Yen Kuo The Sea-of-Wires Array Aynthesis System. [Citation Graph (0, 0)][DBLP ] Conf ] Ranga Vemuri , Paddy Mamtora , Praveen Sinha , Nand Kumar , Jayanta Roy , Raghu Vutukuru Experiences in Functional Validation of a High Level Synthesis System. [Citation Graph (0, 0)][DBLP ] Conf ] Nam Sung Woo , Jaeseok Kim An Efficient Method of Partitioning Circuits for Multiple-FPGA Implementation.. [Citation Graph (0, 0)][DBLP ] Conf ] Prashant Sawkar , Donald E. Thomas Performance Directed Technology Mapping for Look-Up Table Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Yuzheng Ding On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Mahesh Mehendale MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Murgai , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Sequential Synthesis for Table Look Up Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Hirendu Vaishnav , Massoud Pedram Routability-Driven Fanout Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek Chickermane , Elizabeth M. Rudnick , Prithviraj Banerjee , Janak H. Patel Non-Scan Design-for-Testability Techniques for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Rajagopalan Srinivasan , Sandeep K. Gupta , Melvin A. Breuer An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitrios Kagaris , Spyros Tragoudas Partial Scan with Retiming. [Citation Graph (0, 0)][DBLP ] Conf ] Prashant S. Parikh , Miron Abramovici A Cost-Based Approach to Partial Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Yusuke Matsunaga , Patrick C. McGeer , Robert K. Brayton On Computing the Transitive Closure of a State Transition Relation. [Citation Graph (0, 0)][DBLP ] Conf ] Alan J. Hu , David L. Dill Reducing BDD Size by Exploiting Functional Dependencies. [Citation Graph (0, 0)][DBLP ] Conf ] Shin-ichi Minato Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Rachel Y. W. Lau , Hilary J. Kahn Information Modelling of EDIF. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen R. Pollock Life Expectancy of Standards (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Mehrdad Nourani , Christos A. Papachristou A Layout Estimation Algorithm for RTL Datapaths. [Citation Graph (0, 0)][DBLP ] Conf ] Tien-Chien Lee , Niraj K. Jha , Wayne Wolf Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments. [Citation Graph (0, 0)][DBLP ] Conf ] Taewhan Kim , C. L. Liu Utilization of Multiport Memories in Data Path Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Debabrata Ghosh , S. K. Nandy , P. Sadayappan , K. Parthasarathy Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Wolf Embedded Systems and Hardware-Software Co-Design: Panacea or Pandora's Box? (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Rajmohan Rajaraman , D. F. Wong Optimal Clustering for Delay Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Roman Kuznar , Franc Brglez , Krzysztof Kozminski Cost Minimization of Partitions into Multiple Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Sudip Nag , Kaushik Roy Iterative Wirability and Performance Improvement for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Pak K. Chan , Martine D. F. Schlag , Jason Y. Zien On Routability Prediction for Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Ralph D. Nurnberger The Clinton/Gore Technology Policies. [Citation Graph (0, 0)][DBLP ] Conf ] Haigeng Wang , Nikil D. Dutt , Alexandru Nicolau , Kai-Yeung Siu High-Level Synthesis of Scalable Architectures for IIR Filters using Multichip Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Chatterjee , Rabindra K. Roy An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Alok Sharma , Rajiv Jain InSyn: Integrated Scheduling for DSP Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Alok Sharma , Rajiv Jain Estimating Architectural Resources and Performance for High-Level Synthesis Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Bradley S. Carlson , C. Y. Roger Chen Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering. [Citation Graph (0, 0)][DBLP ] Conf ] Dah-Cherng Yuan , Lawrence T. Pillage , Joseph T. Rahmeh Evaluation of Parts by Mixed-Level DC-Connected Components in Logic Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Benoit A. Gennart Comparative Design Validation Based on Event Pattern Mappings. [Citation Graph (0, 0)][DBLP ] Conf ] Georgios I. Stamoulis , Ibrahim N. Hajj Improved Techniques for Probabilistic Simulation Including Signal Correlation Effects. [Citation Graph (0, 0)][DBLP ] Conf ] Harish Kriplani , Farid N. Najm , Ping Yang , Ibrahim N. Hajj Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Cyrus Bamji , Ravi Varadarajan MSTC: A Method for Identifying Overconstraints during Hierarchical Compaction. [Citation Graph (0, 0)][DBLP ] Conf ] So-Zen Yao , Chung-Kuan Cheng , Debaprosad Dutt , Surendra Nahar , Chi-Yuan Lo Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP. [Citation Graph (0, 0)][DBLP ] Conf ] Peichen Pan , Sai-keung Dong , C. L. Liu Optimal Graph Constraint Reduction for Symbolic Layout Compaction. [Citation Graph (0, 0)][DBLP ] Conf ] Joseph Dao , Nobu Matsumoto , Tsuneo Hamai , Chusei Ogawa , Shojiro Mori A Compaction Method for Full Chip VLSI Layouts. [Citation Graph (0, 0)][DBLP ] Conf ] Viraphol Chaiyakul , Daniel Gajski , Loganath Ramachandran High-Level Transformations for Minimizing Syntactic Variances. [Citation Graph (0, 0)][DBLP ] Conf ] Christos A. Papachristou , Haidar Harmanani , Mehrdad Nourani An Approach for Redesigning in Data Path Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Seawright , Forrest Brewer High-Level Symbolic Construction Technique for High Performance Sequential Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Ramesh Karri , Alex Orailoglu High-Level Synthesis of Fault-Secure Microarchitectures. [Citation Graph (0, 0)][DBLP ] Conf ] Manjote S. Haworth , William P. Birmingham Towards Optimal System-Level Design. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy , Prasanti Uppaluri NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] William K. C. Lam , Alexander Saldanha , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Delay Fault Coverage and Performance Tradeoffs. [Citation Graph (0, 0)][DBLP ] Conf ] Tapan J. Chakraborty , Vishwani D. Agrawal , Michael L. Bushnell Design for Testability for Path Delay faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Chess , Tracy Larrabee Bridge Fault simulation strategies for CMOS integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] June-Kyung Rho , Fabio Somenzi , Carl Pixley Minimum Length Synchronizing Sequences of Finite State Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey J. Joyce , Carl-Johan H. Seger Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving. [Citation Graph (0, 0)][DBLP ] Conf ] Ramin Hojati , Thomas R. Shiple , Robert K. Brayton , Robert P. Kurshan A Unified Approach to Language Containment and Fair CTL Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] William S. Johnson Are EDA Platform Preferences About to Shift? (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Srimat T. Chakradhar , Sujit Dey , Miodrag Potkonjak , Steven G. Rothweiler Sequential Circuit Delay optimization Using Global Path Delays. [Citation Graph (0, 0)][DBLP ] Conf ] Narendra V. Shenoy , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Resynthesis of Multi-Phase Pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Marios C. Papaefthymiou , Keith H. Randall TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry. [Citation Graph (0, 0)][DBLP ] Conf ] Pi-Yu Chung , Yi-Min Wang , Ibrahim N. Hajj Diagnosis and Correction of Logic Design Errors in Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Naveena Nagi , Abhijit Chatterjee , Jacob A. Abraham DRAFTS: Discretized Analog Circuit Fault Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang Meyer , Raul Camposano Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy. [Citation Graph (0, 0)][DBLP ] Conf ] Sreejit Chakravarty , Yiming Gong An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Tsu-chang Lee A Bounded 2D Contour Searching Algorithm for Floorplan Design with Arbitrarily Shaped Rectilinear and Soft Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Takeo Hamada , Chung-Kuan Cheng , Paul M. Chau Prime : A Timing-Driven Placement Tool using A Piecewise Linear Resistive Network Approach.Citation Graph (0, 0)][DBLP ] Conf ] Jun Dong Cho , Majid Sarrafzadeh A Nuffer Distribution Algorithm for High-Speed Clock Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Masato Mogaki , Youichi Shiraishi , Mitsuyuki Kimura , Tetsuro Hino Cooperative Approach to a Practical Analog LSI Layout System. [Citation Graph (0, 0)][DBLP ] Conf ] Gopi Ganapathy , Jacob A. Abraham Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth W. Wan , Roshan A. Gidwani ABLE: AMD Backplane for Layout Engines. [Citation Graph (0, 0)][DBLP ] Conf ] Steven G. Duvall Practical Statistical Design of Complex Integrated Circuit Products. [Citation Graph (0, 0)][DBLP ] Conf ] Liang-Fang Chao , Andrea S. LaPaugh , Edwin Hsing-Mean Sha Rotation Scheduling: A Loop Pipelining Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Zia Iqbal , Miodrag Potkonjak , Sujit Dey , Alice C. Parker Critical Path Minimization Using Retiming and Algebraic Speed-Up. [Citation Graph (0, 0)][DBLP ] Conf ] S. H. Huang , Y. L. Jeang , C. T. Hwang , Y. C. Hsu , J. F. Wang A Tree-Based Scheduling Algorithm for Control-Dominated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Richard J. Cloutier , Donald E. Thomas Synthesis of Pipelined Instruction Set Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Michael C. McFarland Military to Commercial Conversion: Is it Necessary, Is it Practical, Is it Possible? (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Kei-Yong Khoo , Jason Cong An Efficient Multilayer MCM Router Based on Four-Via Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Jin Huang , Xianlong Hong , Chung-Kuan Cheng , Ernest S. Kuh An Efficient Timing-Driven Global Routing Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Forbes D. Lewis , Wang Chia-Chi Pong A Negative Reinforcement Method for PGA Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Kwok-Shing Leung , Dian Zhou Performance-Driven Interconnect Design Based on Distributed RC Delay Model. [Citation Graph (0, 0)][DBLP ] Conf ] Masato Edahiro A Clustering-Based Optimization Algorithm in Zero-Skew Routings. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald Collett Multi-vendor Tool Integration Experiences (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Patrick C. McGeer , Jagesh V. Sanghavi , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Espresso-Signature: A New Exact Minimizer for Logic Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Coudert , Jean Christophe Madre , Henri Fraisse A New Viewpoint on Two-Level Logic Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Maurizio Damiani , Jerry Chih-Yuan Yang , Giovanni De Micheli Optimization of Combinational Logic Circuits Based on Compatible Gates. [Citation Graph (0, 0)][DBLP ] Conf ] Hans Eveking , Stefan Höreth Optimization and Resynthesis of Complex Data-Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Yung-Te Lai , Massoud Pedram , Sarma B. K. Vrudhula BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Peter R. Sutton , Jay B. Brockman , Stephen W. Director Design Management Using Dynamically Defined Flows. [Citation Graph (0, 0)][DBLP ] Conf ] Mário J. Silva , Randy H. Katz Active Documentation: A New Interface for VLSI Design. [Citation Graph (0, 0)][DBLP ] Conf ] Ram Mandayam , Ranga Vemuri Performance Specification Using Attributed Grammars. [Citation Graph (0, 0)][DBLP ] Conf ] Cristian A. Giumale , Hilary J. Kahn An Information Model of Time. [Citation Graph (0, 0)][DBLP ] Conf ] Yehuda Kra A Cross-Debugging Method for Hardware/Software Co-design Environments. [Citation Graph (0, 0)][DBLP ] Conf ] Mattan Kamon , Michael J. Tsuk , Jacob White FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program. [Citation Graph (0, 0)][DBLP ] Conf ] Tai-Yu Chou , Jay Cosentino , Zoltan J. Cendes High-Speed Interconnect Modeling and High-Accuracy Simulation Using SPICE and Finite Element Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Mysore Sriram , Sung-Mo Kang Fast Approximation of the Transient Response of Lossy Transmision Line Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Monjurul Haque , S. Chowdhury Analysis and Reliable Design of ECL Circuits with Distributed RLC Interconnections. [Citation Graph (0, 0)][DBLP ] Conf ] Hansruedi Heeb , Saila Ponnapalli , Albert E. Ruehli Frequency Domain Microwave Modeling Using Retarded Partial Element Equivalent Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Valery Yarnikh The State of CAD and VLSI in Russia. [Citation Graph (0, 0)][DBLP ] Conf ] Yuri Tatarnikov The State of VHDL in Russia. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Birger The State of Simulation in Russia. [Citation Graph (0, 0)][DBLP ] Conf ] Valery M. Mikhov The State of EDA in Russian Universities. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew T. Yang , Yu Liu , Jack T. Yao , R. R. Daniels An Efficient Non-Quasi-Static Diode Model for Circuit Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Haifang Liao , Wayne Wei-Ming Dai , Rui Wang , Fung-Yuel Chang S-Parameter Based Macro Model of Distributed-Lumped Networks Using Exponentially Decayed Polynomial Function. [Citation Graph (0, 0)][DBLP ] Conf ] Eli Chiprout , Michel S. Nakhla Addressing High-Speed Interconnect Issues in Asymptotic Waveform Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Chandramouli Visweswariah , Jalal A. Wehbeh Incremental Event-Driven Simulation of Digital FET Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] John A. Darringer Where in the World Should CAD Software be Made? (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Charles J. Alpert , Andrew B. Kahng Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Pak K. Chan , Martine D. F. Schlag , Jason Y. Zien Spectral K -Way Ratio-Cut Partitioning and Clustering. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , M'Lissa Smith A Parallel Bottom-Up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design. [Citation Graph (0, 0)][DBLP ] Conf ] Minshine Shih , Ernest S. Kuh Quadratic Boolean Programming for Performance-Driven System Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Romesh Wadhwani The Key to EDA Results: Component & Library Management (Panel Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] 