The SCEAS System
Navigation Menu

Conferences in DBLP

Design Automation Conference (DAC) (dac)
1993 (conf/dac/93)

  1. Tam Anh Chu, Narayana Mani, Clement K. C. Leung
    An Efficient Critical Race-Free State Assignment Technique for Asynchronous Finite State Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:2-6 [Conf]
  2. Cho W. Moon, Robert K. Brayton
    Elimination of Dynamic hazards by Factoring. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:7-13 [Conf]
  3. Régis Leveugle
    Optimized State Assignment of single fault Tolerant FSMs Based on SEC Codes. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:14-18 [Conf]
  4. Alice M. Tokarnia
    Minimal Shift Counters and Frequency Division. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:19-24 [Conf]
  5. Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Bernard Plessier, Fabio Somenzi
    Algorithms for Approximate FSM Traversal. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:25-30 [Conf]
  6. Miles Ohlrich, Carl Ebeling, Eka Ginting, Lisa Sather
    SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:31-37 [Conf]
  7. Lorenz Ladage, Rainer Leupers
    Resistance Extraction using a Routing Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:38-42 [Conf]
  8. Glenn G. Lai, Donald S. Fussell, D. F. Wong
    HV/VH Trees: A New Spatial Data Structure for Fast Region Queries. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:43-47 [Conf]
  9. Emil F. Girczyc, Steve Carlson
    Increasing Design Quality and Engineering Productivity through Design Reuse. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:48-53 [Conf]
  10. Edmund M. Clarke, Kenneth L. McMillan, Xudong Zhao, Masahiro Fujita, J. Yang
    Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:54-60 [Conf]
  11. Polly Siegel, Giovanni De Micheli, David L. Dill
    Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:61-67 [Conf]
  12. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
    Technology Decomposition and Mapping Targeting Low Power Dissipation. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:68-73 [Conf]
  13. Vivek Tiwari, Pranav Ashar, Sharad Malik
    Technology Mapping for Lower Power. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:74-79 [Conf]
  14. Irith Pomeranz, Sudhakar M. Reddy
    INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:80-85 [Conf]
  15. Kwang-Ting Cheng, A. S. Krishnakumar
    Automatic Functional Test Generation Using the Extended Finite State Machine Model. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:86-91 [Conf]
  16. Jean François Santucci, Anne-lise Courbis, Norbert Giambiasi
    Speed up of Behavioral A.T.P.G. using a Heuristic Criterion. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:92-96 [Conf]
  17. Akira Motohara, Toshinori Hosokawa, Michiaki Muraoka, Hidetsugu Maekawa, Kazuhiro Kayashima, Yasuharu Shimeki, Seichi Shin
    A State Traversal Algorithm Using a State Covariance Matrix. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:97-101 [Conf]
  18. Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
    Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:102-106 [Conf]
  19. Prathima Agrawal, Vishwani D. Agrawal, Joan Villoldo
    Sequential Circuit Test Generation on a Distributed System. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:107-111 [Conf]
  20. Hoon Chang, Jacob A. Abraham
    VIPER: An Efficient Vigorously Sensitizable Path Extractor. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:112-117 [Conf]
  21. Shiang-Tang Huang, Tai-Ming Parng, Jyuo-Min Shyu
    A Polynomial-Time Heuristic Approach to Approximate a Solution to the False Path Problem. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:118-122 [Conf]
  22. Masamichi Kawarabayashi, Narendra V. Shenoy, Alberto L. Sangiovanni-Vincentelli
    A Verification Technique for Gated Clock. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:123-127 [Conf]
  23. William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:128-134 [Conf]
  24. Wen-Ben Jone, Chen-Liang Fang
    Timing Optimization By Gate Resizing And Critical Path Identification. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:135-140 [Conf]
  25. Kurt Keutzer
    What is the Next Big Productivity Boost for Designers? (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:141- [Conf]
  26. Helmut E. Graeb, Claudia U. Wieser, Kurt Antreich
    Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating Tolerances. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:142-147 [Conf]
  27. N. S. Nagaraj
    A New Optimizer for Performance Optimization of Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:148-153 [Conf]
  28. Abhijit Dharchoudhury, Sung-Mo Kang
    Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:154-158 [Conf]
  29. Edward W. Y. Liu, Henry C. Chang, Alberto L. Sangiovanni-Vincentelli
    Analog System Verification in the Presence of Parasitics Using Behavioral Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:159-163 [Conf]
  30. Jonathan Rose
    Logic Emulation: A Niche or a Future Standard for Design Verification? (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:164- [Conf]
  31. Satyamurthy Pullela, Noel Menezes, Lawrence T. Pillage
    Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:165-170 [Conf]
  32. Andrew Lim, Siu-Wing Cheng, Ching-Ting Wu
    Performance Oriented Rectilinear Steiner Trees. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:171-176 [Conf]
  33. Xianlong Hong, Tianxiong Xue, Ernest S. Kuh, Chung-Kuan Cheng, Jin Huang
    Performance-Driven Steiner Tree Algorithm for Global Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:177-181 [Conf]
  34. Kenneth D. Boese, Andrew B. Kahng, Gabriel Robins
    High-Performance Routing Trees With Identified Critical Sinks. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:182-187 [Conf]
  35. Ing-Yi Chen, Geng-Lin Chen, Fredrick J. Hill, Sy-Yen Kuo
    The Sea-of-Wires Array Aynthesis System. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:188-193 [Conf]
  36. Ranga Vemuri, Paddy Mamtora, Praveen Sinha, Nand Kumar, Jayanta Roy, Raghu Vutukuru
    Experiences in Functional Validation of a High Level Synthesis System. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:194-201 [Conf]
  37. Nam Sung Woo, Jaeseok Kim
    An Efficient Method of Partitioning Circuits for Multiple-FPGA Implementation.. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:202-207 [Conf]
  38. Prashant Sawkar, Donald E. Thomas
    Performance Directed Technology Mapping for Look-Up Table Based FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:208-212 [Conf]
  39. Jason Cong, Yuzheng Ding
    On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:213-218 [Conf]
  40. Mahesh Mehendale
    MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:219-223 [Conf]
  41. Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Sequential Synthesis for Table Look Up Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:224-229 [Conf]
  42. Hirendu Vaishnav, Massoud Pedram
    Routability-Driven Fanout Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:230-235 [Conf]
  43. Vivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel
    Non-Scan Design-for-Testability Techniques for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:236-241 [Conf]
  44. Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer
    An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:242-248 [Conf]
  45. Dimitrios Kagaris, Spyros Tragoudas
    Partial Scan with Retiming. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:249-254 [Conf]
  46. Prashant S. Parikh, Miron Abramovici
    A Cost-Based Approach to Partial Scan. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:255-259 [Conf]
  47. Yusuke Matsunaga, Patrick C. McGeer, Robert K. Brayton
    On Computing the Transitive Closure of a State Transition Relation. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:260-265 [Conf]
  48. Alan J. Hu, David L. Dill
    Reducing BDD Size by Exploiting Functional Dependencies. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:266-271 [Conf]
  49. Shin-ichi Minato
    Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:272-277 [Conf]
  50. Rachel Y. W. Lau, Hilary J. Kahn
    Information Modelling of EDIF. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:278-283 [Conf]
  51. Stephen R. Pollock
    Life Expectancy of Standards (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:284- [Conf]
  52. Mehrdad Nourani, Christos A. Papachristou
    A Layout Estimation Algorithm for RTL Datapaths. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:285-291 [Conf]
  53. Tien-Chien Lee, Niraj K. Jha, Wayne Wolf
    Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:292-297 [Conf]
  54. Taewhan Kim, C. L. Liu
    Utilization of Multiport Memories in Data Path Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:298-302 [Conf]
  55. Debabrata Ghosh, S. K. Nandy, P. Sadayappan, K. Parthasarathy
    Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:303-307 [Conf]
  56. Wayne Wolf
    Embedded Systems and Hardware-Software Co-Design: Panacea or Pandora's Box? (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:308- [Conf]
  57. Rajmohan Rajaraman, D. F. Wong
    Optimal Clustering for Delay Minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:309-314 [Conf]
  58. Roman Kuznar, Franc Brglez, Krzysztof Kozminski
    Cost Minimization of Partitions into Multiple Devices. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:315-320 [Conf]
  59. Sudip Nag, Kaushik Roy
    Iterative Wirability and Performance Improvement for FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:321-325 [Conf]
  60. Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien
    On Routability Prediction for Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:326-330 [Conf]
  61. Ralph D. Nurnberger
    The Clinton/Gore Technology Policies. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:331-335 [Conf]
  62. Haigeng Wang, Nikil D. Dutt, Alexandru Nicolau, Kai-Yeung Siu
    High-Level Synthesis of Scalable Architectures for IIR Filters using Multichip Modules. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:336-342 [Conf]
  63. Abhijit Chatterjee, Rabindra K. Roy
    An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:343-348 [Conf]
  64. Alok Sharma, Rajiv Jain
    InSyn: Integrated Scheduling for DSP Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:349-354 [Conf]
  65. Alok Sharma, Rajiv Jain
    Estimating Architectural Resources and Performance for High-Level Synthesis Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:355-360 [Conf]
  66. Bradley S. Carlson, C. Y. Roger Chen
    Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:361-366 [Conf]
  67. Dah-Cherng Yuan, Lawrence T. Pillage, Joseph T. Rahmeh
    Evaluation of Parts by Mixed-Level DC-Connected Components in Logic Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:367-372 [Conf]
  68. Benoit A. Gennart
    Comparative Design Validation Based on Event Pattern Mappings. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:373-378 [Conf]
  69. Georgios I. Stamoulis, Ibrahim N. Hajj
    Improved Techniques for Probabilistic Simulation Including Signal Correlation Effects. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:379-383 [Conf]
  70. Harish Kriplani, Farid N. Najm, Ping Yang, Ibrahim N. Hajj
    Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:384-388 [Conf]
  71. Cyrus Bamji, Ravi Varadarajan
    MSTC: A Method for Identifying Overconstraints during Hierarchical Compaction. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:389-394 [Conf]
  72. So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo
    Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:395-400 [Conf]
  73. Peichen Pan, Sai-keung Dong, C. L. Liu
    Optimal Graph Constraint Reduction for Symbolic Layout Compaction. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:401-406 [Conf]
  74. Joseph Dao, Nobu Matsumoto, Tsuneo Hamai, Chusei Ogawa, Shojiro Mori
    A Compaction Method for Full Chip VLSI Layouts. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:407-412 [Conf]
  75. Viraphol Chaiyakul, Daniel Gajski, Loganath Ramachandran
    High-Level Transformations for Minimizing Syntactic Variances. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:413-418 [Conf]
  76. Christos A. Papachristou, Haidar Harmanani, Mehrdad Nourani
    An Approach for Redesigning in Data Path Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:419-423 [Conf]
  77. Andrew Seawright, Forrest Brewer
    High-Level Symbolic Construction Technique for High Performance Sequential Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:424-428 [Conf]
  78. Ramesh Karri, Alex Orailoglu
    High-Level Synthesis of Fault-Secure Microarchitectures. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:429-433 [Conf]
  79. Manjote S. Haworth, William P. Birmingham
    Towards Optimal System-Level Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:434-438 [Conf]
  80. Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri
    NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:439-445 [Conf]
  81. William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Delay Fault Coverage and Performance Tradeoffs. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:446-452 [Conf]
  82. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
    Design for Testability for Path Delay faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:453-457 [Conf]
  83. Brian Chess, Tracy Larrabee
    Bridge Fault simulation strategies for CMOS integrated Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:458-462 [Conf]
  84. June-Kyung Rho, Fabio Somenzi, Carl Pixley
    Minimum Length Synchronizing Sequences of Finite State Machine. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:463-468 [Conf]
  85. Jeffrey J. Joyce, Carl-Johan H. Seger
    Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:469-474 [Conf]
  86. Ramin Hojati, Thomas R. Shiple, Robert K. Brayton, Robert P. Kurshan
    A Unified Approach to Language Containment and Fair CTL Model Checking. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:475-481 [Conf]
  87. William S. Johnson
    Are EDA Platform Preferences About to Shift? (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:482- [Conf]
  88. Srimat T. Chakradhar, Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler
    Sequential Circuit Delay optimization Using Global Path Delays. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:483-489 [Conf]
  89. Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Resynthesis of Multi-Phase Pipelines. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:490-496 [Conf]
  90. Marios C. Papaefthymiou, Keith H. Randall
    TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:497-502 [Conf]
  91. Pi-Yu Chung, Yi-Min Wang, Ibrahim N. Hajj
    Diagnosis and Correction of Logic Design Errors in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:503-508 [Conf]
  92. Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham
    DRAFTS: Discretized Analog Circuit Fault Simulator. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:509-514 [Conf]
  93. Wolfgang Meyer, Raul Camposano
    Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:515-519 [Conf]
  94. Sreejit Chakravarty, Yiming Gong
    An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:520-524 [Conf]
  95. Tsu-chang Lee
    A Bounded 2D Contour Searching Algorithm for Floorplan Design with Arbitrarily Shaped Rectilinear and Soft Modules. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:525-530 [Conf]
  96. Takeo Hamada, Chung-Kuan Cheng, Paul M. Chau
    Prime: A Timing-Driven Placement Tool using A Piecewise Linear Resistive Network Approach. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:531-536 [Conf]
  97. Jun Dong Cho, Majid Sarrafzadeh
    A Nuffer Distribution Algorithm for High-Speed Clock Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:537-543 [Conf]
  98. Masato Mogaki, Youichi Shiraishi, Mitsuyuki Kimura, Tetsuro Hino
    Cooperative Approach to a Practical Analog LSI Layout System. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:544-549 [Conf]
  99. Gopi Ganapathy, Jacob A. Abraham
    Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:550-555 [Conf]
  100. Kenneth W. Wan, Roshan A. Gidwani
    ABLE: AMD Backplane for Layout Engines. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:556-560 [Conf]
  101. Steven G. Duvall
    Practical Statistical Design of Complex Integrated Circuit Products. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:561-565 [Conf]
  102. Liang-Fang Chao, Andrea S. LaPaugh, Edwin Hsing-Mean Sha
    Rotation Scheduling: A Loop Pipelining Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:566-572 [Conf]
  103. Zia Iqbal, Miodrag Potkonjak, Sujit Dey, Alice C. Parker
    Critical Path Minimization Using Retiming and Algebraic Speed-Up. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:573-577 [Conf]
  104. S. H. Huang, Y. L. Jeang, C. T. Hwang, Y. C. Hsu, J. F. Wang
    A Tree-Based Scheduling Algorithm for Control-Dominated Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:578-582 [Conf]
  105. Richard J. Cloutier, Donald E. Thomas
    Synthesis of Pipelined Instruction Set Processors. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:583-588 [Conf]
  106. Michael C. McFarland
    Military to Commercial Conversion: Is it Necessary, Is it Practical, Is it Possible? (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:589- [Conf]
  107. Kei-Yong Khoo, Jason Cong
    An Efficient Multilayer MCM Router Based on Four-Via Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:590-595 [Conf]
  108. Jin Huang, Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh
    An Efficient Timing-Driven Global Routing Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:596-600 [Conf]
  109. Forbes D. Lewis, Wang Chia-Chi Pong
    A Negative Reinforcement Method for PGA Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:601-605 [Conf]
  110. Jason Cong, Kwok-Shing Leung, Dian Zhou
    Performance-Driven Interconnect Design Based on Distributed RC Delay Model. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:606-611 [Conf]
  111. Masato Edahiro
    A Clustering-Based Optimization Algorithm in Zero-Skew Routings. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:612-616 [Conf]
  112. Ronald Collett
    Multi-vendor Tool Integration Experiences (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:617- [Conf]
  113. Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Espresso-Signature: A New Exact Minimizer for Logic Functions. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:618-624 [Conf]
  114. Olivier Coudert, Jean Christophe Madre, Henri Fraisse
    A New Viewpoint on Two-Level Logic Minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:625-630 [Conf]
  115. Maurizio Damiani, Jerry Chih-Yuan Yang, Giovanni De Micheli
    Optimization of Combinational Logic Circuits Based on Compatible Gates. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:631-636 [Conf]
  116. Hans Eveking, Stefan Höreth
    Optimization and Resynthesis of Complex Data-Paths. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:637-641 [Conf]
  117. Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula
    BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:642-647 [Conf]
  118. Peter R. Sutton, Jay B. Brockman, Stephen W. Director
    Design Management Using Dynamically Defined Flows. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:648-653 [Conf]
  119. Mário J. Silva, Randy H. Katz
    Active Documentation: A New Interface for VLSI Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:654-660 [Conf]
  120. Ram Mandayam, Ranga Vemuri
    Performance Specification Using Attributed Grammars. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:661-667 [Conf]
  121. Cristian A. Giumale, Hilary J. Kahn
    An Information Model of Time. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:668-672 [Conf]
  122. Yehuda Kra
    A Cross-Debugging Method for Hardware/Software Co-design Environments. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:673-677 [Conf]
  123. Mattan Kamon, Michael J. Tsuk, Jacob White
    FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:678-683 [Conf]
  124. Tai-Yu Chou, Jay Cosentino, Zoltan J. Cendes
    High-Speed Interconnect Modeling and High-Accuracy Simulation Using SPICE and Finite Element Methods. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:684-690 [Conf]
  125. Mysore Sriram, Sung-Mo Kang
    Fast Approximation of the Transient Response of Lossy Transmision Line Trees. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:691-696 [Conf]
  126. Monjurul Haque, S. Chowdhury
    Analysis and Reliable Design of ECL Circuits with Distributed RLC Interconnections. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:697-701 [Conf]
  127. Hansruedi Heeb, Saila Ponnapalli, Albert E. Ruehli
    Frequency Domain Microwave Modeling Using Retarded Partial Element Equivalent Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:702-706 [Conf]
  128. Valery Yarnikh
    The State of CAD and VLSI in Russia. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:707-708 [Conf]
  129. Yuri Tatarnikov
    The State of VHDL in Russia. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:709-711 [Conf]
  130. Alexander Birger
    The State of Simulation in Russia. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:712-715 [Conf]
  131. Valery M. Mikhov
    The State of EDA in Russian Universities. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:716-719 [Conf]
  132. Andrew T. Yang, Yu Liu, Jack T. Yao, R. R. Daniels
    An Efficient Non-Quasi-Static Diode Model for Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:720-725 [Conf]
  133. Haifang Liao, Wayne Wei-Ming Dai, Rui Wang, Fung-Yuel Chang
    S-Parameter Based Macro Model of Distributed-Lumped Networks Using Exponentially Decayed Polynomial Function. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:726-731 [Conf]
  134. Eli Chiprout, Michel S. Nakhla
    Addressing High-Speed Interconnect Issues in Asymptotic Waveform Evaluation. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:732-736 [Conf]
  135. Chandramouli Visweswariah, Jalal A. Wehbeh
    Incremental Event-Driven Simulation of Digital FET Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:737-741 [Conf]
  136. John A. Darringer
    Where in the World Should CAD Software be Made? (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:742- [Conf]
  137. Charles J. Alpert, Andrew B. Kahng
    Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:743-748 [Conf]
  138. Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien
    Spectral K-Way Ratio-Cut Partitioning and Clustering. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:749-754 [Conf]
  139. Jason Cong, M'Lissa Smith
    A Parallel Bottom-Up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:755-760 [Conf]
  140. Minshine Shih, Ernest S. Kuh
    Quadratic Boolean Programming for Performance-Driven System Partitioning. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:761-765 [Conf]
  141. Romesh Wadhwani
    The Key to EDA Results: Component & Library Management (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:766- [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002