Conferences in DBLP
Pierre G. Paulin , John P. Knight Scheduling and Binding Algorithms for High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] M. Potkonjack , Jan M. Rabaey A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] P. Sadayappan , V. Visvanathan Efficient Sparse Matrix Factorization for Circuit Simulation on Vector Supercomputers. [Citation Graph (0, 0)][DBLP ] Conf ] A. P.-C. Ng , V. Visvanathan A Framework for Scheduling Multi-Rate Circuit Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Odent , Luc J. M. Claesen , Hugo De Man Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] G. D. Adams , Carlo H. Séquin Template Style Considerations for Sea-of-Gates Layout Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Ichiang Lin , David Hung-Chang Du , Steve H.-C. Yen Gate Matrix Layout Synthesis with Two-Dimensional Folding. [Citation Graph (0, 0)][DBLP ] Conf ] David Marple Transistor Size Optimization in the Tailor Layout System. [Citation Graph (0, 0)][DBLP ] Conf ] Osamu Karatsu VLSI Design Language Standardization Effort in Japan. [Citation Graph (0, 0)][DBLP ] Conf ] Rajiv Jain , Kayhan Küçükçakar , Mitch J. Mlinar , Alice C. Parker Experience with ADAM Synthesis System. [Citation Graph (0, 0)][DBLP ] Conf ] Elizabeth D. Lagnese , Donald E. Thomas Architectural Partitioning for System Level Design. [Citation Graph (0, 0)][DBLP ] Conf ] M. Balakrishnan , Peter Marwedel Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] S. Hayati , A. Parker Automatic Production of Controller Specifications from Control and Timing Behavioral Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Larry Soulé , Anoop Gupta Characterization of Parallelism and Deadlocks in Distributed Digital Logic Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Zhicheng Wang , Peter M. Maurer Scheduling High-Level Blocks for Functional Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Saul A. Kravitz , Randal E. Bryant , Rob A. Rutenbar Massively Parallel Switch-Level Simulation: A Feasibility Study. [Citation Graph (0, 0)][DBLP ] Conf ] M. J. Chung , Y. Chung Data Parallel Simulation Using Time-Warp on the Connection Machine. [Citation Graph (0, 0)][DBLP ] Conf ] M. T. Trick , Stephen W. Director LASSIE: Structure to Layout for Behavioral Synthesis Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Wing K. Luk , Alvar A. Dean Multi-Stack Optimization for Data-Path Chip (Microprocessor) Layout. [Citation Graph (0, 0)][DBLP ] Conf ] B. Lokanathan , Edwin Kinnen Performance optimized floor planning by graph planarization. [Citation Graph (0, 0)][DBLP ] Conf ] Mitsuru Igusa , Mark Beardslee , Alberto L. Sangiovanni-Vincentelli ORCA a Sea-of-Gates Place and Route System. [Citation Graph (0, 0)][DBLP ] Conf ] Michael C. McFarland The Social Implications of Computerization: Making the Technology Humane. [Citation Graph (0, 0)][DBLP ] Conf ] William P. Birmingham , Anurag P. Gupta , Daniel P. Siewiorek The MICON System for Computer Design. [Citation Graph (0, 0)][DBLP ] Conf ] Edward A. Lee , E. Goei , H. Heine , W. Ho , S. Bhattacharyya , Jeffery C. Bier , E. Guntvedt GABRIEL: A Design Environment for Programmable DSPs. [Citation Graph (0, 0)][DBLP ] Conf ] A. Kumar , S. Kumar , P. Kulshreshtha , S. Ghose Automatic Synthesis of Microprogrammed Control Units from Behavioral Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] P. Groenveld On Global Wire Ordering for Macro-Cell Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Jan-Ming Ho , Gopalakrishnan Vijayan , C. K. Wong A New Approach to the Rectilinear Steiner Tree Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Naveed A. Sherwani , Jitender S. Deogun A New Heuristic for Single Row Routing Problems. [Citation Graph (0, 0)][DBLP ] Conf ] A. Salz , Mark Horowitz IRSIM: An Incremental MOS Switch-Level Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] David Blaauw , Daniel G. Saab , Robert B. Mueller-Thuns , Jacob A. Abraham , Joseph T. Rahmeh Automatic Generation of Behavioral Models from Switch-Level Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] K. A. Tamura Locating Functional Errors in Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Anthony I. Wasserman CASE Environments for Design Automation. [Citation Graph (0, 0)][DBLP ] Conf ] James Daniell , Stephen W. Director An Object Oriented Approach to CAD Tool Control within a Design Framework. [Citation Graph (0, 0)][DBLP ] Conf ] Claudia S. Frydman , Norbert Giambiasi , M. Gatumel , P. Bayle DeBuMA: Description, Building and Management of Applications. [Citation Graph (0, 0)][DBLP ] Conf ] E. C. VanHorn , Roy R. Rezac Experience with D-BUS Architecture for a Design Automation Framework. [Citation Graph (0, 0)][DBLP ] Conf ] TingTing Hwang , Robert Michael Owens , Mary Jane Irwin Multi-Level Logic Synthesis Using Communication Complexity. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick C. McGeer , Robert K. Brayton Efficient Prime Factorization of Logic Expressions. [Citation Graph (0, 0)][DBLP ] Conf ] Alan J. Coppola New Methods in the Analysis of Logic Minimization Data and Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] C. C. Chen , S.-L. Chow The Layout Synthesizer: An Automatic Netlist-to-Layout System. [Citation Graph (0, 0)][DBLP ] Conf ] Chong-Leong Ong , Jeong-Tyng Li , Chi-Yuan Lo GENAC: An Automatic Cell Synthesis Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Asim J. Al-Khalili , Yong Zhu , Dhamin Al-Khalili A Module Generator for Optimized CMOS Buffers. [Citation Graph (0, 0)][DBLP ] Conf ] Marianne Winslett , David W. Knapp , K. Hall , Gio Wiederhold Use of Change Coordination in an Information-rich Design Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandros Biliris Database Support for Evolving Design Objects. [Citation Graph (1, 0)][DBLP ] Conf ] Mário J. Silva , David Gedye , Randy H. Katz , R. Newton Protection and Versioning for OCT. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Devadas Approaches to Multi-level Sequential Logic Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Saldanha , Albert R. Wang , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Multi-level Logic Simplification Using Don't Cares and Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Goré , Kotagiri Ramamohanarao Automatic Synthesis of Boolean Equations Using Programmable Array Logic. [Citation Graph (0, 0)][DBLP ] Conf ] H. Shin , Chi-Yuan Lo An Efficient Two-Dimensional Layout Compaction Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] J. Waterkamp , R. Wicke , R. Brück , M. Reinhardt , G. Schrammeck Technology Tracking of Non Manhattan VLSI Layout. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Yuan Lo Automatic Tub Region Generation for Symbolic Layout Compaction. [Citation Graph (0, 0)][DBLP ] Conf ] Kurt Keutzer Three Competing Design Methodologies for ASIC's: Architectual Synthesis, Logic Synthesis, Logic Synthesis and Module Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Devadas General Decomposition of Sequential Machines: Relationships to State Assignment. [Citation Graph (0, 0)][DBLP ] Conf ] Gabriele Saucier , C. Duff , F. Poirot State Assignment Using a New Embedding Method Based on an Intersecting Cube Theory. [Citation Graph (0, 0)][DBLP ] Conf ] Tiziano Villa , Alberto L. Sangiovanni-Vincentelli NOVA: State Assignment of Finite State Machines for Optimal Two-level Logic Implementations. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre G. Paulin Horizontal Partitioning of PLA-based Finite State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Patil , Prithviraj Banerjee A Parallel Branch and Bound Algorithm for Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Hyung Ki Lee , Dong Sam Ha , K. Kim Test Generation of Stuck-open Faults Using Stuck-at Test Sets in CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] C. Thomas Glover , M. Ray Mercer A Deterministic Approach to Adjacency Testing for Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Michael H. Schulz , Franz Fink , Karl Fuchs Parallel Pattern Fault Simulation of Path Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Somchai Prasitjutrakul , William J. Kubitz Path-Delay Constrained Floorplanning: A Mathematical Programming Approach for Initial Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Michael A. B. Jackson , Ernest S. Kuh Performance-driven Placement of Cell Based IC's. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Herrigel , Wolfgang Fichtner An Analytic Optimization Technique for Placement of Macro-Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Sarma Sastry , Jen-I Pi An Investigation into Statistical Properties of Partitioning and Floorplanning Problems. [Citation Graph (0, 0)][DBLP ] Conf ] R. H. Bruce , W. P. Meuli , J. Ho Multi Chip Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Bryan Preas , Massoud Pedram , D. Curry Automatic Layout of Silicon-on-Silicon Hybrid Packages. [Citation Graph (0, 0)][DBLP ] Conf ] Ran Libeskind-Hadas , C. L. Liu Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jih-Shyr Yih , Pinaki Mazumder A Neural Network Design for Circuit Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] M. L. Yu A Study of the Applicability of Hopfield Decision Neural Nets to VLSI CAD. [Citation Graph (0, 0)][DBLP ] Conf ] K. Cho , Randal E. Bryant Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Wu-Tung Cheng , Meng-Lin Yu Differential Fault Simulation - a Fast Method Using Minimal Memory. [Citation Graph (0, 0)][DBLP ] Conf ] F. E. Norrod An Automatic Test Generation Algorithm for Hardware Description Languages. [Citation Graph (0, 0)][DBLP ] Conf ] Heh-Tyan Liaw , K.-T. Tran , Chen-Shang Lin VVDS: A Verification/Diagnosis System for VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] Lothar Nowak , Peter Marwedel Verification of Hardware Descriptions by Retargetable Code Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Cyrus Bamji , Jonathan Allen GRASP: A Grammar-based Schematic Parser. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej J. Strojwas Design for Manufacturability and Yield. [Citation Graph (0, 0)][DBLP ] Conf ] Aangelo C. Hung , Philip M. Reddy , Paul J. Hammer MIOS: A Flexible System for PCB Manufacturing. [Citation Graph (0, 0)][DBLP ] Conf ] William D. Smith , David A. Duff , M. Dragomirecky , J. Caldwell , Michael J. Hartman , Jeffrey R. Jasica , Manuel A. d'Abreu FACE Core Environment: The Model and Its Application in CAE/CAD Tool Development. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus D. Müller-Glaser , J. Bortolazzi An Approach to Intelligent Assistance for the Specification of ASIC Design Using Objects and Rules. [Citation Graph (0, 0)][DBLP ] Conf ] Júlio S. Aude , Hilary J. Kahn Representation and Use of Design Rules within a Technology Adaptable CAD System. [Citation Graph (0, 0)][DBLP ] Conf ] Pak K. Chan , Kevin Karplus Computing Signal Delay in General RC Networks by Tree/Link Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Serge Gaiotti , Michel Dagenais , Nicholas C. Rumin Worst-case Delay Estimation of Transistor Groups. [Citation Graph (0, 0)][DBLP ] Conf ] Nagisa Ishiura , M. Takahashi , Shuzo Yajima Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Charles R. Bonapace , Chi-Yuan Lo An O(nlogm) Algorithm for VLSI Design Rule Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Nils Hedenstierna , Kjell O. Jeppson The Use of Inverse Layout Trees for Hierarchical Design Rule Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Ivo Bolsens , W. De Rammelaere , Luc J. M. Claesen , Hugo De Man Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour. [Citation Graph (0, 0)][DBLP ] Conf ] T. Ogihara , K. Muroi , G. Yonemori , S. Murai MULTES/IS: An Effective and Reliable Test Generation System for Partial Scan and Non-Scan Synchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Ben Jone , Christos A. Papachristou A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Ben Jone , Christos A. Papachristou , M. Pereira A Scheme for Overlaying Concurrent Testing of VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] O. A. Buset , Mohamed I. Elmasry ACE: A Hierarchical Graphical Interface for Architectual Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Dorothy E. Setliff , Rob A. Rutenbar ELF: A Tool for Automatic Synthesis of Custom Physical CAD Software. [Citation Graph (0, 0)][DBLP ] Conf ] M. Dragomirecky , Ephraim P. Glinert , Jeffrey R. Jasica , David A. Duff , William D. Smith , Manuel A. d'Abreu High-Level Graphical User Interface Management in the FACE Synthesis Environment. [Citation Graph (0, 0)][DBLP ] Conf ] David Hung-Chang Du , S. H. Yen , Subbarao Ghanta On the General False Path Problem in Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick C. McGeer , Robert K. Brayton Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network. [Citation Graph (0, 0)][DBLP ] Conf ] S. Perremans , Luc J. M. Claesen , Hugo De Man Static Timing Analysis of Dynamically Sensitizable Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Carol V. Gura , Jacob A. Abraham Average Interconnection Length and Interconnection Distribution Based on Rent's Rule. [Citation Graph (0, 0)][DBLP ] Conf ] Xueqing Zhang , Lawrence T. Pillage , Ronald A. Rohrer Efficient Final Placement Based on Nets-as-Points. [Citation Graph (0, 0)][DBLP ] Conf ] Marwan A. Jabri , David J. Skellern PIAF: A Knowledge-based/Algorithm Top-Down Floorplanning System. [Citation Graph (0, 0)][DBLP ] Conf ] D. F. Wong , P. S. Sakhamuri Efficient Floorplan Area Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Jeff S. Sargent , Prithviraj Banerjee A Parallel Row-based Algorithm for Standard Cell Placement with Integrated Error Control. [Citation Graph (0, 0)][DBLP ] Conf ] John D. Gabbe , P. A. Subrahmanyam A Note on Clustering Modules for Floorplanning. [Citation Graph (0, 0)][DBLP ] Conf ] David Knapp An Interactive Tool for Register-level Structure Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Nam Sung Woo , H. Shin A Technology-adaptive Allocation of Functional Units and Connections. [Citation Graph (0, 0)][DBLP ] Conf ] Joseph Lis , Daniel Gajski VHDL Synthesis Using Structured Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] William P. Birmingham , Daniel P. Siewiorek Capturing Designer Expertise the CGEN System. [Citation Graph (0, 0)][DBLP ] Conf ] D. L. Hwang , T. L. Wernimont , W. Kent Fuchs Evaluation of a Reconfigurable Architecture for Digital Beamforming Using the OODRA Workbench. [Citation Graph (0, 0)][DBLP ] Conf ] M. Rumsey , J. Sackett An ASIC Methodology for Mixed Analog-Digital Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] R. F. Milsom , K. J. Scott , S. G. Clark , J. C. McEntegart , S. Ahmed , F. N. Soper FACET: A CAE System for RF Analogue Simulation Including Layout. [Citation Graph (0, 0)][DBLP ] Conf ] Zhiping Yu , Weijian Zhao , Zhilian Yang , Y. Edmund Lien A Novel Algorithm for Improving Convergence Behavior of Circuit Simulators. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew T. Yang , S. M. Kang iSMILE: A Novel Circuit Simulation Program with Emphasis on New Device Model Development. [Citation Graph (0, 0)][DBLP ] Conf ] Lawrence T. Pillage , Xueqing Huang , Ronald A. Rohrer AWEsim: Asymptotic Waveform Evaluation for Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Kaushik Roy , Jacob A. Abraham A Novel Approach to Accurate Timing Verification Using RTL Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] A. K. George Evaluating Hardware Models in DIGITAL's System Simulation Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Prathima Agrawal , R. Tutundjian , William J. Dally Algorithms for Accuracy Enhancement in a Hardware Logic Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] S. H. Yen , David Hung-Chang Du , Subbarao Ghanta Efficient Algorithms for Extracting the K most Critical Paths in Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] N. Weiner , Alberto L. Sangiovanni-Vincentelli Timing Analysis in a Logic Synthesis Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Jacques Wenin , Johan Verhasselt , Marc Van Camp , Jean Leonard , Pierre Guebels Rule-based VLSI Verification System Constrained by Layout Parasitics. [Citation Graph (0, 0)][DBLP ] Conf ] Jacques Benkoski , Andrzej J. Strojwas Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Narasimha B. Bhat , S. K. Nandy Special Purpose Architecture for Accelerating Bitmap DRC. [Citation Graph (0, 0)][DBLP ] Conf ] N. P. van der Meijs , A. J. van Genderen An Efficient Finite Element Method for Submicron IC Capacitance Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Kuang-Wei Chiang Resistance Extraction and Resistance Calculation in GOALIE? [Citation Graph (0, 0)][DBLP ] Conf ] L. Stok , G. P. Koster From Network to Artwork. [Citation Graph (0, 0)][DBLP ] Conf ] W.-J. Lue , Lawrence P. McNamee Extracting Schematic-like Information from CMOS Circuit Net-lists. [Citation Graph (0, 0)][DBLP ] Conf ] I. Vandeweerd , Kris Croes , Luc Rijnders , Paul Six , Hugo De Man REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Mary Jane Irwin , Robert Michael Owens A Comparison of Four Two-dimensional Gate Matrix Layout Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Knut M. Just , Werner L. Schiele , Th. Krüger Plowing: Modifying Cells and Routing 45: 9D - Layouts. [Citation Graph (0, 0)][DBLP ] Conf ] T. Ghewala CrossCheck: A Cell Based VLSI Testability Solution. [Citation Graph (0, 0)][DBLP ] Conf ] V. G. Hemmady , Sudhakar M. Reddy On the Repair of Redundant RAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Rochit Rajsuman , Anura P. Jayasumana , Yashwant K. Malaiya CMOS Stuck-open Fault Detection Using Single Test Patterns. [Citation Graph (0, 0)][DBLP ] Conf ] Bulent I. Dervisoglu , M. A. Keil ATLAS/ELA: Scan-based Software Tools for Reducing System Debug Time in a State-of-the-art Workstation. [Citation Graph (0, 0)][DBLP ] Conf ] U. J. Davé , Janak H. Patel A Functional-Level Test Generation Methodology Using Two-level Representations. [Citation Graph (0, 0)][DBLP ] Conf ] J. F. Wang , T. Y. Kuo , J. Y. Lee A New Approach to Derive Robust Sets for Stuck-open Faults in CMOS Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Weiwei Mao , Michael D. Ciletti A Simplified Six-waveform Type Method for Delay Fault Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Vinod Narayanan , Vijay Pitchumani A Massively Parallel Algorithm for Fault Simulation on the Connection Machine. [Citation Graph (0, 0)][DBLP ] Conf ] A. J. van der Hoeven , A. A. de Lange , Ed F. Deprettere , Patrick Dewilde A New Model for the High Level Description and Simulation of VLSI Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Walling R. Cyre Toward Synthesis from English Descriptions. [Citation Graph (1, 0)][DBLP ] Conf ] Steven S. Leung Behavioral Modeling of Transmission Gates in VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] Paul R. Jordan , Ronald D. Williams COMP: A VHDL Composition System. [Citation Graph (0, 0)][DBLP ] Conf ] Nikil D. Dutt , Daniel Gajski Designer Controlled Behavioral Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] J. Blanks Partitioning by Probability Condensation. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng Fast Hypergraph Partition. [Citation Graph (0, 0)][DBLP ] Conf ] Youssef Saab , Vasant B. Rao An Evolution-Based Approach to Partitioning ASIC Systems. [Citation Graph (0, 0)][DBLP ] Conf ] G. Vijayan Min-cost Partitioning on a Tree Structure and Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Thang Bui , C. Heigham , C. Jones , Frank Thomson Leighton Improving the Performance of the Kernighan-Lin and Simulated Annealing Graph Bisection Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] S. Ganguly , Vijay Pitchumani Compaction of a Routed Channel on the Connection Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Rajiv Dutta , Malgorzata Marek-Sadowska Automatic Sizing of Power/Ground (P/G) Networks in VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] S. Chowdhury Optimum Design of Reliable IC Power Networks Having General Graph Topologies. [Citation Graph (0, 0)][DBLP ] Conf ] Yasuyuki Fujihara , Yutaka Sekiyama , Y. Ishibashi , M. Yanaka DYNAJUST: An Efficient Automatic Routing Technique Optimizing Delay Conditions. [Citation Graph (0, 0)][DBLP ] Conf ] Anucha Pitaksanonkul , Suchai Thanawastien , Chidchanok Lursinsap , J. A. Gandhi DTR: A Defect-Tolerant Routing Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Khe-Sing The , D. F. Wong , Jason Cong VIA Minimization by Layout Modification. [Citation Graph (0, 0)][DBLP ] Conf ] W. Li , H. Switzer A Unified Data Exchange Environment Based on EDIF. [Citation Graph (0, 0)][DBLP ] Conf ] J. Miller , K. Groning , G. Schulz , C. White The Object-Oriented Integration Methodology of the Cadlab Work Station Design Environment. [Citation Graph (1, 0)][DBLP ] Conf ] P. Kollaritsch , S. Lusky , D. Matzke , D. Smith , P. Stanford A Unified Design Representation Can Work. [Citation Graph (0, 0)][DBLP ] Conf ] Ernst Siepmann , Gerhard Zimmermann An Object-Oriented Datamodel for the VLSI Design System PLAYOUT. [Citation Graph (0, 0)][DBLP ] Conf ] M. Roberts CEDIF: A Data Driven EDIF Reader. [Citation Graph (0, 0)][DBLP ] Conf ] L. G. Jones Fast Online/Offline Netlist Compilation of Hierarchical Schematics. [Citation Graph (0, 0)][DBLP ] Conf ] Gert Goossens , Joos Vandewalle , Hugo De Man Loop Optimization in Register-Transfer Scheduling for DSP-Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroto Yasuura , Nagisa Ishiura Semantics of a Hardware Design Language for Japanese Standardization. [Citation Graph (0, 0)][DBLP ] Conf ] 