Conferences in DBLP
Robert M. Williams IBM perspectives on the electrical design automation industry (keynote address). [Citation Graph (0, 0)][DBLP ] Conf ] Robert J. Smith II Fundamentals of parallel logic simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth F. Wong , Mark A. Franklin , Roger D. Chamberlain , B. L. Shing Statistics on logic simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Edward H. Frank Exploiting parallelism in a switch-level simulation machine. [Citation Graph (0, 0)][DBLP ] Conf ] Randy H. Katz , M. Anwarrudin , Ellis E. Chang A version server for computer-aided design data. [Citation Graph (0, 0)][DBLP ] Conf ] Dominique Rieu , Gia Toan Nguyen Semantics of CAD objects for generalized databases. [Citation Graph (0, 0)][DBLP ] Conf ] Shlomo Weiss , Katie Rotzell , Tom Rhyne , Arny Goldfein DOSS: a storage system for design data. [Citation Graph (0, 0)][DBLP ] Conf ] David Knapp , Alice C. Parker A design utility manager: the ADAM planning engine. [Citation Graph (0, 0)][DBLP ] Conf ] Michael L. Bushnell , Stephen W. Director VLSI CAD tool integration using the Ulysses environment. [Citation Graph (0, 0)][DBLP ] Conf ] Forrest Brewer , Daniel Gajski An expert-system paradigm for design. [Citation Graph (0, 0)][DBLP ] Conf ] J. M. Hancock , S. DasGupta Tutorial on parallel processing for design automation applications (tutorial session). [Citation Graph (0, 0)][DBLP ] Conf ] Aart J. de Geus Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference. [Citation Graph (0, 0)][DBLP ] Conf ] David Gregory , Karen A. Bartlett , Aart J. de Geus , Gary D. Hachtel SOCRATES: a system for automatically synthesizing and optimizing combinational logic. [Citation Graph (0, 0)][DBLP ] Conf ] Tsutomu Sasao MACDAS: multi-level AND-OR circuit synthesis using two-variable function generators. [Citation Graph (0, 0)][DBLP ] Conf ] William H. Joyner Jr. , Louise Trevillyan , Daniel Brand , Theresa A. Nix , Steven C. Gundersen Technology adaption in logic synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] D. F. Wong , C. L. Liu A new algorithm for floorplan design. [Citation Graph (0, 0)][DBLP ] Conf ] Jayaram Bhasker , Sartaj Sahni A linear algorithm to find a rectangular dual of a planar triangulated graph. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunchul Shin , Alberto L. Sangiovanni-Vincentelli , Carlo H. Séquin Two-dimensional compaction by ``zone refining''. [Citation Graph (0, 0)][DBLP ] Conf ] Sching L. Lin , Jonathan Allen Minplex - a compactor that minimizes the bounding rectangle and individual rectangles in a layout. [Citation Graph (0, 0)][DBLP ] Conf ] Venkat V. Venkataraman , Craig D. Wilcox GEMS: an automatic layout tool for MIMOLA schematics. [Citation Graph (0, 0)][DBLP ] Conf ] Akira Sugimoto , Shigeru Abe , Masahiro Kuroda , Yukio Kato An object-oriented visual simulator for microprogram development. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto Di Janni A monitor for complex CAD systems. [Citation Graph (0, 0)][DBLP ] Conf ] Katherine Hammer , Dan Radin , Tom Rhyne , John Hardin , Tina Timmerman Automating the generation of interactive interfaces. [Citation Graph (0, 0)][DBLP ] Conf ] Dan Adler SIMMOS: a multiple-delay switch-level simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Zeev Barzilai , Daniel K. Beece , Leendert M. Huisman , Vijay S. Iyengar , Gabriel M. Silberman SLS - a fast switch level simulator for verification and fault coverage analysis. [Citation Graph (0, 0)][DBLP ] Conf ] William S. Beckett MOS circuit models in Network C. [Citation Graph (0, 0)][DBLP ] Conf ] Luís M. Vidigal , Sani R. Nassif , Stephen W. Director CINNAMON: coupled integration and nodal analysis of MOS networks. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Odryna , Kevin Nazareth , Carl Christensen A workstation-mixed model circuit simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Y. S. Kuo , W. K. Chou Generating essential primes for a Boolean function with multiple-valued inputs. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth J. Supowit , Steven J. Friedman A new method for verifying sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Gotaro Odawara , Masahiro Tomita , Osamu Okuzawa , Tomomichi Ohta , Zhen-quan Zhuang A logic verifier based on Boolean comparison. [Citation Graph (0, 0)][DBLP ] Conf ] S. Bapat , G. Venkatesh Reasoning about digital systems using temporal logic. [Citation Graph (0, 0)][DBLP ] Conf ] Manfred Glesner , Johannes Schuck , R. B. Steck SCAT - a new statistical timing verifier in a silicon compiler system. [Citation Graph (0, 0)][DBLP ] Conf ] Seung Ho Hwang , Young hwan Kim , A. Richard Newton An accuration delay modeling technique for switch-level timing verification. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej J. Strojwas , Clark Beck , Dennis Buss , Tülin Erdim Mangir , Charles H. Stapper Yield of VLSI circuits: myths vs. reality (panel). [Citation Graph (0, 0)][DBLP ] Conf ] Weiwei Mao , Xieting Ling Robust test generation algorithm for stuck-open fault in CMOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hsi-Ching Shih , Jacob A. Abraham Transistor-level test generation for physical failures in CMOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ralph Marlett An effective test generation system for sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel S. Barclay , James R. Armstrong A heuristic chip-level test generation algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre G. Paulin , John P. Knight , Emil F. Girczyc HAL: a multi-paradigm approach to automatic data path synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Marwedel A new synthesis for the MIMOLA software system. [Citation Graph (0, 0)][DBLP ] Conf ] Zebo Peng Synthesis of VLSI systems with the CAMAD design aid. [Citation Graph (0, 0)][DBLP ] Conf ] R. Brück , Bernd Kleinjohann , Thomas Kathöfer , Franz J. Rammig Synthesis of concurrent modular controllers from algorithmic descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Surendra Nahar , Sartaj Sahni , Eugene Shragowitz Simulated annealing and combinatorial optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Antoni A. Szepieniec Integrated placement/routing in sliced layouts. [Citation Graph (0, 0)][DBLP ] Conf ] Knut M. Just , Jürgen M. Kleinhans , Frank M. Johannes On the relative placement and the transportation problem for standard-cell layout. [Citation Graph (0, 0)][DBLP ] Conf ] Mark R. Hartoog Analysis of placement procedures for VLSI standard cell layout. [Citation Graph (0, 0)][DBLP ] Conf ] Moe Shahdad An overview of VHDL language and technology. [Citation Graph (0, 0)][DBLP ] Conf ] John P. Eurich A tutorial introduction to the electronic design interchange format (tutorial session). [Citation Graph (0, 0)][DBLP ] Conf ] Wilfried Daehn A unified treatment of PLA faults by Boolean differences. [Citation Graph (0, 0)][DBLP ] Conf ] Michiel M. Ligthart , Emile H. L. Aarts , Frans P. M. Beenker Design-for-testability of PLA's using statistical cooling. [Citation Graph (0, 0)][DBLP ] Conf ] M. Ladjadj , J. F. McDonald , D.-H. Ho , W. Murray Use of the subscripted DALG in submodule testing with applications in cellular arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Yasuhiro Ohno , Masayuki Miyoshi , Norio Yamada , Toshihiko Odaka , Tokinori Kozawa , Kooichiro Ishihara Principles of design automatioon system for very large scale computer design. [Citation Graph (0, 0)][DBLP ] Conf ] Masayuki Miyoshi , Yoshio Ooshima , Atsushi Sugiyama , Nobuhiko Onizuka , Nobutaka Amano An extensive logic simulation method of very large scale computer design. [Citation Graph (0, 0)][DBLP ] Conf ] Yooji Tsuchiya , Masato Morita , Yukio Ikariya , Eiichi Tsurumi , Teruo Mori , Tamoatsu Yanagita Establishment of higher level logic design for very large scale computer. [Citation Graph (0, 0)][DBLP ] Conf ] Roger J. Pachter , R. Smith , Ronald Waxman , J. Hines , H. G. Adhead , L. O'Connell , M. Shahdad , John P. Eurich Computer aided (CA) tools integration and related standards development (panel session). [Citation Graph (0, 0)][DBLP ] Conf ] David R. Tryon Self-testing with correlated faults. [Citation Graph (0, 0)][DBLP ] Conf ] Gerd Krüger Automatic generation of self-test programs - a new feature of the MIMOLA design system. [Citation Graph (0, 0)][DBLP ] Conf ] Sy-Yen Kuo , W. Kent Fuchs Efficient spare allocation in reconfigurable arrays. [Citation Graph (0, 0)][DBLP ] Conf ] T. Shinsha , T. Kubo , Y. Sakataya , J. Koshishita , K. Ishihara Incremental logic synthesis through gate logic structure identification. [Citation Graph (0, 0)][DBLP ] Conf ] Reiji Toyoshima , Yoshimitsu Takiguchi , Kazumi Matsumoto , Hidetomo Hongou , Mashiro Hashimoto , Ryotaro Kamikawai , Katsuhiko Takizawa An effective delay analysis system for a large scale computer design. [Citation Graph (0, 0)][DBLP ] Conf ] Yasushi Ogawa , Tatsuki Ishii , Yoichi Shiraishi , Hidekazu Terai , Tokinori Kozawa , Kyoji Yuyama , Kyoji Chiba Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs. [Citation Graph (0, 0)][DBLP ] Conf ] Surendra Nahar , Sartaj Sahni A time and space efficient net extractor. [Citation Graph (0, 0)][DBLP ] Conf ] R. D. Freeman , S. M. Kang , C. G. Lin-Hendel , M. L. Newby Automated extraction of SPICE circuit models from symbolic gate matrix layout with pruning. [Citation Graph (0, 0)][DBLP ] Conf ] Ahsan Bootehsaz , Robert A. Cottrel A technology independent approach to hierarchical IC layout extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Carl Sechen , Alberto L. Sangiovanni-Vincentelli TimberWolf3.2: a new standard cell placement and global routing package. [Citation Graph (0, 0)][DBLP ] Conf ] Peter S. Hauge , Ellen J. Yoffa Vanguard: a chip physical design system. [Citation Graph (0, 0)][DBLP ] Conf ] David E. Krekelberg , Eugene Shragowitz , Gerald E. Sobelman , Li-Shin Lin Automated layout synthesis in the YASC silicon compiler. [Citation Graph (0, 0)][DBLP ] Conf ] Nohbyung Park , Alice C. Parker Sehwa: a program for synthesis of pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Alice C. Parker , Jorge T. Pizarro , Mitch J. Mlinar MAHA: a program for datapath synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Fadi J. Kurdahi , Alice C. Parker PLEST: a program for area estimation of VLSI integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Michael C. McFarland Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] W. K. Luk , Donald T. Tang , C. K. Wong Hierarchial global wiring for custom chip design. [Citation Graph (0, 0)][DBLP ] Conf ] Charles H. Ng An industrial world channel router for non-rectangular channels. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas Braun , Jeffrey L. Burns , Srinivas Devadas , Hi-Keung Tony Ma , Kartikeya Mayaram , Fabio Romeo , Alberto L. Sangiovanni-Vincentelli Chameleon: a new multi-layer channel router. [Citation Graph (0, 0)][DBLP ] Conf ] Alex Orailoglu , Daniel Gajski Flow graph representation. [Citation Graph (0, 0)][DBLP ] Conf ] Júlio S. Aude , Hilary J. Kahn A design rule database system to support technology-adaptable applications. [Citation Graph (0, 0)][DBLP ] Conf ] John Ivie , Kwok-Woon Larry Lai STL - a high level language for simulation and test. [Citation Graph (0, 0)][DBLP ] Conf ] Jon A. Solworth GENERIC: a silicon compiler support language. [Citation Graph (0, 0)][DBLP ] Conf ] William P. Birmingham , Rostam Joobbani , Jin Kim Knowlege-based expert systems and their application (tutorial session. [Citation Graph (0, 0)][DBLP ] Conf ] Hans-Joachim Wunderlich , Wolfgang Rosenstiel On fault modeling for dynamic MOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay J. Patel , Janak H. Patel Effectiveness of heuristics measures for automatic test pattern generation. [Citation Graph (0, 0)][DBLP ] Conf ] Hi-Keung Tony Ma , Alberto L. Sangiovanni-Vincentelli Mixed-level fault coverage estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Wojciech Maly Optimal order of the VLSI IC testing sequence. [Citation Graph (0, 0)][DBLP ] Conf ] Saul A. Kravitz , Rob A. Rutenbar Multiprocessor-based placement by simulated annealing. [Citation Graph (0, 0)][DBLP ] Conf ] Takumi Watanabe , Yoshi Sugiyama A new routing algorithm and its hardware implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Shigeru Takasaki , Tohru Sasaki , Nobuyoshi Nomizu , Hiroshi Ishikura , Nobuhiko Koike HAL II: a mixed level hardware logic simulation system. [Citation Graph (0, 0)][DBLP ] Conf ] George K. Jacob , A. Richard Newton , Donald O. Pederson An empirical analysis of the performance of a multiprocessor-based circuit simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Takao Saito , Hiroyuki Sugimoto , Masami Yamazaki , Nobuaki Kawato A rule-based logic circuit synthesis system for CMOS gate arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Watanabe , Bryan D. Ackland Flute - a floorplanning agent for full custom VLSI design. [Citation Graph (0, 0)][DBLP ] Conf ] T. Watanabe , T. Masuishi , T. Nishiyama , N. Horie Knowledge-based optimal IIL generator from conventional logic circuit descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Edward J. DeJesus , James P. Callan , Curtis R. Whitehead PEARL: an expert system for power supply layout. [Citation Graph (0, 0)][DBLP ] Conf ] Bryan Preas , Patrick G. Karger Automatic placement a review of current techniques (tutorial session). [Citation Graph (0, 0)][DBLP ] Conf ] Howard S. Rifkin , William Heller , Steve Law , Misha Burich , Alberto L. Sangiovanni-Vincentelli Floor planning systems (panel session). [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Devadas , A. Richard Newton GENIE: a generalized array optimizer for VLSI synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Christine M. Gerveshi Comparison of CMOS PLA and polycell representations of control logic. [Citation Graph (0, 0)][DBLP ] Conf ] Alan J. Coppola An implementation of a state assignment heuristic. [Citation Graph (0, 0)][DBLP ] Conf ] Edmund M. Clarke , Yulin Feng Escher - a geometrical layout system for recursively defined circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Patrice Frison , Eric Gautrin MADMACS: a new VLSI layout macro editor. [Citation Graph (0, 0)][DBLP ] Conf ] Antony P.-C. Ng , Clark D. Thompson , Prabhakar Raghavan A language for describing rectilinear Steiner tree configurations. [Citation Graph (0, 0)][DBLP ] Conf ] S. K. Nandy , L. V. Ramakrishnan Dual quadtree representation for VLSI designs. [Citation Graph (0, 0)][DBLP ] Conf ] Richard H. Lathrop , Robert S. Kirk Precedent-based manipulation of VLSI structures. [Citation Graph (0, 0)][DBLP ] Conf ] W. Stephen Adolph , Hassan K. Reghbati , Amar Sanmugasunderam A frame based system for representing knowledge about VLSI design: a proposal. [Citation Graph (0, 0)][DBLP ] Conf ] Sumit Ghosh A rule-based approach to unifying functional and fault simulation and timing verification. [Citation Graph (0, 0)][DBLP ] Conf ] David E. Wallace , Carlo H. Séquin Plug-in timing models for an abstract timing verifier. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan D. Pincus , Alvin M. Despain Delay reduction using simulated annealing. [Citation Graph (0, 0)][DBLP ] Conf ] J. Fernando Naveda , K. C. Chang , David Hung-Chang Du A new approach to multi-layer PCB routing with short vias. [Citation Graph (0, 0)][DBLP ] Conf ] K. C. Chang , David Hung-Chang Du A preprocessor for the via minimization problem. [Citation Graph (0, 0)][DBLP ] Conf ] Richard J. Enbody , David Hung-Chang Du Near-optimal n -layer channel routing. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed Amine Jerraya , P. Varinot , R. Jamier , Bernard Courtois Principles of the SYCO compiler. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Marshburn , Ivy Lui , Rick Brown , Dan Cheung , Gary Lum , Peter Cheng DATAPATH: a CMOS data path silicon assembler. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Six , Luc J. M. Claesen , Jan M. Rabaey , Hugo De Man An intelligent module generator environment. [Citation Graph (0, 0)][DBLP ] Conf ] Rathin Putatunda , David Smith , Stephen McNeary , James Crabbe HAPPI: a chip compiler based on double-level-metal technology. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Wolf An object-oriented, procedural database for VLSI chip planning. [Citation Graph (0, 0)][DBLP ] Conf ] J. Gonzalez-Sustaeta , Alejandro P. Buchmann An automated database design tool using the ELKA conceptual model. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Jullien , Andre Leblond , Jacques Lecourvoisier A database interface for an integrated CAD system. [Citation Graph (0, 0)][DBLP ] Conf ] Robert P. Larsen Rules-based object clustering: a data structure for symbolic VLSI synthesis and analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Robert E. Canright Simulating and controlling the effects of transmission line impedance mismatches. [Citation Graph (0, 0)][DBLP ] Conf ] Kuniaki Kishida , F. Shirotori , Y. Ikemoto , Shun Ishiyama , Terumine Hayashi A delay test system for high speed logic LSI's. [Citation Graph (0, 0)][DBLP ] Conf ] Toshihiko Tada , Akihiko Hanafusa Router system for printed wiring boards of very high-speed, very large-scale computers. [Citation Graph (0, 0)][DBLP ] Conf ] John Kessenich , Gary Jackoway Global forced hierarchical router. [Citation Graph (0, 0)][DBLP ] Conf ] Kaoru Kawamura , Masanobu Umeda , Hiroshi Shiraishi Hierarchical dynamic router. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay S. Bobba , J. W. Smith A parameter-driven router. [Citation Graph (0, 0)][DBLP ] Conf ] Pat Lamey Early verification of prototype tooling for IC designs. [Citation Graph (0, 0)][DBLP ] Conf ] J. G. Xiong Algorithms for global routing. [Citation Graph (0, 0)][DBLP ] Conf ] 