Conferences in DBLP
Tariq Samad , Stephen W. Director Towards a natural language interface for CAD. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto Di Janni , Margherita Italiano Unified user interface for a CAD system. [Citation Graph (0, 0)][DBLP ] Conf ] Cyrus Bamji , Charles E. Hauck , Jonathan Allen A design by example regular structure generator. [Citation Graph (0, 0)][DBLP ] Conf ] S. C. Hughes , D. B. Lewis , C. J. Rimkus A technique for distributed execution of design automation tools. [Citation Graph (0, 0)][DBLP ] Conf ] Ellen J. Yoffa , Peter S. Hauge ACORN: a local customization approach to DCVS physical design. [Citation Graph (0, 0)][DBLP ] Conf ] Tak-Kwong Ng , S. Lennart Johnsson Generation of layouts from MOS circuit schematics: a graph theoretic approach. [Citation Graph (0, 0)][DBLP ] Conf ] Shigeo Noda , Hitoshi Yoshizawa , Etsuko Fukuda , Haruo Kato , Hiroshi Kawanishi , Takashi Fujii Automatic layout algorithms for function blocks of CMOS gate arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Gabriele Saucier , Ghislaine Thuau Systematic and optimized layout of MOS cells. [Citation Graph (0, 0)][DBLP ] Conf ] C. Durward Rogers , Jonathan B. Rosenberg , Stephen W. Daniel MCNC's vertically integrated symbolic design system. [Citation Graph (0, 0)][DBLP ] Conf ] George Entenman , Stephen W. Daniel A fully automatic hierarchical compactor. [Citation Graph (0, 0)][DBLP ] Conf ] Phillip Smtih , Stephen W. Daniel The VIVID system approach to technology independence: the matster technology file system. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan B. Rosenberg Auto-interactive schematics to layout translation. [Citation Graph (0, 0)][DBLP ] Conf ] Al Lowenstein , Greg Winter Importance of standards (tutorial session). [Citation Graph (0, 0)][DBLP ] Conf ] Roger J. Pachter Computer aided (CA) tools integration and related standards development in a multi-vendor universe (panel session). [Citation Graph (0, 0)][DBLP ] Conf ] John A. Pierro , George F. Donnellan Mechanical design/analysis integration on Apollo workstations. [Citation Graph (0, 0)][DBLP ] Conf ] Raj Abraham Custom microcomputers for CAD optimization software. [Citation Graph (0, 0)][DBLP ] Conf ] Yehuda E. Kalay A database management approach to CAD/CAM systems integration. [Citation Graph (0, 0)][DBLP ] Conf ] Malgorzata Marek-Sadowska Two-dimensional router for double layer layout. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Burstein , Mary N. Youssef Timing influenced layout design. [Citation Graph (0, 0)][DBLP ] Conf ] J. N. Song , Y. K. Chen An algorithm for one and half layer channel routing. [Citation Graph (0, 0)][DBLP ] Conf ] B. Hennion , P. Senn , D. Coquelle A new algorithm for third generation circuit simulators: the one-step relaxation method. [Citation Graph (0, 0)][DBLP ] Conf ] Mark D. Matson Macromodeling of digital MOS VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Michiaki Muraoka , Hirokazu Iida , Hideyuki Kikuchihara , Michio Murakami , Kazuyuki Hirakawa ACTAS: an accurate timing analysis system for VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Cecelia Jankowski Engineering workstation applications to systems design (panel session): life above the IC. [Citation Graph (0, 0)][DBLP ] Conf ] J. P. Simmons Jr. Early verification of prototype tooling for IC designs (tutorial). [Citation Graph (0, 0)][DBLP ] Conf ] Steven T. Healey , Daniel D. Gajski Decomposition of logic networks into silicon. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher Rowen , John L. Hennessy SWAMI: a flexible logic implementation system. [Citation Graph (0, 0)][DBLP ] Conf ] David E. Krekelberg , Gerald E. Sobelman , Chu S. Jhon Yet another silicon compiler. [Citation Graph (0, 0)][DBLP ] Conf ] José Monteiro da Mata ALLENDE: a procedural language for the hierarchical specification of VLSI layouts. [Citation Graph (0, 0)][DBLP ] Conf ] H. S. Fung , S. Hirschhorn , R. Kulkarni Design for testability in a silicon compilation environment. [Citation Graph (0, 0)][DBLP ] Conf ] Ruey-Sing Wei , Alberto L. Sangiovanni-Vincentelli PLATYPUS: a PLA test pattern generation tool. [Citation Graph (0, 0)][DBLP ] Conf ] Hans-Joachim Wunderlich PROTEST: a tool for probabilistic testability analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Takuji Ogihara , Shuichi Saruyama , Shinichi Murai PATEGE: an automatic DC parametric test generation system for series gated ECL circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Prathima Agrawal , Frederick L. Cohen , Chet A. Palesko , Hung-Fai Stephen Law , Mark Miller , Mike Price , David W. Smith , Nicholas P. Van Brunt Workstations (panel discussion): a complete solution to the VLSI designer? [Citation Graph (0, 0)][DBLP ] Conf ] Francine S. Frome Course, video, and manual dexterity (tutorial): tailoring training to CAD users. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy Blackman , Jeffrey Fox , Christopher Rosebrugh The Silc silicon compiler: language and features. [Citation Graph (0, 0)][DBLP ] Conf ] F. Meshkinpour , Milos D. Ercegovac A functional language for description and design of digital systems: sequential constructs. [Citation Graph (0, 0)][DBLP ] Conf ] Warren E. Cory Layla: a VLSI layout language. [Citation Graph (0, 0)][DBLP ] Conf ] Thaddeus J. Kowalski , Donald E. Thomas The VLSI design automation assistant: what's in a knowledge base. [Citation Graph (0, 0)][DBLP ] Conf ] Melvin A. Breuer , Xi-an Zhu A knowledge based system for selecting a test methodology for a PLA. [Citation Graph (0, 0)][DBLP ] Conf ] Rostam Joobbani , Daniel P. Siewiorek WEAVER: a knowledge-based routing expert. [Citation Graph (0, 0)][DBLP ] Conf ] Neil Bergmann Generalised CMOS-a technology independent CMOS IC design style. [Citation Graph (0, 0)][DBLP ] Conf ] Kung-Chao Chu , Y. Edmund Lien Technology tracking for VLSI layout design tools. [Citation Graph (0, 0)][DBLP ] Conf ] Walter S. Scott , John K. Ousterhout Magic's circuit extractor. [Citation Graph (0, 0)][DBLP ] Conf ] Louis Scheffer , Ronny Soetarman Hierarchical analysis of IC artwork with user defined abstraction rules. [Citation Graph (0, 0)][DBLP ] Conf ] George E. Bier , Andrew R. Pleszkun An algorithm for design rule checking on a multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Erich Barke Resistance calculation from mask artwork data by finite element method. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas R. Smith A data architecture for an uncertain design and manufacturing environment. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej J. Strojwas CMU-CAM system. [Citation Graph (0, 0)][DBLP ] Conf ] Keith S. Reid-Green Cost-effective computer-aided manufacturing of prototype parts. [Citation Graph (0, 0)][DBLP ] Conf ] Kai-Hsiung Chang , William G. Wee A knowledge based planning system for mechanical assembly usign robots. [Citation Graph (0, 0)][DBLP ] Conf ] Susan L. Taylor , Roderic Beresford , Theodore Sabety Layout design-lessons from the Jedi designer (tutorial session). [Citation Graph (0, 0)][DBLP ] Conf ] Winfried Hahn , Kristian Fischer MuSiC: an event-flow computer for fast simulation of digital systems. [Citation Graph (0, 0)][DBLP ] Conf ] David M. Lewis A hardware engine for analogue mode simulation of MOS digital circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick M. Hefferan , Robert J. Smith II , Val Burdick , Donald L. Nelson The STE-264 accelerated electronic CAD system. [Citation Graph (0, 0)][DBLP ] Conf ] Philip M. Spira , Carl Hage Hardware acceleration of gate array layout. [Citation Graph (0, 0)][DBLP ] Conf ] Jayanth V. Rajan , Donald E. Thomas Synthesis by delayed binding of decisions. [Citation Graph (0, 0)][DBLP ] Conf ] Robert L. Blackburn , Donald E. Thomas Linking the behavioral and structural dominis of representation in a synthesis system. [Citation Graph (0, 0)][DBLP ] Conf ] Kumar Ramayya , Anshul Kumar , Surendra Prasad An automated data path synthesizer for a canonic structure, implementable in VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Anjali Arya , Anshul Kumar , V. V. Swaminathan , Amit Misra Automatic generation of digital system schematic diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Eric Cho A subjective review of compaction (tutorial session). [Citation Graph (0, 0)][DBLP ] Conf ] Michael R. Wayne , Susan M. Braun Looking for Mr. "Turnkey". [Citation Graph (0, 0)][DBLP ] Conf ] Marianne Winslett , Richard Berlin , Thomas H. Payne , Gio Wiederhold Relational and entity-relationship model databases and specialized design files in VLSI design. [Citation Graph (0, 0)][DBLP ] Conf ] Connie U. Smith , Geoffrey A. Frank , John L. Cuadrado An architecture design and assessment system for software/hardware codesign. [Citation Graph (0, 0)][DBLP ] Conf ] Steve Perry , Mike Mitchell , D. Pilling Yield analysis modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Takeshi Sakata , Aritoyo Kishimoto A circuit comparison system for bipolar linear LSI. [Citation Graph (0, 0)][DBLP ] Conf ] Russel L. Steinweg , Susan J. Aguirre , Kerry Pierce , Scott Nance Silicon compilation of gate array bases. [Citation Graph (0, 0)][DBLP ] Conf ] M. Iachponi , D. Vail , S. Bierly , A. Ignatowski A hierarchical gate array architecture and design methodology. [Citation Graph (0, 0)][DBLP ] Conf ] C. P. Hsu , B. N. Tien , K. Chow , R. A. Perry , J. Tang ALPS2: a standard cell layout system for double-layer metal technology. [Citation Graph (0, 0)][DBLP ] Conf ] Hart Anway , Greg Farnham , Rebecca Reid PLINT layout system for VLSI chips. [Citation Graph (0, 0)][DBLP ] Conf ] Robert A. Walker , Donald E. Thomas A model of design representation and synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] N. Giambiasi , B. MacGee , R. L'Bath , L. Demians d'Archimbaud , C. Delorme , P. Roux An adaptive and evolutive tool for describing general hierarchical models, based on frames and demons. [Citation Graph (0, 0)][DBLP ] Conf ] James C. Althoff , Robert D. Shur A behavioral modeling system for cell compilers. [Citation Graph (0, 0)][DBLP ] Conf ] Raul Camposano Synthesis techniques for digital systems design. [Citation Graph (0, 0)][DBLP ] Conf ] Charles W. Rose , Marcus Buchnen , Yatin Trivedi Integrating stochastic performance analysis with system design tools. [Citation Graph (0, 0)][DBLP ] Conf ] Nohbyung Park , Alice C. Parker Synthesis of optimal clocking schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Rob A. Rutenbar Future directions for DA machine research (panel session). [Citation Graph (0, 0)][DBLP ] Conf ] Robert P. Collins , William J. Ketelhut The impact of technological advances on programmable controller s(tutorial session). [Citation Graph (0, 0)][DBLP ] Conf ] Hidekazu Terai , Michiyoshi Hayase , Tokinori Kozawa A routing procedure for mixed array of custom macros and standard cells. [Citation Graph (0, 0)][DBLP ] Conf ] A. C. Finch , K. J. Mackenzie , G. J. Balsdon , G. Symonds A method for gridless routing of printed circuit boards. [Citation Graph (0, 0)][DBLP ] Conf ] Sangyong Han , Sartaj Sahni Layering algorithms for single row routing. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Leonard Joseph An expert systems approach to completing partially routed printed circuit boards. [Citation Graph (0, 0)][DBLP ] Conf ] W. M. Budney , S. K. Holewa MIDAS: integrated CAD for total system design. [Citation Graph (0, 0)][DBLP ] Conf ] Shigenobu Suzuki , Kazutoshi Takahashi , Takao Sugimoto , Mikio Kuwata Integrated design system for supercomputer SX-1/SX-2. [Citation Graph (0, 0)][DBLP ] Conf ] A. F. Hutchings , R. J. Bonneau , W. M. Fisher Integrated VLSI CAD systems at Digital Equipment Corporation. [Citation Graph (0, 0)][DBLP ] Conf ] N. J. Elias , R. J. Byrne , A. D. Close , R. M. McDermott The ITT VLSI design system: CAD integration in a multi-national environment. [Citation Graph (0, 0)][DBLP ] Conf ] John Lowell Computer aided design for analog applications (panel session): an assessment. [Citation Graph (0, 0)][DBLP ] Conf ] E. T. Grinthal Software quality assurance for CAD (tutorial). [Citation Graph (0, 0)][DBLP ] Conf ] Christopher W. Pidgeon , Peter A. Freeman Development concerns for a software design quality expert system. [Citation Graph (0, 0)][DBLP ] Conf ] Howard B. Schutzman ICHABOD: a data base manager for design automation applications. [Citation Graph (0, 0)][DBLP ] Conf ] G. P. Barabino , G. S. Barabino , G. Bisio , M. Marchesi A module for improving data access and management in an integrated CAD environment. [Citation Graph (0, 0)][DBLP ] Conf ] Gary B. Goates , Patrick M. Hefferan , Robert J. Smith II , Randy Harris Star's envoling design environment: a user's perspective on CAE. [Citation Graph (0, 0)][DBLP ] Conf ] Natalie Royal , John Hunter , Irene Buchanan A case study in process independence. [Citation Graph (0, 0)][DBLP ] Conf ] John P. Gray , John Hunter Portability in silicon CAE. [Citation Graph (0, 0)][DBLP ] Conf ] Lu Sha , Robert W. Dutton An analytical algorithm for placement of arbitrarily sized rectangular blocks. [Citation Graph (0, 0)][DBLP ] Conf ] John P. Blanks Near-optimal placement using a quadratic objective function. [Citation Graph (0, 0)][DBLP ] Conf ] Gotaro Odawara , Kazuhiko Iijima , Kazutoshi Wakabayashi Knowledge-based placement technique for printed wiring boards. [Citation Graph (0, 0)][DBLP ] Conf ] C. Roy , L.-P. Demers , Eduard Cerny , Jan Gecsei An object-oriented swicth-level simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Richard H. Lathrop , Robert S. Kirk An extensible object-oriented mixed-mod functional simulation system. [Citation Graph (0, 0)][DBLP ] Conf ] V. Ashok , Roger L. Costello , P. Sadayappan Modeling switch-level simulation using data flow. [Citation Graph (0, 0)][DBLP ] Conf ] Robert V. Zara , David R. Henke Building a layered database for design automation. [Citation Graph (0, 0)][DBLP ] Conf ] Paul McLellan Effective data management for VLSI design. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Schell , M. Ray Mercer CADTOOLS: a CAD algorithm development system. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Dagenais , Vinod K. Agarwal , Nicholas C. Rumin The McBOOLE logic minimizer. [Citation Graph (0, 0)][DBLP ] Conf ] Prathima Agrawal , Vishwani D. Agrawal , Nripendra N. Biswas Multiple output minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Kye S. Hedlund Electrical optimization of PLAs. [Citation Graph (0, 0)][DBLP ] Conf ] Randal E. Bryant Symbolic manipulation of Boolean functions using a graphical representation. [Citation Graph (0, 0)][DBLP ] Conf ] Yiwan Wong Hierarchical circuit verification. [Citation Graph (0, 0)][DBLP ] Conf ] J. Doug Tygar , Ron Ellickson Efficient netlist comparison using hierarchy and randomization. [Citation Graph (0, 0)][DBLP ] Conf ] Nandakumar N. Tendolkar Analysis of timing failures due to random AC defects in VLSI modules. [Citation Graph (0, 0)][DBLP ] Conf ] Randal E. Bryant , Michael Dd. Schuster Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Anil K. Gupta , James R. Armstrong Functional fault modeling and simulation for VLSI devices. [Citation Graph (0, 0)][DBLP ] Conf ] John J. Granacki , David Knapp , Alice C. Parker The ADAM advanced design automation system: overview, planner and natural language interface. [Citation Graph (0, 0)][DBLP ] Conf ] Gotaro Odawara , Masahiro Tomita , Ichiro Ogata Diagrammatic function description of microprocessor and data-flow processor. [Citation Graph (0, 0)][DBLP ] Conf ] Edward H. Frank Switch-level simulation of VLSI using a special-purpose data-driven computer. [Citation Graph (0, 0)][DBLP ] Conf ] Peter J. M. van Laarhoven , Emile H. L. Aarts , Marc Davio PHIPLA-a new algorithm for logic minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Y. S. Kuo , C. Chen , T. C. Hu A heuristic algorithm for PLA block folding. [Citation Graph (0, 0)][DBLP ] Conf ] Surendra Nahar , Sartaj Sahni , Eugene Shragowitz Experiments with simulated annealing. [Citation Graph (0, 0)][DBLP ] Conf ] Robert V. Zara , Kevin Rose , Ghulam Nurie , Harish Sarin An abstract machine data structure for non-procedural functional models. [Citation Graph (0, 0)][DBLP ] Conf ] Vighneswara Row Mokkarala , Antony Fan , Ravi Apte A unified approach to simulation and timing verification at the functional level. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas J. Schaefer A transistor-level logic-with-timing simulator for MOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshiyuki Koseki , Teruhiko Yamada PLAYER: a PLA design system for VLSI's. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Dwyer , Stephen Morris , Edward Bard , Daniel Green The integration of an advanced gate array router into a fully automated design system. [Citation Graph (0, 0)][DBLP ] Conf ] Louise T. Lemaire GAMMA: a fast prototype design, build, and test process. [Citation Graph (0, 0)][DBLP ] Conf ] Dwight D. Hill , John P. Fishburn , Mary Diane Palmer Leland Effective use of virtual grid compaction in macro-module generators. [Citation Graph (0, 0)][DBLP ] Conf ] William H. Kao , Nader Fathi , Chia-Hao Lee Algorithms for automatic transistor sizing in CMOS digital circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Andou , Ichiro Yamamoto , Yuuko Mori , Yutaka Koike , Kimikatsu Shouji , Kazuyuki Hirakawa Automatic routing algorithm for VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Stef van Vlierberghe , Jeff Rijmenants , Walter Heyns Symbolic hierarchical artwork generation system. [Citation Graph (0, 0)][DBLP ] Conf ] Salim U. Chowdhury , Melvin A. Breuer The construction of minimal area power and ground nets for VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Fred W. Obermeier , Randy H. Katz PLA driver selection: an analytic approach. [Citation Graph (0, 0)][DBLP ] Conf ] Semyon Shteingart , Andrew W. Nagle , John Grason RTG: automatic register level test generator. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Krasniewski , Alexander Albicki Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applications. [Citation Graph (0, 0)][DBLP ] Conf ] Masayuki Miyoshi , Yoshiharu Kazama , Osamu Tada , Yasuo Nagura , Nobutaka Amano Speed up techniques of logic simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Edward Chan Development of a timing analysis program for multiple clocked network. [Citation Graph (0, 0)][DBLP ] Conf ] C. Delorme , P. Roux , L. Demians d'Archimbaud , N. Giambiasi , R. L'Bath , B. MacGee , R. Charroppin A functional partitioning expert system for test sequences generation. [Citation Graph (0, 0)][DBLP ] Conf ] Madhukar K. Reddy , Sudhakar M. Reddy , Prathima Agrawal Transistor level test generation for MOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Beth W. Tucker Electronic CAD/CAM-is it revolution or evolution (tutorial session). [Citation Graph (0, 0)][DBLP ] Conf ] 