Conferences in DBLP

Design, Automation, and Test in Europe (date)
2001 (conf/date/2001)

1. Pallab Dasgupta, P. P. Chakrabarti, Amit Nandi, Sekar Krishna, Arindam Chakrabarti
   Abstraction of word-level linear arithmetic functions from bit-level component descriptions. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:4-8 [Conf]
   
2. Gianpiero Cabodi, Paolo Camurati, Stefano Quer
   Biasing symbolic search by means of dynamic activity profiles. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:9-15 [Conf]
   
3. Luc Charest, Michel Reid, El Mostapha Aboulhamid, Guy Bois
   A methodology for interfacing open source systemC with a third party software. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:16- [Conf]
   
4. George Economakos, Petros Oikonomakos, Ioannis Panagopoulos, Ioannis Poulakis, George K. Papakonstantinou
   Behavioral synthesis with systemC. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:21-25 [Conf]
   
5. Robert Siegmund, Dietmar Müller
   SystemCSV - an extension of SystemC for mixed multi-level communication modeling and interface-based system design. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:26-33 [Conf]
   
6. Yervant Zorian, Paolo Prinetto, João Paulo Teixeira, Isabel C. Teixeira, Carlos Eduardo Pereira, O. P. Dias, Jorge Semião, Peter Muhmenthaler, W. Radermacher
   Embedded tutorial: TRP: integrating embedded test and ATE. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:34-37 [Conf]
   
7. Peter van Staa, Thomas Beck
   Embedded tutorial: current trends in the design of automotive electronic systems. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:38-39 [Conf]
   
8. G. Martin, Ralf Seepold, Ting Zhang, Luca Benini, Giovanni De Micheli
   Component selection and matching for IP-based design. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:40-46 [Conf]
   
9. Thilo Demmeler, Paolo Giusto
   A universal communication model for an automotive system integration platform. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:47-54 [Conf]
   
10. Amer Baghdadi, Damien Lyonnard, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
    An efficient architecture model for systematic design of application-specific multiprocessor SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:55-63 [Conf]
    
11. Jürgen Ruf, Dirk W. Hoffmann, Joachim Gerlach, Thomas Kropf, Wolfgang Rosenstiel, Wolfgang Müller 0003
    The simulation semantics of systemC. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:64-70 [Conf]
    
12. J. Zhu
    MetaRTL: raising the abstraction level of RTL design. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:71-76 [Conf]
    
13. Kjetil Svarstad, Gabriela Nicolescu, Ahmed Amine Jerraya
    A model for describing communication between aggregate objects in the specification and design of embedded systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:77-85 [Conf]
    
14. A. Irion, Gundolf Kiefer, Harald P. E. Vranken, Hans-Joachim Wunderlich
    Circuit partitioning for efficient logic BIST synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:86-91 [Conf]
    
15. Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Yervant Zorian
    Deterministic software-based self-testing of embedded processor cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:92-96 [Conf]
    
16. Jin-Fu Li, Cheng-Wen Wu
    Memory fault diagnosis by syndrome compression. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:97-101 [Conf]
    
17. Ismet Bayraktaroglu, Alex Orailoglu
    Diagnosis for scan-based BIST: reaching deep into the signatures. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:102-111 [Conf]
    
18. Arjun Panday, Damien Couderc, Simon Marichalar
    AIL: description of a global electronic architecture at the vehicle scale. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:112- [Conf]
    
19. Jakob Axelsson
    Methods and tools for systems engineering of automotive electronic architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:112- [Conf]
    
20. G. Hettich, Thomas Thurner
    Vehicle electric/electronic architecture - one of the most important challenges for OEM's. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:112-113 [Conf]
    
21. Evguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton
    Using SAT for combinational equivalence checking. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:114-121 [Conf]
    
22. Sherief Reda, A. Salem
    Combinational equivalence checking using Boolean satisfiability and binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:122-126 [Conf]
    
23. Yakov Novikov, Evguenii I. Goldberg
    An efficient learning procedure for multiple implication checks. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:127-135 [Conf]
    
24. Daniel Gajski, Eugenio Villar, Wolfgang Rosenstiel, Vassilios Gerousis, D. Barton, J. Plantin, S. E. Ericsson, Patrizia Cavalloro, Gjalt G. de Jong
    C/C++: progress or deadlock in system-level specification. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:136-137 [Conf]
    
25. Erik Larsson, Zebo Peng
    An integrated system-on-chip test framework. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:138-144 [Conf]
    
26. Anshuman Chandra, Krishnendu Chakrabarty
    Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:145-149 [Conf]
    
27. Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
    Testing TAPed cores and wrapped cores with the same test access mechanism. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:150-155 [Conf]
    
28. Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Hans-Joachim Wunderlich
    On applying the set covering model to reseeding. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:156-161 [Conf]
    
29. Peter van Staa, Robert Bosch, H. Heidbrink, B. Potock, J. Mueller, W. Kisselmann, W. Herden
    Data management: limiter or accelerator for electronic design creativity. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:162-163 [Conf]
    
30. Gerd Vandersteen, Piet Wambacq, Yves Rolain, Johan Schoukens, Stéphane Donnay, Marc Engels, Ivo Bolsens
    Efficient bit-error-rate estimation of multicarrier transceivers. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:164-168 [Conf]
    
31. Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
    Efficient time-domain simulation of telecom frontends using a complex damped exponential signal model. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:169-175 [Conf]
    
32. Luong Nguyen, Vincent Janicot
    Simulation method to extract characteristics for digital wireless communication systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:176-181 [Conf]
    
33. Cheng-Ta Hsieh, L. Chen, Massoud Pedram
    Microprocessor power analysis by labeled simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:182-189 [Conf]
    
34. Anoop Iyer, Diana Marculescu
    Power aware microarchitecture resource scaling. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:190-196 [Conf]
    
35. Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Extending lifetime of portable systems by battery scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:197-203 [Conf]
    
36. Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal
    Efficient spectral techniques for sequential ATPG. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:204-208 [Conf]
    
37. Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante
    On the test of microprocessor IP cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:209-213 [Conf]
    
38. Irith Pomeranz, Sudhakar M. Reddy
    Sequence reordering to improve the levels of compaction achievable by static compaction procedures. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:214-218 [Conf]
    
39. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    SEU effect analysis in an open-source router via a distributed fault injection environment. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:219-225 [Conf]
    
40. A. Lock, Raul Camposano, Heinrich Meyr
    The programmable platform: does one size fit all? [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:226-227 [Conf]
    
41. Minghorng Lai, D. F. Wong
    Slicing tree is a complete floorplan representation. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:228-232 [Conf]
    
42. Chak-Chung Cheung, Yu-Liang Wu, David Ihsin Cheng
    Further improve circuit partitioning using GBAW logic perturbation techniques. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:233-239 [Conf]
    
43. Makoto Saitoh, Masaaki Azuma, Atsushi Takahashi
    Clustering based fast clock scheduling for light clock-tree. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:240-245 [Conf]
    
44. John Dielissen, Jef L. van Meerbergen, Marco Bekooij, Françoise Harmsze, Sergej Sawitzki, Jos Huisken, Albert van der Werf
    Power-efficient layered turbo decoder processor. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:246-251 [Conf]
    
45. Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    Exploiting data forwarding to reduce the power budget of VLIW embedded processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:252-257 [Conf]
    
46. Alexander Worm, Holger Lamm, Norbert Wehn
    Design of low-power high-speed maximum a priori decoder architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:258-267 [Conf]
    
47. Cassondra Neau, Khurram Muhammad, Kaushik Roy
    Low complexity FIR filters using factorization of perturbed coefficients. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:268-272 [Conf]
    
48. Andrea Acquaviva, Luca Benini, Bruno Riccò
    An adaptive algorithm for low-power streaming multimedia processing. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:273-279 [Conf]
    
49. Xun Liu, Marios C. Papaefthymiou
    A static power estimation methodolodgy for IP-based design. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:280-289 [Conf]
    
50. Michele Favalli, Cecilia Metra
    Optimization of error detecting codes for the detection of crosstalk originated errors. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:290-296 [Conf]
    
51. Ph. Cheynet, B. Nicolescu, Raoul Velazco, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    System safety through automatic high-level code transformations: an experimental evaluation. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:297-301 [Conf]
    
52. Michael G. Wahl, Anthony P. Ambler, Christoph Maaß, Mohammed Rahman
    From DFT to systems test - a model based cost optimization tool. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:302-306 [Conf]
    
53. Alexander V. Drozd, M. V. Lobachev
    Efficient on-line testing method for a floating-point adder. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:307-313 [Conf]
    
54. Julio Leao da Silva Jr., J. Shamberger, M. Josie Ammer, C. Guo, Suet-Fei Li, Rahul C. Shah, Tim Tuan, Michael Sheets, Jan M. Rabaey, B. Nikolic, Alberto L. Sangiovanni-Vincentelli, Paul K. Wright
    Design methodology for PicoRadio networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:314-325 [Conf]
    
55. Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, Stéphane Donnay, Hugo De Man, Georges G. E. Gielen, Marc Engels, Ivo Bolsens
    High-level simulation of substrate noise generation from large digital circuits with multiple supplies. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:326-330 [Conf]
    
56. Chr. Werner, R. Göttsche, A. Wörner, Ulrich Ramacher
    Crosstalk noise in future digital CMOS circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:331-335 [Conf]
    
57. P. Kralicek, Werner John, Heyno Garbe
    Modeling electromagnetic emission of integrated circuits for system analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:336-340 [Conf]
    
58. Franco Fiori, Francesco Musolino
    Analysis of EME produced by a microcontroller operation. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:341-347 [Conf]
    
59. Rocio del Río, Josep Lluís de la Rosa, F. Medeiro, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez
    Top-down design of a xDSL 14-bit 4MS/s sigma-delta modulator in digital CMOS technology. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:348-352 [Conf]
    
60. Mohamed Dessouky, Andreas Kaiser, Marie-Minerve Louërat, Alain Greiner
    Analog design for reuse - case study: very low-voltage sigma-delta modulator. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:353-360 [Conf]
    
61. Friedel Gerfers, Yiannos Manoli
    A design strategy for low-voltage low-power continuous-time sigma-delta A/D converters. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:361-369 [Conf]
    
62. Srinath R. Naidu, E. T. A. F. Jacobs
    Minimizing stand-by leakage power in static CMOS circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:370-376 [Conf]
    
63. Chih-Wei Jim Chang, Bo Hu, Malgorzata Marek-Sadowska
    In-place delay constrained power optimization using functional symmetries. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:377-382 [Conf]
    
64. Lech Józwiak, Artur Chojnacki
    High-quality sub-function construction in functional decomposition based on information relationship measures. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:383-390 [Conf]
    
65. José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías
    Generalized reasoning scheme for redundancy addition and removal logic optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:391-397 [Conf]
    
66. Zhihong Zeng, Priyank Kalla, Maciej J. Ciesielski
    LPSAT: a unified approach to RTL satisfiability. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:398-402 [Conf]
    
67. Fabrizio Ferrandi, G. Ferrara, Donatella Sciuto, Alessandro Fin, Franco Fummi
    Functional test generation for behaviorally sequential models. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:403-410 [Conf]
    
68. Amjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman
    High quality behavioral verification using statistical stopping criteria. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:411-419 [Conf]
    
69. Pierre G. Paulin, Faraydon Karim, Paul Bromley
    Network processors: a perspective on market requirements, processor architectures and embedded S/W tools. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:420-429 [Conf]
    
70. Michael W. Beattie, Lawrence T. Pileggi
    Efficient inductance extraction via windowing. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:430-436 [Conf]
    
71. Qinwei Xu, Pinaki Mazumder
    Efficient and passive modeling of transmission lines by using differential quadrature method. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:437-444 [Conf]
    
72. Qingjian Yu, Ernest S. Kuh
    Explicit formulas and efficient algorithm for moment computation of coupled RC trees with lumped and distributed elements. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:445-450 [Conf]
    
73. Tom Chen
    On the impact of on-chip inductance on signal nets under the influence of power grid noise. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:451-459 [Conf]
    
74. Raimund Ubar, Artur Jutman, Zebo Peng
    Timing simulation of digital circuits with binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:460-466 [Conf]
    
75. Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia
    HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:467-471 [Conf]
    
76. Klaus Hering, Jork Löser, Jens Markwardt
    dibSIM: a parallel functional logic simulator allowing dynamic load balancing. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:472-478 [Conf]
    
77. Joachim Küter, Erich Barke
    Architecture driven partitioning. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:479-487 [Conf]
    
78. Christian Piguet, Marc Renaudin, Thierry J.-F. Omnés
    Low-power systems on chips (SOCs). [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:488- [Conf]
    
79. Zaid Al-Ars, A. J. van de Goor
    Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:496-503 [Conf]
    
80. Irith Pomeranz, Sudhakar M. Reddy
    Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:504-508 [Conf]
    
81. Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada
    CMOS open defect detection by supply current test. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:509- [Conf]
    
82. Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham
    Full chip false timing path identification: applications to the PowerPCTM microprocessors. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:514-519 [Conf]
    
83. Piet Wambacq, Gerd Vandersteen, Joel R. Phillips, Jaijeet S. Roychowdhury, Wolfgang Eberle, Baolin Yang, David E. Long, Alper Demir
    CAD for RF circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:520-529 [Conf]
    
84. Pirouz Bazargan-Sabet, Fabrice Ilponse
    Modeling crosstalk noise for deep submicron verification tools. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:530-534 [Conf]
    
85. Youxin Gao, D. F. Wong
    A graph based algorithm for optimal buffer insertion under accurate delay models. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:535-539 [Conf]
    
86. Probir Sarkar, Cheng-Kok Koh
    Repeater block planning under simultaneous delay and transition time constraints. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:540-545 [Conf]
    
87. Luca Macchiarulo, Luca Benini, Enrico Macii
    On-the-fly layout generation for PTL macrocells. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:546-551 [Conf]
    
88. Tatjana Serdar, Carl Sechen
    Automatic datapath tile placement and routing. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:552-559 [Conf]
    
89. Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
    A boolean satisfiability-based incremental rerouting approach with application to FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:560-565 [Conf]
    
90. Mauricio Varea, Bashir M. Al-Hashimi
    Dual transitions petri net based modelling technique for embedded systems specification. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:566-571 [Conf]
    
91. Radu Marculescu, Amit Nandi
    Probabilistic application modeling for system-level perfromance analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:572-579 [Conf]
    
92. Paolo Giusto, Grant Martin, Edwin A. Harcourt
    Reliable estimation of execution time of embedded software. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:580-589 [Conf]
    
93. Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell
    Implementation of a linear histogram BIST for ADCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:590-595 [Conf]
    
94. Sasikumar Cherubal, Abhijit Chatterjee
    Test generation based diagnosis of device parameters for analog circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:596-602 [Conf]
    
95. Bernhard Burdiek
    Generation of optimum test stimuli for nonlinear analog circuits using nonlinear - programming and time-domain sensitivities. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:603-609 [Conf]
    
96. Ron Wilson
    Managing the SoC design challenge with "Soft" hardware. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:610-611 [Conf]
    
97. Alex Doboli
    Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraints. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:612-619 [Conf]
    
98. Yuan Xie, Wayne Wolf
    Allocation and scheduling of conditional task graph in hardware/software co-synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:620-625 [Conf]
    
99. Sri Parameswaran
    Code placement in hardware/software co-synthesis to improve performance and reduce cost. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:626-632 [Conf]
    
100. Bilge Saglam Akgul, Vincent John Mooney III
     System-on-a-chip processor synchronization support in hardware. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:633-641 [Conf]
     
101. Reiner W. Hartenstein
     A decade of reconfigurable computing: a visionary retrospective. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:642-649 [Conf]
     
102. Iyad Ouaiss, Ranga Vemuri
     Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:650-657 [Conf]
     
103. Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich
     Optimal FPGA module placement with temporal precedence constraints. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:658-667 [Conf]
     
104. Claudio Passerone, Yosinori Watanabe, Luciano Lavagno
     Generation of minimal size code for scheduling graphs. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:668-673 [Conf]
     
105. Andreas Hoffmann, Achim Nohl, Stefan Pees, Gunnar Braun, Heinrich Meyr
     Generating production quality software development tools using a machine description language. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:674-678 [Conf]
     
106. Lovic Gauthier, Sungjoo Yoo, Ahmed Amine Jerraya
     Automatic generation and targeting of application specific operating systems and embedded systems software. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:679-685 [Conf]
     
107. Chidamber Kulkarni, C. Ghez, Miguel Miranda, Francky Catthoor, Hugo De Man
     Cache conscious data layout organization for embedded multimedia applications. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:686-693 [Conf]
     
108. Georges G. E. Gielen, B. Sorensen, H. Casier, Philippe Magarshack, J. Rodriguez
     Design challenges and emerging EDA solutions in mixed-signal IC design. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:694-695 [Conf]
     
109. Haruyuki Tago, Kazuhiro Hashimoto, Nobuyuki Ikumi, Masato Nagamatsu, Masakazu Suzuoki, Yasuyuki Yamamoto
     CPU for PlayStation 2. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:696- [Conf]
     
110. Anand Mandapati
     Implementation of the ATI flipper chip. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:697-698 [Conf]
     
111. Susumu Narita
     SH-4 RISC microprocessor for multimedia, game machine. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:699-701 [Conf]
     
112. Shin-ichi Minato, Shinya Ishihara
     Streaming BDD manipulation for large-scale combinatorial problems. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:702-707 [Conf]
     
113. Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu
     Binary decision diagram with minimum expected path length. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:708-712 [Conf]
     
114. Mitchell A. Thornton, Rolf Drechsler
     Spectral decision diagrams using graph transformations. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:713-719 [Conf]
     
115. Ahmed Amine Jerraya, G. Matheron
     Electronic system design methodology: Europe's positioning. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:720-721 [Conf]
     
116. Anshuman Nayak, Malay Haldar, Alok N. Choudhary, Prithviraj Banerjee
     Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:722-728 [Conf]
     
117. Juanjo Noguera, Rosa M. Badia
     A HW/SW partitioning algorithm for dynamically reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:729- [Conf]
     
118. Zhining Huang, Sharad Malik
     Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:735- [Conf]
     
119. Jürgen Ruf, Dirk W. Hoffmann, Thomas Kropf, Wolfgang Rosenstiel
     Simulation-guided property checking based on a multi-valued AR-automata. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:742-748 [Conf]
     
120. Jinyong Jung, Sungjoo Yoo, Kiyoung Choi
     Performance improvement of multi-processor systems cosimulation based on SW analysis. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:749-753 [Conf]
     
121. Gabriela Nicolescu, Sungjoo Yoo, Ahmed Amine Jerraya
     Mixed-level cosimulation for fine gradual refinement of communication in SoC design. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:754-759 [Conf]
     
122. Andreas Hoffmann, Tim Kogel, Heinrich Meyr
     A framework for fast hardware-software co-simulation. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:760-765 [Conf]
     
123. Natividad Martínez Madrid, Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda
     Analog/mixed-signal IP modeling for design reuse. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:766-767 [Conf]
     
124. Xu Jingnan, João C. Vital, Nuno Horta
     A Skill-based library for retargetable embedded analog cores. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:768-769 [Conf]
     
125. Marco Rona, Gunter Krampl
     Modelling SoC devices for virtual test using VHDL. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:770-771 [Conf]
     
126. R. Castro-López, Francisco V. Fernández, Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez
     Retargeting of mixed-signal blocks for SoCs. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:772-775 [Conf]
     
127. C. Yeung, Anssi Haverinen, Graham Matthews, Jonathan Morris, Jauher Zaidi
     Standard bus vs. bus wrapper: what is the best solution for future SoC integration? [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:776-777 [Conf]
     
128. Peter Grun, Nikil D. Dutt, Alexandru Nicolau
     Access pattern based local memory customization for low power embedded systems. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:778-784 [Conf]
     
129. Jianwen Zhu
     Static memory allocation by pointer analysis and coloring. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:785-790 [Conf]
     
130. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
     Heuristic datapath allocation for multiple wordlength systems. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:791-797 [Conf]
     
131. Elena Teica, Rajesh Radhakrishnan, Ranga Vemuri
     On the verification of synthesized designs using automatically generated transformational witnesses. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:798- [Conf]
     
132. Albert E. Casavant, Aarti Gupta, S. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi, Pranav Ashar
     Property-specific witness graph generation for guided simulation. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:799- [Conf]
     
133. Vytautas Stuikys, Giedrius Ziberkas, Robertas Damasevicius, Giedrius Majauskas
     Two approaches for developing generic components in VHDL. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:800- [Conf]
     
134. Gordon Cichon, Winthir Bunnbauer
     Annotated data types for addressed token passing networks. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:801- [Conf]
     
135. Nicola Nicolici, Bashir M. Al-Hashimi
     Testability trade-offs for BIST RTL data paths: the case for three dimensional design space. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:802- [Conf]
     
136. A. Lechner, A. Richardson, B. Hermes
     Towards a better understanding of failure modes and test requirements of ADCs. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:803- [Conf]
     
137. Md. Saffat Quasem, Sandeep K. Gupta
     Exact fault simulation for systems on Silicon that protects each core's intellectual property. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:804- [Conf]
     
138. Rainer Dorsch, Hans-Joachim Wunderlich
     Using mission logic for embedded testing. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:805- [Conf]
     
139. Alex Doboli, Ranga Vemuri
     A regularity-based hierarchical symbolic analysis method for large-scale analog networks. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:806- [Conf]
     
140. Markus Olbrich, Achim Rein, Erich Barke
     An improved hierarchical classification algorithm for structural analysis of integrated circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:807- [Conf]
     
141. Eike Schmidt, Gerd Jochens, Lars Kruse, Frans Theeuwen, Wolfgang Nebel
     Automatic nonlinear memory power modelling. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:808- [Conf]
     
142. Dongkun Shin, Jihong Kim, Naehyuck Chang
     An operation rearrangement technique for power optimization in VLIM instruction fetch. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:809- [Conf]
     
143. Oscar Garnica, Juan Lanchares, Román Hermida
     A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:810- [Conf]
     
144. C. Rousselle, Matthias Pflanz, A. Behling, T. Mohaupt, Heinrich Theodor Vierhaus
     A register-transfer-level fault simulator for permanent and transient faults in embedded processors. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:811- [Conf]
     
145. Guido Bertoni, Luca Breveglieri, Pasqualina Fragneto
     Efficient finite field digital-serial multiplier architecture for cryptography applications. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:812- [Conf]
     
146. Chun Wong, Paul Marchal, Peng Yang, Francky Catthoor, Hugo De Man, Aggeliki Prayati, Nathalie Cossement, Rudy Lauwereins, Diederik Verkest
     Task concurrency management methodology summary. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:813- [Conf]
     
147. Franco Fiori
     Susceptibility of analog cells to substrate interference. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:814- [Conf]
     
148. Arie van Staveren, Chris J. M. Verhoeven
     Order determination for frequency compensation of negative-feedback systems. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:815- [Conf]
     
149. E. Yildiz, Arie van Staveren, Chris J. M. Verhoeven
     Minimizing the number of floating bias voltage sources with integer linear programming. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:816- [Conf]
     
150. Gregorio Cappuccino, Giuseppe Cocorullo
     CMOS sizing rule for high performance long interconnects. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:817- [Conf]
     
151. Sandeep Koranne, Om Prakash Gangwal
     On automatic analysis of geometrically proximate nets in VSLI layout. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:818- [Conf]
     
152. Jens Lienig, Goeran Jerke, Thorsten Adler
     AnalogRouter: a new approach of current-driven routing for analog circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:819- [Conf]
     
153. José Manuel Moya, Francisco Moya, Juan Carlos López
     A hardware-software operating system for heterogeneous designs. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:820- [Conf]
     
154. Andrei Terechko, Evert-Jan D. Pol, Jos T. J. van Eijndhoven
     PRMDL: a machine description language for clustered VLIW architectures. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:821- [Conf]
     
155. Marco Bekooij, Loek J. M. Engels, Albert van der Werf, Natalino G. Busá
     Functional units with conditional input/output behavior in VLIW processors. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:822- [Conf]
     
156. Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi
     Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:823- [Conf]
     
157. Carlos A. Alba Pinto, Bart Mesman, Koen van Eijk, Jochen A. G. Jess
     Constraint satisfaction for storage files with Fifos or stacks during scheduling. [Citation Graph (0, 0)][DBLP]
     DATE, 2001, pp:824- [Conf]