Conferences in DBLP

Design, Automation, and Test in Europe (date)
1998 (conf/date/1998)

1. Alexander Chatzigeorgiou, Spiridon Nikolaidis
   Collapsing the Transistor Chain to an Effective Single Equivalent Transistor. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:2-6 [Conf]
   
2. Michael Nicolaidis, Ricardo de Oliveira Duarte
   Design of Fault-Secure Parity-Prediction Booth Multipliers. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:7-14 [Conf]
   
3. Kimihiro Ogawa, Michinari Kohno, Fusako Kitamura
   PASTEL: A Parameterized Memory Characterization System. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:15-0 [Conf]
   
4. Jesper Grode, Peter Voigt Knudsen, Jan Madsen
   Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:22-27 [Conf]
   
5. Vinoo Srinivasan, Shankar Radhakrishnan, Ranga Vemuri
   Hardware Software Partitioning with Integrated Hardware Design Space Exploration. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:28-35 [Conf]
   
6. Michael Gasteier, Manfred Glesner, Michael Münch
   Generation of Interconnect Topologies for Communication Synthesis. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:36-0 [Conf]
   
7. Sun-Yen Tan, Stephen B. Furber, Wen-Fang Yen
   The Design of an Asynchronous VHDL Synthesizer. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:44-51 [Conf]
   
8. Christoph Grimm, Klaus Waldschmidt
   Repartitioning and Technology-Mapping of Electronic Hybrid Systems. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:52-58 [Conf]
   
9. Eduard Moser, Norbert Mittwollen
   VHDL-AMS: The Missing Link in System Design - Experiments with Unified Modelling in Automotive Engineering. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:59-0 [Conf]
   
10. Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
    Scheduling and Module Assignment for Reducing Bist Resources. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:66-73 [Conf]
    
11. Laurence Tianruo Yang, Zebo Peng
    An Efficient Algorithm to Integrate Scheduling and Allocation in High-Level Test Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:74-81 [Conf]
    
12. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    RAM-Based FPGA's: A Test Approach for the Configurable Logic. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:82-88 [Conf]
    
13. Cecilia Metra, Michel Renovell, G. Mojoli, Jean Michel Portal, S. Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi
    Novel Technique for Testing FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:89-0 [Conf]
    
14. Juan Carlos Diaz, Pierre Plaza, Jesus Crespo
    ATM Traffic Shaper: ATS. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:96-101 [Conf]
    
15. E. Lago, C. J. Jiménez, D. R. Lopez, Santiago Sánchez-Solano, Angel Barriga Barrios
    XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:102-107 [Conf]
    
16. Wolfgang Eppler, Thomas Fischer, Hartmut Gemmeke, A. Menchikov
    High Speed Neural Network Chip for Trigger Purposes in High Energy Physics. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:108-0 [Conf]
    
17. Bharat P. Dave, Niraj K. Jha
    CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:118-124 [Conf]
    
18. Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess
    Stream Communication between Real-Time Tasks in a High-Performance Multiprocessor. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:125-131 [Conf]
    
19. Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop
    Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:132-0 [Conf]
    
20. Yee-Wing Hsieh, Steven P. Levitan
    Model Abstraction for Formal Verification. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:140-147 [Conf]
    
21. Jason Coppens, Dhamin Al-Khalili, Come Rozon
    VHDL Modelling and Analysis of Fault Secure Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:148-152 [Conf]
    
22. Matthias Mutz
    Register Transfer Level VHDL Models without Clocks. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:153-158 [Conf]
    
23. Edwin Naroska
    Parallel VHDL Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:159-0 [Conf]
    
24. Wei Zhao, Christos A. Papachristou
    Testing DSP Cores Based on Self-Test Programs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:166-172 [Conf]
    
25. Vyacheslav N. Yarmolik, Sybille Hellebrand, Hans-Joachim Wunderlich
    Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:173-179 [Conf]
    
26. T. Bogue, Michael Gössel, Helmut Jürgensen, Yervant Zorian
    Built-In Self-Test with an Alternating Output. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:180-0 [Conf]
    
27. Claus Schneider, Martin Kayss, Thomas Hollstein, Jürgen Deicke
    From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:186-190 [Conf]
    
28. A. M. Rassau, T. C. B. Yu, H. Cheung, Stefan Lachowicz, Kamran Eshraghian, W. A. Crossland, T. D. Wilkinson
    Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:191-195 [Conf]
    
29. Isidoro Urriza, José I. Artigas, José I. García-Nicolás, Luis A. Barragan, Denis Navarro
    VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:196-0 [Conf]
    
30. Alberto Allara, William Fornaciari, Fabio Salice, Donatella Sciuto
    A Model for System-Level Timed Analysis and Profiling. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:204-210 [Conf]
    
31. Bill Lin
    Efficient Compilation of Process-Based Concurrent Programs without Run-Time Scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:211-217 [Conf]
    
32. J. A. Maestro, Daniel Mozos, Hortensia Mecha
    A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:218-225 [Conf]
    
33. Joachim Gerlach, Wolfgang Rosenstiel
    A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration Environment. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:226-0 [Conf]
    
34. Guido Schumacher, Wolfgang Nebel
    Object-Oriented Modelling of Parallel Hardware Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:234-241 [Conf]
    
35. Wolfram Putzke-Röming, Martin Radetzki, Wolfgang Nebel
    A Flexible Message Passing Mechanism for Objective VHDL. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:242-249 [Conf]
    
36. Michael Mrva
    Enhanced Reuse and Teamwork Capabilities for an Object-oriented Extension of VHDL. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:250-256 [Conf]
    
37. Ralf Reetz, Klaus Schneider, Thomas Kropf
    Formal Specification in VHDL for Hardware Verification. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:257-0 [Conf]
    
38. Anna Antola, Vincenzo Piuri, Mariagiovanna Sami
    A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:266-272 [Conf]
    
39. Li-C. Wang, Magdy S. Abadir, Jing Zeng
    Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:273-277 [Conf]
    
40. Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee
    Functional Scan Chain Testing. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:278-0 [Conf]
    
41. Grant Martin
    Design Methodologies for System Level IP. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:286-289 [Conf]
    
42. Bart de Loore
    IP-Based System-on-a-Chip Design. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:290-0 [Conf]
    
43. Manfred Koegst, Dieter Garte, Peter Conradi, Michael G. Wahl
    A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:292-296 [Conf]
    
44. Serafín Olcoz, Lorenzo Ayuda, Ivan Izaguirre, Olga Peñalba
    VHDL Teamwork, Organization Units and Workspace Management. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:297-302 [Conf]
    
45. Jörg Böttger, Karlheinz Agsteiner, Dieter Monjau, Sören Schulze
    An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:303-0 [Conf]
    
46. Jürgen Koehl, Ulrich Baur, Thomas Ludwig, Bernhard Kick, Thomas Pflueger
    A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:312-320 [Conf]
    
47. Jens Vygen
    Algorithms for Detailed Placement of Standard Cells. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:321-324 [Conf]
    
48. Uwe Fassnacht, Jürgen Schietke
    Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:325-331 [Conf]
    
49. Asmus Hetzel
    A Sequential Detailed Router for Huge Grid Graphs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:332-0 [Conf]
    
50. W. Shields Neely
    Reconfigurable Logic for Systems on a Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:340- [Conf]
    
51. Jan M. Rabaey, Marlene Wan
    An Energy-Conscious Exploration Methodology for Reconfigurable DSPs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:341-342 [Conf]
    
52. Ian Page
    Design Of Future Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:343-0 [Conf]
    
53. V. Chandramouli, Jesse Whittemore, Karem A. Sakallah
    AFTA: A Formal Delay Model for Functional Timing Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:350-355 [Conf]
    
54. Dirk Rabe, Gerd Jochens, Lars Kruse, Wolfgang Nebel, Carl von Ossietzky
    Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:356-361 [Conf]
    
55. S. Schmerler, Y. Tanurhan, Klaus D. Müller-Glaser
    Advanced Optimistic Approaches in Logic Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:362-0 [Conf]
    
56. Andreas Pyttel, Alexander Sedlmeier, Christian Veith
    PSCP: A Scalable Parallel ASIP Architecture for Reactive Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:370-376 [Conf]
    
57. Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess
    A Constraint Driven Approach to Loop Pipelining and Register Binding. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:377-383 [Conf]
    
58. Ju Hwan Yi, Hoon Choi, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung
    Multiple Behavior Module Synthesis Based on Selective Groupings. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:384-388 [Conf]
    
59. Meenakshi Kaul, Ranga Vemuri
    Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:389-0 [Conf]
    
60. Jianjian Song, Zhaoxuan Shen, Wenjun Zhuang
    An Effective General Connectivity Concept for Clustering. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:398-405 [Conf]
    
61. Christopher S. Helvig, Gabriel Robins, Alexander Zelikovsky
    Improved Approximation Bounds for the Group Steiner Problem. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:406-413 [Conf]
    
62. Thorsten Adler, Juergen Schaeuble
    An Interactive Router for Analog IC Design. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:414-0 [Conf]
    
63. Wolfgang Rosenstiel
    Formal Verification: A New Standard CAD Tool for the Industrial Design Flow. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:422-0 [Conf]
    
64. Guido Post, Andrea Müller, Thorsten Grötker
    A System-Level Co-Verification Environment for ATM Hardware Design. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:424-428 [Conf]
    
65. Holger Keding, Markus Willems, Martin Coors, Heinrich Meyr
    FRIDGE: A Fixed-Point Design and Simulation Environment. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:429-435 [Conf]
    
66. Cordula Hansen, Arno Kunzmann, Wolfgang Rosenstiel
    Verification by Simulation Comparison using Interface Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:436-0 [Conf]
    
67. Min Xu, Fadi J. Kurdahi
    Layout-Driven High Level Synthesis for FPGA Based Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:446-450 [Conf]
    
68. Oliver Bringmann, Wolfgang Rosenstiel
    Cross-Level Hierarchical High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:451-456 [Conf]
    
69. Jian Li, Rajesh K. Gupta
    An Algorithm To Determine Mutually Exclusive Operations In Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:457-0 [Conf]
    
70. Dongsheng Wang, Ernest S. Kuh
    A Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:466-470 [Conf]
    
71. Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma
    Interconnect Tuning Strategies for High-Performance Ics. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:471-478 [Conf]
    
72. Chris C. N. Chu, D. F. Wong
    A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:479-0 [Conf]
    
73. Wolfgang Rosenstiel
    Next Generation System Level Design Tools. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:488-0 [Conf]
    
74. Rosa Rodríguez-Montañés, Joan Figueras
    Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:490-494 [Conf]
    
75. B. Straka, Hans A. R. Manhaeve, Jozef Vanneuville, M. Svajda
    A Fully Digital Controlled Off-Chip IDDQ Measurement Unit. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:495-500 [Conf]
    
76. A. J. van de Goor, Issam B. S. Tlili
    March Tests for Word-Oriented Memories. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:501-0 [Conf]
    
77. R. Neul, U. Becker, G. Lorenz, P. Schwarz, J. Haase, S. Wünsche
    A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:510-217 [Conf]
    
78. Vladimir Székely, Márta Rencz
    Fast Field Solvers for Thermal and Electrostatic Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:518-523 [Conf]
    
79. Marcelo Lubaszewski, Érika F. Cota, Bernard Courtois
    Microsystems Testing: an Approach and Open Problems. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:524-0 [Conf]
    
80. Roland W. Freund, Peter Feldmann
    Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Pade Approximation. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:530-537 [Conf]
    
81. Nuno Alexandre Marques, Mattan Kamon, Jacob White, Luis Miguel Silveira
    An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:538-543 [Conf]
    
82. Jianhua Shao, Richard M. M. Chen
    MCM Interconnect Design Using Two-Pole Approximation. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:544-0 [Conf]
    
83. Wojciech Maly, Pranab K. Nag, Hans T. Heineken, Jitendra Khare
    Design-Manufacturing Interface: Part I - Vision. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:550-556 [Conf]
    
84. Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, P. Simon
    Design-Manufacturing Interface: Part II - Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:557-562 [Conf]
    
85. Hans T. Heineken, Wojciech Maly
    Performance - Manufacturability Tradeoffs in IC Design. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:563-0 [Conf]
    
86. Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:570-576 [Conf]
    
87. Michael S. Hsiao, Srimat T. Chakradhar
    State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:577-582 [Conf]
    
88. Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy
    Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:583-0 [Conf]
    
89. A. Jemai, Polen Kission, Ahmed Amine Jerraya
    Architectural Simulation in the Context of Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:590-595 [Conf]
    
90. Johnny Öberg, Ahmed Hemani, Anshul Kumar
    Scheduling of Outputs in Grammar-based Hardware Synthesis of Data Communication Protocols. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:596-0 [Conf]
    
91. Samuel Norman Hamilton, Alex Orailoglu
    Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:604-0 [Conf]
    
92. Stefan Höreth, Rolf Drechsler
    Dynamic Minimization of Word-Level Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:612-617 [Conf]
    
93. C. A. J. van Eijk
    Sequential Equivalence Checking without State Space Traversal. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:618-623 [Conf]
    
94. Lluis Ribas, Jordi Carrabina
    On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:624-0 [Conf]
    
95. 
    Silicon Debug of Systems-on-Chips. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:632-0 [Conf]
    
96. Josef Eckmueller, Martin Groepl, Helmut E. Graeb
    Hierarchical Characterization of Analog Integrated CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:636-643 [Conf]
    
97. G. Droege, M. Thole, Ernst-Helmut Horneber
    EASY - a System for Computer-Aided Examination of Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:644-648 [Conf]
    
98. Lars Hedrich, Erich Barke
    A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:649-0 [Conf]
    
99. Debabrata Ghosh, Nevin Kapur, Franc Brglez, Justin E. Harlow III
    Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:656-663 [Conf]
    
100. Aiguo Lu, Guenter Stenz, Frank M. Johannes
     Technology Mapping for Minimizing Gate and Routing Area. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:664-669 [Conf]
     
101. Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante
     Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:670-0 [Conf]
     
102. Jean Michel Daga, E. Ottaviano, Daniel Auvergne
     Temperature Effect on Delay for Low Voltage Applications. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:680-685 [Conf]
     
103. Qi Wang, Sarma B. K. Vrudhula
     Data Driven Power Optimization of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:686-691 [Conf]
     
104. Jaewon Oh, Massoud Pedram
     Gated Clock Routing Minimizing the Switched Capacitance. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:692-697 [Conf]
     
105. Yi-Min Jiang, Kwang-Ting Cheng
     Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:698-0 [Conf]
     
106. Norbert Wehn, Søren Hein
     Embedded DRAM Architectural Trade-Offs. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:704-708 [Conf]
     
107. Francky Catthoor
     Energy-Delay Efficient Data Storage and Transfer Architectures: Circuit Technology versus Design Methodology Solutions. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:709-0 [Conf]
     
108. Jan Vandenbussche, Stéphane Donnay, Francky Leyn, Georges G. E. Gielen, Willy M. C. Sansen
     Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:716-720 [Conf]
     
109. R. Rosenberger, Sorin A. Huss
     A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:721-728 [Conf]
     
110. Labros Bisdounis, Odysseas G. Koufopavlou, Constantinos E. Goutis, Spiridon Nikolaidis
     Switching Response Modeling of the CMOS Inverter for Sub-micron Devices. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:729-0 [Conf]
     
111. David Ihsin Cheng
     On Removing Multiple Redundancies in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:738-742 [Conf]
     
112. Christoph Scholl
     Multi-output Functional Decomposition with Exploitation of Don't Cares. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:743-748 [Conf]
     
113. J. W. J. M. Rutten, Michel R. C. M. Berkelaar, C. A. J. van Eijk, M. A. J. Kolsteren
     An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:749-754 [Conf]
     
114. Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya
     Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:755-0 [Conf]
     
115. Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino
     Power Estimation of Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:762-766 [Conf]
     
116. Alessandro Bogliolo, Luca Benini, Giovanni De Micheli
     Characterization-Free Behavioral Power Modeling. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:767-773 [Conf]
     
117. Diana Marculescu, Radu Marculescu, Massoud Pedram
     Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:774-0 [Conf]
     
118. Steven Vercauteren, Diederik Verkest, Gjalt G. de Jong, Bill Lin
     Efficient Verification using Generalized Partial Order Analysis. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:782-789 [Conf]
     
119. Enric Pastor, Jordi Cortadella
     Efficient Encoding Schemes for Symbolic Analysis of Petri Nets. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:790-795 [Conf]
     
120. Maroun Kassab, Eduard Cerny, Sidi Aourid, Thomas H. Krodel
     Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:796-802 [Conf]
     
121. Evguenii I. Goldberg, Yuji Kukimoto, Robert K. Brayton
     Combinational Verification based on High-Level Functional Specifications. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:803-0 [Conf]
     
122. Salvador Mir, Adoración Rueda, Diego Vázquez, José Luis Huertas
     Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:810-814 [Conf]
     
123. Michel Renovell, Florence Azaïs, Yves Bertrand
     Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:815-821 [Conf]
     
124. Walter M. Lindermeir, Thomas J. Vogels, Helmut E. Graeb
     Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:822-0 [Conf]
     
125. Olivier Coudert
     A New Paradigm for Dichotomy-based Constrained Encoding. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:830-834 [Conf]
     
126. Manuel Martínez, Maria J. Avedillo, José M. Quintana, José L. Huertas
     A Dynamic Model for the State Assignment Problem. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:835-839 [Conf]
     
127. Naresh Maheshwari, Sachin S. Sapatnekar
     Efficient Minarea Retiming of Large Level-Clocked Circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:840-0 [Conf]
     
128. Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha
     IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:848-854 [Conf]
     
129. Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura
     Instruction Scheduling for Power Reduction in Processor-Based System Design. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:855-860 [Conf]
     
130. Luca Benini, Giovanni De Micheli, Donatella Sciuto, Enrico Macii, Cristina Silvano
     Address Bus Encoding Techniques for System-Level Power Optimization. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:861-0 [Conf]
     
131. Michael Mrva, Klaus Buchenrieder, Rainer Kress
     A Scalable Architecture for Multi-threaded JAVA Applications. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:868-874 [Conf]
     
132. Valentina Salapura, Michael Gschwind
     Hardware/Software Co-Design of a Fuzzy RISC Processor. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:875-882 [Conf]
     
133. Kazushige Higuchi, Kazuhiro Shirakawa
     Innovative System-level Design Environment Based on FORM for Transport Processing System. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:883-0 [Conf]
     
134. Joao Paulo Costa, Mike Chou, L. Miguel Silveira
     Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC's. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:892-898 [Conf]
     
135. Michael W. Tian, C.-J. Richard Shi
     Efficient DC Fault Simulation of Nonlinear Analog Circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:899-904 [Conf]
     
136. Juan A. Prieto, Adoración Rueda, Ian A. Grout, Eduardo J. Peralías, José L. Huertas, Andrew M. D. Richardson
     An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:905-0 [Conf]
     
137. R. Niemann, Peter Marwedel
     Synthesis of Communicating Controllers for Concurrent Hardware/Software Systems. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:912-913 [Conf]
     
138. Marisa Luisa López-Vallejo, Carlos Angel Iglesias, Juan Carlos López
     A Knowledge-based System for Hardware-Software Partitioning. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:914-915 [Conf]
     
139. Tom J. Kazmierski
     A Formal Description of VHDL-AMS Analogue Systems. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:916-920 [Conf]
     
140. Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, L. Volpe
     Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:921-922 [Conf]
     
141. Davor Runje, Mario Kovac
     Universal Strong Encryption FPGA Core Implementation. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:923-924 [Conf]
     
142. Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
     Data Cache Sizing for Embedded Processor Applications. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:925-926 [Conf]
     
143. Jean Paul Calvez, Dominique Heller, F. Muller, Olivier Pasquier
     A Programmable Multi-Language Generator for CoDesign. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:927-928 [Conf]
     
144. Anupam Basu, Rainer Leupers, Peter Marwedel
     Register-Constrained Address Computation in DSP Programs. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:929-930 [Conf]
     
145. Thomas Müller-Wipperfürth, Richard Hagelauer
     Graphical Entry of FSMDs Revisited: Putting Graphical Models on a Solid Base. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:931-932 [Conf]
     
146. George Economakos, George K. Papakonstantinou, Panayotis Tsanakas
     AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:933-934 [Conf]
     
147. Serafín Olcoz, Ana Castellvi, Maria Garcia, Jose Angel Gomez
     Static Analysis Tools for Soft-Core Reviews and Audits. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:935-936 [Conf]
     
148. Michael G. Wahl, Holger Völkel
     A VHDL SGRAM Model for the Validation Environment of a High Performance Graphic Processor. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:937-938 [Conf]
     
149. Hans-Georg Martin, Wolfgang Rosenstiel
     A Comparing Study of Technology Mapping for FPGA. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:939-940 [Conf]
     
150. Tom J. Kazmierski
     Fuzzy-logic digital-analogue interfaces for accurate mixed-signal simulation. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:941-944 [Conf]
     
151. Wonyong Sung, Soonhoi Ha
     Optimized Timed Hardware Software Cosimulation without Roll-back. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:945-946 [Conf]
     
152. Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez
     A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:947-948 [Conf]
     
153. Jie Gong, Chih-Tung Chen, Kayhan Küçükçakar
     Architectural Rule Checking for High-level Synthesis. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:949-950 [Conf]
     
154. Hideaki Kimura, Norihito Iyenaga
     A Unified Technique for PCB/MCM Design by Combining Electromagnetic Field Analysis with Circuit Simulator. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:951-952 [Conf]
     
155. Petra Nordholz, Hartmut Grabinski, Dieter Treytnar, Jan Otterstedt, Dirk Niggemeyer, Uwe Arz, T. W. Williams
     Core Interconnect Testing Hazards. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:953-954 [Conf]
     
156. Teresa Riesgo, Yago Torroja, Eduardo de la Torre, J. Uceda
     Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:955-956 [Conf]
     
157. Cristiana Bolchini, Fabio Salice, Donatella Sciuto
     Fault Analysis in Networks with Concurrent Error Detection Properties. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:957-958 [Conf]
     
158. M. Svajda, B. Straka, Hans A. R. Manhaeve
     IOCIMU - An Integrated Off-Chip IDDQ Measurement Unit. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:959-960 [Conf]
     
159. Markus Wolf, Ulrich Kleine
     Automatic Topology Optimization for Analog Module Generators. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:961-962 [Conf]
     
160. Anatoly Prihozhy
     Asynchronous Scheduling and Allocation. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:963-964 [Conf]
     
161. Matthias Ringe, Thomas Lindenkreuz, Erich Barke
     Path Verification Using Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:965-966 [Conf]
     
162. Sumit Roy, Harm Arts, Prithviraj Banerjee
     PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean Expressions. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:967-968 [Conf]
     
163. Wolfgang Roethig, A. M. Zarkesh, M. Andrews
     Power and Timing Modeling for ASIC Designs. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:969-970 [Conf]
     
164. Bogdan G. Arsintescu, Ralph H. J. M. Otten
     Constraints Space Management for the Layout of Analog IC's. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:971-972 [Conf]
     
165. Irith Pomeranz, Sudhakar M. Reddy
     A Synthesis Procedure for Flexible Logic Functions. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:973-974 [Conf]
     
166. Felix Nicoli
     Denotational Semantics of a Behavioral Subset of VHDL. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:975-976 [Conf]
     
167. José M. Mendías, Román Hermida
     Correct High-Level Synthesis: a Formal Perspective. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:977-978 [Conf]
     
168. Mehrdad Nourani, Christos A. Papachristou
     A Bypass Scheme for Core-Based System Fault Testing. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:979-980 [Conf]
     
169. Cecilia Metra, Michele Favalli, Bruno Riccò
     Highly Testable and Compact 1-out-of-n Code Checker with Single Output. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:981-982 [Conf]
     
170. Irith Pomeranz, Sudhakar M. Reddy
     Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:983-984 [Conf]
     
171. Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija
     CMOS Combinational Circuit Sizing by Stage-wise Tapering. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:985-988 [Conf]
     
172. J. Velasco-Medina, Th. Calin, Michael Nicolaidis
     Fault Detection for Linear Analog Circuits Using Current Injection. [Citation Graph (0, 0)][DBLP]
     DATE, 1998, pp:987-0 [Conf]