Conferences in DBLP

Design, Automation, and Test in Europe (date)
2002 (conf/date/2002)

1. Taylor Scanlon
   Global Responsibilities in SOC Design. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:12-13 [Conf]
   
2. Hugo De Man
   On Nanoscale Integration and Gigascale Complexity in the Post.Com World. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:12- [Conf]
   
3. Ian Phillips
   How to Choose Semiconductor IP? - Embedded Processor. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:14- [Conf]
   
4. Vincent Ratford
   Make Your SoC Design a Winner: Select the Right Memory IP. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:15- [Conf]
   
5. Grant Martin
   How to Choose Semiconductor IP: Embedded Software. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:16- [Conf]
   
6. Pierre Bricaud
   IP Day: How to Choose Semiconductor IP? [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:17-19 [Conf]
   
7. Roope Kaivola, Naren Narasimhan
   Formal Verification of the Pentium ® 4 Floating-Point Multiplier. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:20-27 [Conf]
   
8. Miroslav N. Velev
   Using Rewriting Rules and Positive Equality to Formally Verify Wide-Issue Out-of-Order Microprocessors with a Reorder Buffer. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:28-35 [Conf]
   
9. Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama
   Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:36-43 [Conf]
   
10. Marco A. Peña, Jordi Cortadella, Alexander B. Smirnov, Enric Pastor
    A Case Study for the Verification of Complex Timed Circuits: IPCMOS. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:44-53 [Conf]
    
11. Juan de Vicente, Juan Lanchares, Román Hermida
    FPGA Placement by Thermodynamic Combinatorial Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:54-60 [Conf]
    
12. Changwen Zhuang, Yoji Kajitani, Keishi Sakanushi, Liyan Jin
    An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:61-68 [Conf]
    
13. Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang
    Arbitrary Convex and Concave Rectilinear Module Packing Using TCG. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:69-77 [Conf]
    
14. Michael Pronath, Helmut E. Graeb, Kurt Antreich
    A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:78-83 [Conf]
    
15. Saravanan Padmanaban, Spyros Tragoudas
    Exact Grading of Multiple Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:84-88 [Conf]
    
16. Zaid Al-Ars, A. J. van de Goor
    Modeling Techniques and Tests for Partial Faults in Memory Devices. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:89-93 [Conf]
    
17. Sooryong Lee, Brad Cobb, Jennifer Dworak, Michael R. Grimaila, M. Ray Mercer
    A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:94-101 [Conf]
    
18. Davide Bertozzi, Luca Benini, Giovanni De Micheli
    Low Power Error Resilient Encoding for On-Chip Data Buses. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:102-109 [Conf]
    
19. Tajana Simunic, Stephen P. Boyd
    Managing Power Consumption in Networks on Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:110-116 [Conf]
    
20. Sandy Irani, Rajesh K. Gupta, Sandeep K. Shukla
    Competitive Analysis of Dynamic Power Management Strategies for Systems with Multiple Power Savings States. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:117-123 [Conf]
    
21. Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
    AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:124-131 [Conf]
    
22. Vernon P. Essi Jr.
    IP is All About Implementation and Customer Satisfaction. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:132-133 [Conf]
    
23. Evguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton
    Using Problem Symmetry in Search Based Satisfiability Algorithms. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:134-141 [Conf]
    
24. Evguenii I. Goldberg, Yakov Novikov
    BerkMin: A Fast and Robust Sat-Solver. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:142-149 [Conf]
    
25. Gianpiero Cabodi, Paolo Camurati, Stefano Quer
    Dynamic Scheduling and Clustering in Symbolic Image Computation. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:150-157 [Conf]
    
26. Luca Macchiarulo, Enrico Macii, Massimo Poncino
    Wire Placement for Crosstalk Energy Minimization in Address Buses. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:158-162 [Conf]
    
27. Chris H. Kim, Kaushik Roy
    Dynamic VTH Scaling Scheme for Active Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:163-167 [Conf]
    
28. Ana Azevedo, Ilya Issenin, Radu Cornea, Rajesh Gupta, Nikil D. Dutt, Alexander V. Veidenbaum, Alexandru Nicolau
    Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:168-175 [Conf]
    
29. Arindam Mukherjee, Kai Wang, Lauren Hui Chen, Malgorzata Marek-Sadowska
    Sizing Power/Ground Meshes for Clocking and Computing Circuit Components. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:176-185 [Conf]
    
30. Ramakrishna Voorakaranam, Sasikumar Cherubal, Abhijit Chatterjee
    A Signature Test Framework for Rapid Production Testing of RF Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:186-191 [Conf]
    
31. Carlo Guardiani, Patrick McNamara, Lidia Daldoss, Sharad Saxena, Stefano Zanella, Wei Xiang, Suli Liu
    Analog IP Testing: Diagnosis and Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:192-196 [Conf]
    
32. Christoph Hoffmann
    A New Design Flow and Testability Measure for the Generation of a Structural Test and BIST for Analogue and Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:197-204 [Conf]
    
33. Y. Lechuga, R. Mozuelos, Mar Martínez, Salvador Bracho
    Built-In Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal Ics. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:205-213 [Conf]
    
34. L. Ghanmi, A. Ghrab, M. Hamdoun, B. Missaoui, K. Skiba, Gabriele Saucier
    E-Design Based on the Reuse Paradigm. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:214-220 [Conf]
    
35. André Schneider, Karl-Heinz Diener, Eero Ivask, Jaan Raik, Raimund Ubar, P. Miklos, T. Cibáková, Elena Gramatová
    Internet-Based Collaborative Test Generation with MOSCITO. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:221-226 [Conf]
    
36. Tom J. Kazmierski, Neil Clayton
    A Two-Tier Distributed Electronic Design Framework. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:227-231 [Conf]
    
37. Achim Rettberg, Wolfgang Thronicke
    Embedded System Design Based On Webservices. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:232-237 [Conf]
    
38. Vassilios Gerousis, Oz Levia, Pierre G. Paulin, Mark Pinto, Chris Rowen, Gabriele Saucier
    Who Owns the Platform? [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:238-239 [Conf]
    
39. Michael Nicolaidis
    IP for Embedded Robustness. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:240-241 [Conf]
    
40. Stephen Pateras
    Embedded Diagnosis IP. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:242-243 [Conf]
    
41. Eric Dupont, Michael Nicolaidis, Peter Rohr
    Embedded Robustness Ips. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:244-247 [Conf]
    
42. Sezer Gören, F. Joel Ferguson
    CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:248-254 [Conf]
    
43. Mitchell A. Thornton, Kenneth Fazel, Robert B. Reese, Cherrice Traver
    Generalized Early Evaluation in Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:255-259 [Conf]
    
44. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:260-267 [Conf]
    
45. Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
    A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:268-273 [Conf]
    
46. Rolf Popp, Joerg Oehmen, Lars Hedrich, Erich Barke
    Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:274-278 [Conf]
    
47. Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
    Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer Matrices. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:279-284 [Conf]
    
48. Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre
    Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:285-291 [Conf]
    
49. 
    EDA Tools for RF: Myth or Reality? [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:292-295 [Conf]
    
50. Tin-Man Lee, Wayne Wolf, Jörg Henkel
    Dynamic Runtime Re-Scheduling Allowing Multiple Implementations of a Task for Platform-Based Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:296-301 [Conf]
    
51. Robert Pasko, Serge Vernalde, Patrick Schaumont
    Techniques to Evolve a C++ Based System Design Language. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:302-309 [Conf]
    
52. Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda, Ralf Seepold, Natividad Martínez Madrid
    A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:310-315 [Conf]
    
53. W. Rahajandraibe, Christian Dufaza, Daniel Auvergne, B. Cialdella, B. Majoux, V. Chowdhury
    Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:316-321 [Conf]
    
54. S. Lampe, S. Laur
    Global Optimization Applied to the Oscillator Problem. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:322-327 [Conf]
    
55. Joseph Borel, G. Matheron, Ahmed Amine Jerraya, S. Resve, M. Rogers, Wolfgang Rosenstiel, Irmtraud Rugen-Herzig, F. Theewen
    MEDEA+ and ITRS Roadmaps. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:328-329 [Conf]
    
56. Tiberiu Chelcea, Steven M. Nowick, Andrew Bardsley, Doug Edwards
    A Burst-Mode Oriented Back-End for the Balsa Synthesis System. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:330-337 [Conf]
    
57. Victor Khomenko, Maciej Koutny, Alexandre Yakovlev
    Detecting State Coding Conflicts in STGs Using Integer Programming. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:338-345 [Conf]
    
58. Soha Hassoun, Eduardo Calvillo-Gámez, Christopher Cromer
    Verifying Clock Schedules in the Presence of Cross Talk. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:346-351 [Conf]
    
59. Michaël Goffioul, Piet Wambacq, Gerd Vandersteen, Stéphane Donnay
    Analysis of Nonlinearities in RF Front-End Architectures Using a Modified Volterra Series Approach . [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:352-356 [Conf]
    
60. Jan Vandenbussche, Erik Lauwers, K. Uyttenhove, Michiel Steyaert, Georges G. E. Gielen
    Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:357-361 [Conf]
    
61. Ricardo Carmona-Galán, Francisco Jiménez-Garrido, Rafael Domínguez-Castro, Servando Espejo-Meana, Ángel Rodríguez-Vázquez
    Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:362-367 [Conf]
    
62. Amit R. Pandey, Janak H. Patel
    An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:368-375 [Conf]
    
63. Ismet Bayraktaroglu, Alex Orailoglu
    Gate Level Fault Diagnosis in Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:376-381 [Conf]
    
64. Chunsheng Liu, Krishnendu Chakrabarty, Michael Gössel
    An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:382-386 [Conf]
    
65. Sherief Reda, Alex Orailoglu
    Reducing Test Application Time Through Test Data Mutation Encoding. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:387-395 [Conf]
    
66. Heiko Michel, Alexander Worm, Norbert Wehn, Michael Münch
    Hardware/Software Trade-Offs for Advanced 3G Channel Coding. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:396-401 [Conf]
    
67. Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil D. Dutt, Alexandru Nicolau
    An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:402-408 [Conf]
    
68. Stefan Steinke, Lars Wehmeyer, Bo-Sik Lee, Peter Marwedel
    Assigning Program and Data Objects to Scratchpad for Energy Reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:409-417 [Conf]
    
69. Giovanni De Micheli, Luca Benini
    Networks on Chip: A New Paradigm for Systems on Chip Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:418-419 [Conf]
    
70. Joseph Williams, Nevin Heintze, Bryan D. Ackland
    Communication Mechanisms for Parallel DSP Systems on a Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:420-422 [Conf]
    
71. Kees G. W. Goossens, Paul Wielage, Ad M. G. Peeters, Jef L. van Meerbergen
    Networks on Silicon: Combining Best-Effort and Guaranteed Services. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:423-427 [Conf]
    
72. Tanja Van Achteren, Geert Deconinck, Francky Catthoor, Rudy Lauwereins
    Data Reuse Exploration Techniques for Loop-Dominated Application. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:428-535 [Conf]
    
73. Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam
    EAC: A Compiler Framework for High-Level Energy Estimation and Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:436-442 [Conf]
    
74. Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau
    Power Savings in Embedded Processors through Decode Filer Cache. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:443-448 [Conf]
    
75. Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii
    Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:449-450 [Conf]
    
76. Murat R. Becer, Vladimir Zolotov, David Blaauw, Rajendran Panda, Ibrahim N. Hajj
    Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:456-464 [Conf]
    
77. Goeran Jerke, Jens Lienig
    Hierarchical Current Density Verification for Electromigration Analysis in Arbitrary Shaped Metallization Patterns of Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:464-469 [Conf]
    
78. Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu
    A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:470-477 [Conf]
    
79. Érika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu
    Test Planning and Design Space Exploration in a Core-Based Environment. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:478-485 [Conf]
    
80. Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Ping Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin
    A Hierarchical Test Scheme for System-On-Chip Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:486-490 [Conf]
    
81. Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
    Efficient Wrapper/TAM Co-Optimization for Large SOCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:491-498 [Conf]
    
82. Andrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei
    Beyond UML to an End-of-Line Functional Test Engine. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:499-505 [Conf]
    
83. Kai Richter, Rolf Ernst
    Event Model Interfaces for Heterogeneous System Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:506-513 [Conf]
    
84. Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles
    Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:514-521 [Conf]
    
85. JoAnn M. Paul, Donald E. Thomas
    A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:522-528 [Conf]
    
86. Daniel Menard, Olivier Sentieys
    Automatic Evaluation of the Accuracy of Fixed-Point Algorithms. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:529-537 [Conf]
    
87. K. Brock, C. Edwards, R. Lannoo, Ulf Schlichtmann, Antun Domic, Jacques Benkoski, David Overhauser, M. Kliment
    Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:538-539 [Conf]
    
88. Davide Rizzo, Osvaldo Colavin
    A Video Compression Case Study on a Reconfigurable VLIW Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:540-546 [Conf]
    
89. Marcos Sanchez-Elez, Milagros Fernández, Rafael Maestre, Fadi J. Kurdahi, Román Hermida, Nader Bagherzadeh
    A Complete Data Scheduler for Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:547-552 [Conf]
    
90. Gilles Sassatelli, Lionel Torres, Pascal Benoit, Thierry Gil, Camille Diou, Gaston Cambon, Jérôme Galy
    Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:553-558 [Conf]
    
91. Jürgen Teich, Markus Köster
    (Self-)reconfigurable Finite State Machines: Theory and Implementation. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:559-567 [Conf]
    
92. Emrah Acar, Sani R. Nassif, Lawrence T. Pileggi
    A Linear-Centric Simulation Framework for Parametric Fluctuations. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:568-575 [Conf]
    
93. Mohamed Dessouky, DiaaEldin Sayed
    Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:576-580 [Conf]
    
94. Robert Schwencker, Frank Schenkel, Michael Pronath, Helmut E. Graeb
    Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:581-585 [Conf]
    
95. Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Frans Verbeyst
    High-Frequency Nonlinear Amplifier Model for the Efficient Evaluation of Inband Distortion Under Nonlinear Load-Pull Conditions. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:586-591 [Conf]
    
96. Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian
    Effective Software Self-Test Methodology for Processor Cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:592-597 [Conf]
    
97. Anshuman Chandra, Krishnendu Chakrabarty
    Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:598-603 [Conf]
    
98. Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici
    Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:604-611 [Conf]
    
99. Michele Favalli, Cecilia Metra
    Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:612-619 [Conf]
    
100. Sungjoo Yoo, Gabriela Nicolescu, Lovic Gauthier, Ahmed Amine Jerraya
     Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:620-627 [Conf]
     
101. Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie, Byron Krauter
     Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:628-633 [Conf]
     
102. Peng Li, Lawrence T. Pileggi
     A Linear-Centric Modeling Approach to Harmonic Balance Analysis. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:634-639 [Conf]
     
103. Paul I. Pénzes, Alain J. Martin
     An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:640-649 [Conf]
     
104. Ralph H. J. M. Otten, Raul Camposano, Patrick Groeneveld
     Design Automation for Deepsubmicron: Present and Future. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:650-659 [Conf]
     
105. J. Bryan Lewis, Ivo Bolsens, Rudy Lauwereins, Chris Wheddon, Bhusan Gupta, Yankin Tanurhan
     Reconfigurable SoC - What Will it Look Like? [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:660-663 [Conf]
     
106. Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
     Congestion-Aware Logic Synthesis. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:664-671 [Conf]
     
107. Thomas Kutzschebauch, Leon Stok
     Layout Driven Decomposition with Congestion Consideration. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:672-676 [Conf]
     
108. Kolja Sulimma, Wolfgang Kunz, Ingmar Neumann, Lukas VanGinneken
     Improving Placement under the Constant Delay Model. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:677-682 [Conf]
     
109. Tzyy-Kuen Tien, Tong-Kai Tsai, Shih-Chieh Chang
     Crosstalk Alleviation for Dynamic PLAs. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:683-689 [Conf]
     
110. Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao
     Flip-Flop and Repeater Insertion for Early Interconnect Planning. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:690-695 [Conf]
     
111. Wai-Chiu Wong, Chiu-Wing Sham, Evangeline F. Y. Young
     Congestion Estimation with Buffer Planning in Floorplan Design. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:696-701 [Conf]
     
112. Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao
     Maze Routing with Buffer Insertion under Transition Time Constraints. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:702-707 [Conf]
     
113. Li Ding 0002, Pinaki Mazumder
     Optimal Transistor Tapering for High-Speed CMOS Circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:708-715 [Conf]
     
114. Andreas G. Veneris, Jiang Brandon Liu, Mandana Amiri, Magdy S. Abadir
     Incremental Diagnosis and Correction of Multiple Faults and Errors. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:716-721 [Conf]
     
115. Irith Pomeranz, Sudhakar M. Reddy
     Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:722-729 [Conf]
     
116. Vivekananda M. Vedula, Jacob A. Abraham
     FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:730-735 [Conf]
     
117. Frederic Doucet, Sandeep K. Shukla, Rajesh K. Gupta, Masato Otsuka
     An Environment for Dynamic Component Composition for Efficient Co-Design . [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:736-743 [Conf]
     
118. Fabrizio Ferrandi, Michele Rendine, Donatella Sciuto
     Functional Verification for SystemC Descriptions Using Constraint Solving. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:744-751 [Conf]
     
119. M. D. Edwards, P. N. Green
     The Modelling of Embedded Systems Using HASoC. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:752-759 [Conf]
     
120. Alex Doboli, Ranga Vemuri
     A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:760-769 [Conf]
     
121. Bran Selic
     The Real-Time UML Standard: Definition and Application. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:770-772 [Conf]
     
122. Grant Martin
     UML for Embedded Systems Specification and Design: Motivation and Overview. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:773-775 [Conf]
     
123. Gjalt G. de Jong
     A UML-Based Design Methodology for Real-Time and Embedded Sytems. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:776-781 [Conf]
     
124. Gang Quan, Xiaobo Hu
     Minimum Energy Fixed-Priority Scheduling for Variable Voltage Processor. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:782-787 [Conf]
     
125. Woonseok Kim, Jihong Kim, Sang Lyul Min
     A Dynamic Voltage Scaling Algorithm for Dynamic-Priority Hard Real-Time Systems Using Slack Time Analysis. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:788-794 [Conf]
     
126. George Logothetis, Klaus Schneider
     Extending Synchronous Languages for Generating Abstract Real-Time Models. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:795-803 [Conf]
     
127. David Goren, Michael Zelikson, Tiberiu C. Galambos, Rachel Gordin, Betty Livshitz, Alon Amir, Anatoly Sherman, Israel A. Wagner
     An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach . [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:804-811 [Conf]
     
128. Lauren Hui Chen, Malgorzata Marek-Sadowska
     Closed-Form Crosstalk Noise Metrics for Physical Design Applications. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:812-819 [Conf]
     
129. Qinwei Xu, Pinaki Mazumder
     Formulation of Low-Order Dominant Poles for Y-Matrix of Interconnects. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:820-825 [Conf]
     
130. Bernard N. Sheehan
     Library Compatible Ceff for Gate-Level Timing. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:826-831 [Conf]
     
131. Cecilia Metra, Luca Schiano, Bruno Riccò, Michele Favalli
     Self-Checking Scheme for the On-Line Testing of Power Supply Noise. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:832-836 [Conf]
     
132. Régis Leveugle
     Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:837-841 [Conf]
     
133. Kaijie Wu, Ramesh Karri
     Exploiting Idle Cycles for Algorithm Level Re-Computing. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:842-846 [Conf]
     
134. Luis Berrojo, I. Gónzólez, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López
     New Techniques for Speeding-Up Fault-Injection Campaigns. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:847-853 [Conf]
     
135. Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst
     System Design for Flexibility. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:854-861 [Conf]
     
136. Anshuman Nayak, Malay Haldar, Alok N. Choudhary, Prithviraj Banerjee
     Accurate Area and Delay Estimators for FPGAs. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:862-869 [Conf]
     
137. Klaus Buchenrieder, Andreas Pyttel, Alexander Sedlmeier
     A Powerful System Design Methodology Combining OCAPI and Handel-C for Concept Engineering. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:870-874 [Conf]
     
138. Nick Savoiu, Sandeep K. Shukla, Rajesh K. Gupta
     Automated Concurrency Re-Assignment in High Level System Models for Efficient System-Level Simulation. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:875-883 [Conf]
     
139. R. Sommer, Irmtraud Rugen-Herzig, E. Hennig, Umberto Gatti, Piero Malcovati, Franco Maloberti, Karsten Einwich, Christoph Clauß, Peter Schwarz, G. Noessing
     From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:884-893 [Conf]
     
140. Peter Grun, Nikil D. Dutt, Alexandru Nicolau
     Memory System Connectivity Exploration. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:894-901 [Conf]
     
141. Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas J. W. Clarke
     Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:902-908 [Conf]
     
142. María C. Molina, José M. Mendías, Román Hermida
     Multiple-Precision Circuits Allocation Independent of Data-Objects Length. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:909-915 [Conf]
     
143. Emad Gad, Michel S. Nakhla
     Efficient Model Reduction of Linear Time-Varying Systems via Compressed Transient System Function. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:916-922 [Conf]
     
144. Carlos P. Coelho, Luis Miguel Silveira, Joel R. Phillips
     Passive Constrained Rational Approximation Algorithm Using Nevanlinna-Pick Interpolation. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:923-930 [Conf]
     
145. Yiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Kaushik Roy
     Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:931-937 [Conf]
     
146. Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
     An Optimal Algorithm for the Automatic Generation of March Tests. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:938-943 [Conf]
     
147. A. J. van de Goor, Magdy S. Abadir, Alan Carlin
     Minimal Test for Coupling Faults in Word-Oriented Memories. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:944-948 [Conf]
     
148. Michael S. Hsiao
     Maximizing Impossibilities for Untestable Fault Identification. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:949-953 [Conf]
     
149. Soumitra Bose
     Automated Modeling of Custom Digital Circuits for Test. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:954-963 [Conf]
     
150. G. Arrigoni, L. Duchini, Claudio Passerone, Luciano Lavagno, Yosinori Watanabe
     False Path Elimination in Quasi-Static Scheduling. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:964-970 [Conf]
     
151. Gianluca Bontempi, Wido Kruijtzer
     A Data Analysis Method for Software Performance Prediction. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:971-976 [Conf]
     
152. Nikolaos D. Liveris, Nikolaos D. Zervas, Dimitrios Soudris, Constantinos E. Goutis
     A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:977-983 [Conf]
     
153. Mahmut T. Kandemir
     A Compiler-Based Approach for Improving Intra-Iteration Data Reuse. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:984-991 [Conf]
     
154. Joseph Borel
     European CAD from the 60's to the New Millenium. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:992-993 [Conf]
     
155. Steve Guccione, Diederik Verkest, Ivo Bolsens
     Design Technology for Networked Reconfigurable FPGA Platforms. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:994-999 [Conf]
     
156. Recep O. Ozdag, Peter A. Beerel, Montek Singh, Steven M. Nowick
     High-Speed Non-Linear Asynchronous Pipelines. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1000-1007 [Conf]
     
157. Marcos Ferretti, Peter A. Beerel
     Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1008-1015 [Conf]
     
158. Chunhong Chen, Majid Sarrafzadeh
     Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1016-1020 [Conf]
     
159. Qin Zhao, Bart Mesman, Twan Basten
     Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1021-1027 [Conf]
     
160. Thomas Brandtner, Robert Weigel
     Hierarchical Simulation of Substrate Coupling in Mixed-Signal ICs Considering the Power Supply Network. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1028-1032 [Conf]
     
161. B. L. A. Van Thielen, G. A. E. Vandenbosch
     Fast Method to Include Parasitic Coupling in Circuit Simulations. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1033-1037 [Conf]
     
162. Li Ding 0002, Pinaki Mazumder
     Accurate Estimating Simultaneous Switching Noises by Using Application Specific Device Modeling. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1038-1043 [Conf]
     
163. Igor S. Stievano, Flavio G. Canavero, Ivan A. Maio, Z. Chen, Wiren D. Becker, George A. Katopis
     Macromodeling of Digital I/O Ports for System EMC Assessment . [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1044-1049 [Conf]
     
164. Joel Blasquez, Marten van Hulst, Andrea Fedeli, Jean-Luc Lambert, Dominique Borrione, Coby Hanoch, Pierre Bricaud
     Formal Verification Techniques: Industrial Status and Perspectives. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1050-1051 [Conf]
     
165. Armita Peymandoust, Tajana Simunic, Giovanni De Micheli
     Low Power Embedded Software Optimization Using Symbolic Algebra. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1052-1058 [Conf]
     
166. Tiehan Lv, Wayne Wolf, Jörg Henkel, Haris Lekatsas
     An Adaptive Dictionary Encoding Scheme for SOC Data Buses. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1059- [Conf]
     
167. Peter Petrov, Alex Orailoglu
     Power Efficient Embedded Processor Ip's through Application-Specific Tag Compression in Data Caches. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1065-1071 [Conf]
     
168. Martin Palkovic, Miguel Miranda, Francky Catthoor
     Systematic Power-Performance Trade-Off in MPEG-4 by Means of Selective Function Inlining Steered by Address Optimization Opportunities. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1072-1079 [Conf]
     
169. Walter Hartong, Lars Hedrich, Erich Barke
     An Approach to Model Checking for Nonlinear Analog Systems. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1080- [Conf]
     
170. Slawomir Pilarski, Gracia Hu
     Speeding up SAT for EDA. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1081- [Conf]
     
171. Fadi A. Aloul, Maher N. Mneimneh, Karem A. Sakallah
     Search-Based SAT Using Zero-Suppressed BDDs. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1082- [Conf]
     
172. Manuel Martínez, Maria J. Avedillo, José M. Quintana, H. Süß, Manfred Koegst
     An Encoding Technique for Low Power CMOS Implementations of Controllers. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1083- [Conf]
     
173. Elena Dubrova
     Composition Trees in Finding Best Variable Orderings for ROBDDs. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1084- [Conf]
     
174. Joerg Abke, Erich Barke
     A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs . [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1085- [Conf]
     
175. Peyman Rezvani, Massoud Pedram
     Concurrent and Selective Logic Extraction with Timing Consideration. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1086- [Conf]
     
176. Dariusz Kania
     Improved Technology Mapping for PAL-Based Devices Using a New Approach to Multi-Output Boolean Functions. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1087- [Conf]
     
177. Michel R. C. M. Berkelaar, Koen van Eijk
     Efficient and Effective Redundancy Removal for Million-Gate Circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1088- [Conf]
     
178. Alexandre V. Bystrov, Maciej Koutny, Alexandre Yakovlev
     Visualization of Partial Order Models in VLSI Design Flow. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1089- [Conf]
     
179. Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana
     High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1090- [Conf]
     
180. Jie S. Hu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
     Power-Efficient Trace Caches. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1091- [Conf]
     
181. Mahmut T. Kandemir, Ibrahim Kolcu
     Reducing Cache Access Energy in Array-Intensive Application. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1092- [Conf]
     
182. Carsten Nitsch, Udo Kebschull
     The Use of Runtime Configuration Capabilities for Networked Embedded Systems. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1093- [Conf]
     
183. Iouliia Skliarova, António de Brito Ferrari
     A SAT Solver Using Software and Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1094- [Conf]
     
184. Ralf Münzenberger, Matthias Dörfel, Frank Slomka, Richard Hofmann
     A New Time Model for the Specification, Design, Validation and Synthesis of Embedded Real-Time Systems. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1095- [Conf]
     
185. Martin Grajcar, Werner Grass
     Improved Constraints for Multiprocessor System Scheduling. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1096- [Conf]
     
186. Olga Peñalba, José M. Mendías, Román Hermida
     Maximizing Conditonal Reuse by Pre-Synthesis Transformations. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1097- [Conf]
     
187. Sunan Tugsinavisut, Peter A. Beerel
     Control Circuit Templates for Asynchronous Bundled-Data Pipelines. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1098- [Conf]
     
188. Olivier Peyran, Wenjun Zhuang
     Transforming Arbitrary Structures into Topologically Equivalent Slicing Structures. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1099- [Conf]
     
189. Chih-Hung Lee, Yu-Chung Lin, Wen-Yu Fu, Chun-Chiao Chang, Tsai-Ming Hsieh
     A New Formulation for SOC Floorplan Area Minimization Problem. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1100- [Conf]
     
190. Chris C. N. Chu, Evangeline F. Y. Young
     Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1101- [Conf]
     
191. Yazdan Aghaghiri, Massoud Pedram, Farzan Fallah
     EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1102- [Conf]
     
192. Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner
     Estimation of Power Consumption in Encoded Data Buses. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1103- [Conf]
     
193. Tran chi Hieu
     Optimization Techniques for Design of General and Feedback Linear Analog Amplifier with Symbolic Analysis. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1104- [Conf]
     
194. Antonio Luchetta, Stefano Manetti, Maria Cristina Piccirilli
     Critical Comparison among Some Analog Fault Diagnosis Procedures Based on Symbolic Techniques. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1105- [Conf]
     
195. Mircea R. Stan, Avishek Panigrahi
     The Selective Pull-Up (SP) Noise Immunity Scheme for Dynamic Circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1106- [Conf]
     
196. Andreia Cathelin, D. Saias, Didier Belot, Y. Leclercq, F. Clément
     Substrate Parasitic Extraction for RF Integrated Circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1107- [Conf]
     
197. David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin
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     DATE, 2002, pp:1108- [Conf]
     
198. Cristinel Ababei, Kia Bazargan
     Statistical Timing Driven Partitioning for VLSI Circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1109- [Conf]
     
199. Kenneth Francken, Martin Vogels, Ewout Martens, Georges G. E. Gielen
     DAISY-CT: A High-Level Simulation Tool for Continuous-Time Delta Sigma Modulators. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1110- [Conf]
     
200. A. Hassibi, Maria del Mar Hershenson
     Automated Optimal Design of Switched-Capacitor Filters. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1111- [Conf]
     
201. Tao Lin, Michael W. Beattie, Lawrence T. Pileggi
     On-Chip Inductance Models: 3D or Not 3D? [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1112- [Conf]
     
202. Hasan Ymeri, Bart Nauwelaers, Karen Maex, David De Roest, Michele Stucchi, Servaas Vandenberghe
     Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1113- [Conf]
     
203. Roni Khazaka, Michel S. Nakhla
     Compact Macromodel for Lossy Coupled Transmission Lines. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1114- [Conf]
     
204. Jean-Luc Levant, Mohammed Ramdani
     An EMC-Compliant Design Method of High-Density Integrated Circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1115- [Conf]
     
205. Irith Pomeranz, Janusz Rajski, Sudhakar M. Reddy
     Finding a Common Fault Response for Diagnosis during Silicon Debug. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1116- [Conf]
     
206. Suriya Ashok Kumar, Rafic Z. Makki, David Binkley
     I_DDT Testing of Embedded CMOS SRAMs. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1117- [Conf]
     
207. Swarup Bhunia, Kaushik Roy
     Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1118- [Conf]
     
208. Jun-Weir Lin, Chung-Len Lee, Jwu E. Chen
     An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1119- [Conf]
     
209. Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet
     On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1120- [Conf]
     
210. Rohit Kapur, Thomas W. Williams, M. Ray Mercer
     Directed-Binary Search in Logic BIST Diagnostics. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1121- [Conf]
     
211. Michele Favalli, Marcello Dalpasso
     An Evolutionary Approach to the Design of On-Chip Pseudorandom Test Pattern Generators. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1122- [Conf]
     
212. Irith Pomeranz, Yervant Zorian
     Fault Isolation Using Tests for Non-Isolated Blocks. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1123- [Conf]
     
213. Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre
     A Heuristic for Test Scheduling at System Level. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1124- [Conf]
     
214. Sandeep Koranne, Vishal Suhas Choudhary
     Formulation of SOC Test Scheduling as a Network Transportation Problem. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1125- [Conf]
     
215. Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira
     A Novel Methodology for the Concurrent Test of Partial and Dynamically Reconfigurable SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1126- [Conf]
     
216. Alexander V. Drozd, M. V. Lobachev, J. V. Drozd
     Efficient On-Line Testing Method for a Floating-Point Iterative Array Divider. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1127- [Conf]
     
217. Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon
     An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1128- [Conf]
     
218. Anton Sauer, Günter Elst, Ludger Krahn, Werner John
     The Fraunhofer Knowledge Network (FKN) for Training in Critical Design Disciplines. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1129- [Conf]
     
219. Leandro Soares Indrusiak, Manfred Glesner, Ricardo Augusto da Luz Reis
     Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1130- [Conf]
     
220. Bernd Stöhr, Michael Simmons, Joachim Geishauser
     FlexBench: Reuse of Verification IP to Increase Productivity. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1131- [Conf]
     
221. Juha-Pekka Soininen, Jari Kreku, Yang Qu
     Mappability Estimation of Architecture and Algorithm. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1132- [Conf]
     
222. Peter R. Wilson, J. Neil Ross, Mark Zwolinski, Andrew D. Brown, Yavuz Kiliç
     Behavioural Modelling of Operational Amplifier Faults Using VHDL-AMS. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1133- [Conf]
     
223. Klaus Hering
     A Parallel LCC Simulation System. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1134- [Conf]
     
224. Francesco Bruschi, Michele Chiamenti, Fabrizio Ferrandi, Donatella Sciuto
     Error Simulation Based on the SystemC Design Description Language. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1135- [Conf]
     
225. Dag Björklund, Johan Lilius
     Towards a Kernel Language for Heterogeneous Computing. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1136- [Conf]
     
226. Lukai Cai, Daniel Gajski, Paul Kritzinger, Mike Olivarez
     Top-Down System Level Design Methodology Using SpecC, VCC and SystemC. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1137- [Conf]
     
227. Laura Pozzi, Miljan Vuletic, Paolo Ienne
     Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1138- [Conf]
     
228. Hans Georg Brachtendorf, S. Lampe, Rainer Laur, Robert C. Melville, Peter Feldmann
     Steady State Calculation of Oscillators Using Continuation Methods. [Citation Graph (0, 0)][DBLP]
     DATE, 2002, pp:1139- [Conf]