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Conferences in DBLP

Design, Automation, and Test in Europe (date)
2004 (conf/date/2004)

  1. Robert C. Aitken, Fidel Muradali
    From Working Design Flow to Working Chips: Dependencies and Impacts of Methodology Decisions. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:2- [Conf]
  2. Greg Spirakis
    Opportunities and Challenges in Building Silicon Products in 65nm and Beyond. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:2-3 [Conf]
  3. Veikko Loukusa, Helena Pohjonen, Antti Ruha, Tarmo Ruotsalainen, Olli Varkki
    Systems on Chips Design: System Manufacturer Point of View. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:3-4 [Conf]
  4. Kihwan Choi, Ramakrishna Soma, Massoud Pedram
    Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-Off Based on the Ratio of Off-Chip Access to On-Chip Computation Times. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:4-9 [Conf]
  5. Sanjay Dandia
    Package Design for High Performance ICs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:5- [Conf]
  6. Bill Eklow
    IP Testing - The Future Differentiator? [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:6-9 [Conf]
  7. Kevin Skadron
    Hybrid Architectural Dynamic Thermal Management. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:10-15 [Conf]
  8. Adão Antônio de Souza Jr., Luigi Carro
    Highly Digital, Low-Cost Design of Statistic Signal Acquisition in SoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:10-15 [Conf]
  9. Faress Tissafi-Drissi, Ian O'Connor, Frédéric Gaffiot
    RUNE: Platform for Automated Design of Integrated Multi-Domain Systems. Application to High-Speed CMOS Photoreceiver Front-Ends. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:16-21 [Conf]
  10. Yen-Jen Chang, Chia-Lin Yang, Feipei Lai
    Value-Conscious Cache: Simple Technique for Reducing Cache Access Power. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:16-21 [Conf]
  11. Yiming Chen, Xiaojuen Yuan, David Scagnelli, James Mecke, Jeff Gross, David L. Harame
    Demonstration of a SiGe RF LNA Design Using IBM Design Kits in 0.18um SiGe BiCMOS Technology. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:22-27 [Conf]
  12. Yingmin Li, Dharmesh Parikh, Yan Zhang, Karthik Sankaranarayanan, Mircea R. Stan, Kevin Skadron
    State-Preserving vs. Non-State-Preserving Leakage Control in Caches. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:22-29 [Conf]
  13. Peter H. Saul
    Low Power Analogue 90 Degree Phase Shifter. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:28-33 [Conf]
  14. Markus Wedler, Dominik Stoffel, Wolfgang Kunz
    Arithmetic Reasoning in DPLL-Based SAT Solving. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:30-35 [Conf]
  15. Pavel Horsky
    A 16 Bit + Sign Monotonic Precise Current DAC for Sensor Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:34-38 [Conf]
  16. Jason Baumgartner, Andreas Kuehlmann
    Enhanced Diameter Bounding via Structural. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:36-41 [Conf]
  17. Sotiris Bantas, Yorgos Koutsoyannopoulos, Apostolos Liapis
    An Inductance Modeling Flow Seamlessly Integrated in the RF IC Design Chain. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:39-45 [Conf]
  18. Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Chih-Chan Lin
    Improved Symoblic Simulation by Dynamic Funtional Space Partitioning. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:42-49 [Conf]
  19. Andreas Wortmann, Sven Simon, Matthias Müller
    A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:46-51 [Conf]
  20. Saravanan Padmanaban, Spyros Tragoudas
    Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:50-55 [Conf]
  21. Alex Panato, Sandro V. Silva, Flávio Rech Wagner, Marcelo O. Johann, Ricardo Reis, Sergio Bampi
    Design of Very Deep Pipelined Multipliers for FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:52-57 [Conf]
  22. Irith Pomeranz, Sudhakar M. Reddy
    Level of Similarity: A Metric for Fault Collapsing. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:56-61 [Conf]
  23. Pierre G. Paulin, Chuck Pilkington, Essaid Bensoudane, Michel Langevin, Damien Lyonnard
    Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:58-63 [Conf]
  24. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
    Design of Routing-Constrained Low Power Scan Chains. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:62-67 [Conf]
  25. A. P. Niranjan, Paul C. Wiscombe
    Islands of Synchronicity, a Design Methodology for SoC Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:64-69 [Conf]
  26. Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, Bharath Seshadri
    Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:68-75 [Conf]
  27. Luigi Dadda, Marco Macchetti, Jeff Owen
    The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512). [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:70-75 [Conf]
  28. Chang Hong Lin, Yuan Xie, Wayne Wolf
    LZW-Based Code Compression for VLIW Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:76-81 [Conf]
  29. Angelo Nagari, Germano Nicollini
    A 2.7V 350muW 11-b Algorithmic Analog-to-Digital Converter with Single-Ended Multiplexed Inputs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:76-81 [Conf]
  30. R. Le Moigne, Olivier Pasquier, Jean Paul Calvez
    A Generic RTOS Model for Real-time Systems Simulation with SystemC. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:82-87 [Conf]
  31. Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
    Digital Background Gain Error Correction in Pipeline ADCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:82-87 [Conf]
  32. Mauro Cocco, John Dielissen, Marc J. M. Heijligers, Andries Hekstra, Jos Huisken
    A Scalable Architecture for LDPC Decodin. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:88-95 [Conf]
  33. Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Digital Ground Bounce Reduction by Phase Modulation of the Clock. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:88-93 [Conf]
  34. Francesco Corsi, Cristoforo Marzocca, Gianvito Matarrese, Andrea Baschirotto, Stefano D'Amico
    Pseudo-Random Sequence Based Tuning System for Continuous-Time Filters. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:94-101 [Conf]
  35. Stephen Schmitt, Wolfgang Rosenstiel
    Verification of a Microcontroller IP Core for System-on-a-Chip Designs Using Low-Cost Prototyping Environments. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:96-101 [Conf]
  36. Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    A Crosstalk Aware Interconnect with Variable Cycle Transmission. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:102-107 [Conf]
  37. Alexander Krupp, Wolfgang Mueller, Ian Oliver
    Formal Refinement and Model Checking of an Echo Cancellation Unit. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:102-107 [Conf]
  38. Nattawut Thepayasuwan, Alex Doboli
    Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:108-113 [Conf]
  39. Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, Steven Oostdijk
    Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:108-113 [Conf]
  40. Tobias Thiel
    Have I Really Met Timing? - Validating PrimeTime Timing Reports with Spice. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:114-119 [Conf]
  41. Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alexandru Nicolau
    Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:114-121 [Conf]
  42. Vlado Vorisek, Thomas Koch, Hermann Fischer
    At-Speed Testing of SOC ICs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:120-125 [Conf]
  43. Donatella Sciuto, Grant Martin, Wolfgang Rosenstiel, Stuart Swan, Frank Ghenassia, Peter Flake, Johny Srouji
    SystemC and SystemVerilog: Where do They Fit? Where are They Going? [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:122-129 [Conf]
  44. Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin
    Utilizing Formal Assertions for System Design of Network Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:126-133 [Conf]
  45. Siu-Kei Wong, Chi-Ying Tsui
    Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:130-135 [Conf]
  46. Juan C. Diaz, Marta Saburit
    Clock Management in a Gigabit Ethernet Physical Layer Transceiver Circuit. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:134-139 [Conf]
  47. Zhiyuan Ren, Bruce H. Krogh, Radu Marculescu
    Hierarchical Adaptive Dynamic Power Management. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:136-141 [Conf]
  48. Richard Auletta
    Expert System Perimeter Block Placement Floorplanning. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:140-143 [Conf]
  49. Chuanjun Zhang, Frank Vahid, Roman L. Lysecky
    A Self-Tuning Cache Architecture for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:142-147 [Conf]
  50. Ibrahim M. Elfadel, Alina Deutsch, Gerard V. Kopcsay, Bradley Rubin, H. Smith
    A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:144-149 [Conf]
  51. Jie S. Hu, Narayanan Vijaykrishnan, Soontae Kim, Mahmut T. Kandemir, Mary Jane Irwin
    Scheduling Reusable Instructions for Power Reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:148-155 [Conf]
  52. Jesús Ruiz-Amaya, Josep Lluís de la Rosa, F. Medeiro, Francisco V. Fernández, Rocio del Río, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez
    MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time [Sigma, Delta] Modulators. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:150-155 [Conf]
  53. Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl
    RTL Processor Synthesis for Architecture Exploration and Implementation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:156-160 [Conf]
  54. Per Bjesse, James H. Kukula
    Using Counter Example Guided Abstraction Refinement to Find Complex Bugs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:156-161 [Conf]
  55. Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng
    Pattern Selection for Testing of Deep Sub-Micron Timing Defects. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:160- [Conf]
  56. Ankush Varma, Shuvra S. Bhattacharyya
    Java-through-C Compilation: An Enabling Technology for Java in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:161-167 [Conf]
  57. Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey
    Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:162-167 [Conf]
  58. Franco Fummi, Stefano Martini, Giovanni Perbellini, Massimo Poncino, Fabio Ricciato, Maura Turolla
    Heterogeneous Co-Simulation of Networked Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:168-173 [Conf]
  59. Panagiotis Manolios, Sudarshan K. Srinivasan
    Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:168-175 [Conf]
  60. Marcello Coppola, Stephane Curaba, Miltos D. Grammatikakis, Giuseppe Maruccia, Francesco Papariello
    OCCN: A Network-On-Chip Modeling and Simulation Framework. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:174-179 [Conf]
  61. José M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João C. Teixeira
    A Probabilistic Method for the Computation of Testability of RTL Constructs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:176-181 [Conf]
  62. Francesco Bruschi, Massimo Bombana
    A Design Methodology for the Exploitation of High Level Communication Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:180-185 [Conf]
  63. Prabhat Mishra, Nikil Dutt
    Graph-Based Functional Test Program Generation for Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:182-187 [Conf]
  64. Ioannis Papaefstathiou, George Kornaros, Nicholaos Zervos
    Software Processing Performance in Network Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:186-191 [Conf]
  65. O. Goloubeva, Matteo Sonza Reorda, Massimo Violante
    Automatic Generation of Validation Stimuli for Application-Specific Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:188-193 [Conf]
  66. Friedbert Berens, Gerd Kreiselmaier, Norbert Wehn
    Channel Decoder Architecture for 3G Mobile Wireless Terminals. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:192-197 [Conf]
  67. Michael Dimopoulos, Panagiotis Linardis
    Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering Techniques. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:194-201 [Conf]
  68. Cesar Albenes Zeferino, Márcio Eduardo Kreutz, Altamiro Amadeu Susin
    RASoC: A Router Soft-Core for Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:198-205 [Conf]
  69. Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil Dutt
    Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:202-207 [Conf]
  70. Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese
    Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:206-211 [Conf]
  71. Ann Gordon-Ross, Frank Vahid, Nikil Dutt
    Automatic Tuning of Two-Level Caches to Embedded Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:208-213 [Conf]
  72. Hala A. Farouk, Magdy Saeb
    Design and Implementation of a Secret Key Steganographic Micro-Architecture Employing FPGA. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:212-217 [Conf]
  73. Chuanjun Zhang, Jun Yang, Frank Vahid
    Low Static-Power Frequent-Value Data Caches. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:214-219 [Conf]
  74. Daniel Ferrer, Ramiro González, Roberto Fleitas, Julio Pérez Acle, Rafael Canetti
    NeuroFPGA - Implementing Artificial Neural Networks on Programmable Logic Devices. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:218-223 [Conf]
  75. Chuanjun Zhang, Frank Vahid
    Using a Victim Buffer in an Application-Specific Memory Hierarchy. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:220-227 [Conf]
  76. Roger Endrigo Carvalho Porto, Luciano Volcan Agostini
    Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:224-229 [Conf]
  77. Marc Renaudin, G. Fraidy Bouesse, Ph. Proust, J. P. Tual, Laurent Sourgen, Fabien Germain
    High Security Smartcards. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:228-233 [Conf]
  78. Marc Quax, Jos Huisken, Jef L. van Meerbergen
    A Scalable Implementation of a Reconfigurable WCDMA Rake Receiver. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:230-235 [Conf]
  79. Jingcao Hu, Radu Marculescu
    Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time Constraints. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:234-239 [Conf]
  80. W. W. S. Chu, R. G. Dimond, S. Perrott, S. P. Seng, W. Luk
    Customisable EPIC Processor: Architecture and Tools. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:236-241 [Conf]
  81. Tom W. Chen, Justin Gregg
    A Low Cost Individual-Well Adaptive Body Bias (IWABB) Scheme for Leakage Power Reduction and Performance Enhancement in the Presence of Intra-Die Variations. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:240-245 [Conf]
  82. Marcos R. Boschetti, Ivan Saraiva Silva, Sergio Bampi
    A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:242-247 [Conf]
  83. Kris Tiri, Ingrid Verbauwhede
    A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:246-251 [Conf]
  84. Djones Lettnin, Axel G. Braun, Martin Bogdan, Joachim Gerlach, Wolfgang Rosenstiel
    Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:248-255 [Conf]
  85. Wei-Chung Cheng, Yu Hou, Massoud Pedram
    Power Minimization in a Backlit TFT-LCD Display by Concurrent Brightness and Contrast Scaling. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:252-259 [Conf]
  86. Sara Blanc, J. Gracia, Pedro J. Gil
    Experiences during the Experimental Validation of the Time-Triggered Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:256-261 [Conf]
  87. Sean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee
    Managing Don't Cares in Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:260-265 [Conf]
  88. Thorsten Schubert, Jürgen Hanisch, Joachim Gerlach, Jens-E. Appell, Wolfgang Nebel
    Evaluation of a Refinement-Driven SystemC'-Based Design Flow. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:262-267 [Conf]
  89. Miroslav N. Velev
    Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of Microprocessors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:266-271 [Conf]
  90. N. Bannow, K. Haug
    Evaluation of an Object-Oriented Hardware Design Methodology for Automotive Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:268-273 [Conf]
  91. Bin Li, Michael S. Hsiao, Shuo Sheng
    A Novel SAT All-Solutions Solver for Efficient Preimage Computation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:272-279 [Conf]
  92. W. J. Bainbridge, Luis A. Plana, Stephen B. Furber
    The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:274-279 [Conf]
  93. Beibei Ren, Anru Wang, Joyopriya Bakshi, Kai Liu, Wei Li, Wayne Wei-Ming Dai
    A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:280-285 [Conf]
  94. Ganesh Srinivasan, Soumendu Bhattacharya, Sasikumar Cherubal, Abhijit Chatterjee
    Efficient Test Strategy for TDMA Power Amplifiers Using Transient Current Measurements: Uses and Benefit. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:280-285 [Conf]
  95. Chee-Kian Ong, Dongwoo Hong, Kwang-Ting Cheng, Li-C. Wang
    Random Jitter Extraction Technique in a Multi-Gigahertz Signal. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:286-291 [Conf]
  96. Jay Abraham, Guruprasad Rao
    Qualification and Integration of Complex I/O in SoC Design Flows. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:286-293 [Conf]
  97. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Low Cost Analog Testing of RF Signal Paths. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:292-297 [Conf]
  98. Lieven Hollevoet, Andy Dewilde, Kristof Denolf, Francky Catthoor, Filip Louagie
    A Power Optimized Display Memory Organization for Handheld User Terminal. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:294-299 [Conf]
  99. Diego Vázquez, Gildas Leger, Gloria Huertas, Adoración Rueda, José L. Huertas
    A Method for Parameter Extraction of Analog Sine-Wave Signals for Mixed-Signal Built-In-Self-Test Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:298-305 [Conf]
  100. Ulrich Neffe, Klaus Rothbart, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger
    Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:300-305 [Conf]
  101. Sambuddhi Hettiaratchi, Peter Y. K. Cheung
    A Novel Implementation of Tile-Based Address Mapping. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:306-311 [Conf]
  102. Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto
    Analysis and Modeling of Energy Reducing Source Code Transformations. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:306-311 [Conf]
  103. Francesco Menichelli, Mauro Olivieri, Luca Benini, Monica Donno, Labros Bisdounis
    A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:312-317 [Conf]
  104. Zhong Wang, Xiaobo Sharon Hu
    Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:312-317 [Conf]
  105. Andrea Bona, Vittorio Zaccaria, Roberto Zafalon
    System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:318-323 [Conf]
  106. Radoslaw Szymanek, Francky Catthoor, Krzysztof Kuchcinski
    Time-Energy Design Space Exploration for Multi-Layer Memory Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:318-323 [Conf]
  107. Krisztián Flautner, David Flynn, David Roberts, Dipesh I. Patel
    IEM926: An Energy Efficient SoC with Dynamic Voltage Scaling. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:324-329 [Conf]
  108. Arathi Ramani, Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
    Breaking Instance-Independent Symmetries in Exact Graph Coloring. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:324-331 [Conf]
  109. Kathy Werner
    Can IP Quality be Objectively Measured? [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:330-331 [Conf]
  110. Francky Catthoor, Andrea Cuomo, Grant Martin, Patrick Groeneveld, Rudy Lauwereins, Karen Maex, Patrick van de Steeg, Ron Wilson
    How Can System-Level Design Solve the Interconnect Technology Scaling Problem? [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:332-339 [Conf]
  111. Stephen Bailey, Erich Marschner, Jayaram Bhasker, Jim Lewis, Peter J. Ashenden
    Improving Design and Verification Productivity with VHDL-200x. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:332-335 [Conf]
  112. Pierluigi Daglio, David Iezzi, Danilo Rimondi, Carlo Roma, Salvatore Santapa
    Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:336-337 [Conf]
  113. B. Hecker, M. Chavassieux, M. Laflutte, E. Beguin, L. Lagasse, Jean Oudinot
    VHDL-AMS Library Development for Pacemaker Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:338-341 [Conf]
  114. Todor Stefanov, Claudiu Zissulescu, Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
    System Design Using Kahn Process Networks: The Compaan/Laura Approach. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:340-345 [Conf]
  115. Franco Fummi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino
    Modeling and Analysis of Heterogeneous Industrial Networks Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:342-344 [Conf]
  116. Douglas Densmore, Sanjay Rekhi, Alberto L. Sangiovanni-Vincentelli
    Microarchitecture Development via Metropolis Successive Platform Refinement. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:346-351 [Conf]
  117. Chulho Shin, Young-Taek Kim, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo
    Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:352-357 [Conf]
  118. Jean-Yves Brunel, Marco Di Natale, Alberto Ferrari, Paolo Giusto, Luciano Lavagno
    SoftContract: an Assertion-Based Software Development Process that Enables Design-by-Contract. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:358-363 [Conf]
  119. D. Quinn, Bruno Lavigueur, Guy Bois, El Mostapha Aboulhamid
    A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:364-371 [Conf]
  120. Christoph Grimm, Wilhelm Heupke, Klaus Waldschmidt
    Refinement of Mixed-Signal Systems with Affine Arithmetic. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:372-377 [Conf]
  121. Hector Posadas, F. Herrera, Pablo Sánchez, Eugenio Villar, Francisco Blasco
    System-Level Performance Analysis in SystemC. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:378-383 [Conf]
  122. Mohammad Reza Mousavi, Paul Le Guernic, Jean-Pierre Talpin, Sandeep K. Shukla, Twan Basten
    Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:384-389 [Conf]
  123. Vijay D'Silva, S. Ramesh, Arcot Sowmya
    Synchronous Protocol Automata: A Framework for Modelling and Verification of SoC Communication Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:390-395 [Conf]
  124. Tiberiu Seceleanu, Tomi Westerlund
    Aspects of Formal and Graphical Design of a Bus System. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:396-403 [Conf]
  125. Ozgur Sinanoglu, Alex Orailoglu
    Scan Power Minimization through Stimulus and Response Transformations. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:404-409 [Conf]
  126. Matthew W. Heath, Wayne P. Burleson, Ian G. Harris
    Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?s. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:410-415 [Conf]
  127. Qiang Xu, Nicola Nicolici
    Wrapper Design for Testing IP Cores with Multiple Clock Domains. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:416-421 [Conf]
  128. Anuja Sehgal, Krishnendu Chakrabarty
    Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:422-427 [Conf]
  129. Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre
    An Arithmetic Structure for Test Data Horizontal Compression. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:428-435 [Conf]
  130. Ewout Martens, Georges G. E. Gielen
    A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:436-441 [Conf]
  131. Lutz Näthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke
    Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:442-447 [Conf]
  132. Tholom Kiely, Georges G. E. Gielen
    Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:448-453 [Conf]
  133. Gerd Vandersteen, Rik Pintelon, Dimitri Linten, Stéphane Donnay
    Extended Subspace Identification of Improper Linear Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:454-459 [Conf]
  134. Xiaoling Huang, H. Alan Mantooth
    Identification and Modeling of Nonlinear Dynamic Behavior in Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:460-467 [Conf]
  135. Aneesh Koorapaty, V. Kheterpal, Padmini Gopalakrishnan, M. Fu, Lawrence T. Pileggi
    Exploring Logic Block Granularity for Regular Fabrics. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:468-473 [Conf]
  136. Nikhil Bansal, Sumit Gupta, Nikil Dutt, Alexandru Nicolau, Rajesh Gupta
    Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:474-479 [Conf]
  137. Roman L. Lysecky, Frank Vahid
    A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:480-485 [Conf]
  138. Guilin Chen, Mahmut T. Kandemir, Ugur Sezer
    Configuration-Sensitive Process Scheduling for FPGA-Based Computing Platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:486-493 [Conf]
  139. Dongwoo Lee, Harmander Deogun, David Blaauw, Dennis Sylvester
    Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:494-499 [Conf]
  140. Pietro Babighian, Luca Benini, Enrico Macii
    A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:500-505 [Conf]
  141. Mahmut T. Kandemir
    Impact of Data Transformations on Memory Bank Locality. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:506-511 [Conf]
  142. Claudia Kretzschmar, André K. Nieuwland, Dietmar Müller
    Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:512-517 [Conf]
  143. Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi
    Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:518-525 [Conf]
  144. Le Cai, Yung-Hsiang Lu
    Dynamic Power Management Using Data Buffers. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:526-531 [Conf]
  145. David Atienza, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris
    Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:532-537 [Conf]
  146. Hye-On Jang, Minsoo Kang, Myeong-jin Lee, Kwanyeob Chae, Kookpyo Lee, Kyuhyun Shim
    High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:538-543 [Conf]
  147. Guido Post, P. K. Venkataraghavan, Tapan Ray, D. R. Seetharaman
    A SystemC-Based Verification Methodology for Complex Wireless Software IP. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:544-551 [Conf]
  148. Daniel Gracia Pérez, Gilles Mouchard, Olivier Temam
    A New Optimized Implemention of the SystemC Engine Using Acyclic Scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:552-557 [Conf]
  149. Avi Ziv
    Stimuli Generation with Late Binding of Values. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:558-563 [Conf]
  150. Franco Fummi, Stefano Martini, Giovanni Perbellini, Massimo Poncino
    Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:564-569 [Conf]
  151. Soumitra Bose, Amit Nandi
    Extraction of Schematic Array Models for Memory Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:570-577 [Conf]
  152. Antonis M. Paschalis, Dimitris Gizopoulos
    Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:578-583 [Conf]
  153. M. Bellato, Paolo Bernardi, D. Bortolato, A. Candelori, M. Ceschia, A. Paccagnella, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, P. Zambolin
    Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:584-589 [Conf]
  154. Régis Leveugle, Abdelaziz Ammari
    Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:590-595 [Conf]
  155. Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris
    On Concurrent Error Detection with Bounded Latency in FSMs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:596-603 [Conf]
  156. Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen
    Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:604-609 [Conf]
  157. Rajeev Murgai, Subodh M. Reddy, Takashi Miyoshi, Takeshi Horie, Mehdi Baradaran Tahoori
    Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:610-615 [Conf]
  158. Thomas Brandtner, Robert Weigel
    SubCALM: A Program for Hierarchical Substrate Coupling Simulation on Floorplan Level. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:616-621 [Conf]
  159. Yong Zhan, Sachin S. Sapatnekar
    Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:622-629 [Conf]
  160. Abhijit K. Deb, Axel Jantsch, Johnny Öberg
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    DATE, 2004, pp:630-635 [Conf]
  161. Joseph Zambreno, Alok N. Choudhary, Rahul Simha, Bhagirath Narahari
    Flexible Software Protection Using Hardware/Software Codesign Techniques. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:636-641 [Conf]
  162. Patrick Schaumont, Ingrid Verbauwhede
    Interactive Cosimulation with Partial Evaluation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:642-647 [Conf]
  163. Axel Siebenborn, Oliver Bringmann, Wolfgang Rosenstiel
    Communication Analysis for System-On-Chip Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:648-655 [Conf]
  164. Christian Piguet, Jacques Gautier, Christoph Heer, Ian O'Connor, Ulf Schlichtmann
    Extremely Low-Power Logic. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:656-663 [Conf]
  165. Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
    Decomposition of Instruction Decoder for Low Power Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:664-665 [Conf]
  166. Johann Laurent, Nathalie Julien, Eric Senn, Eric Martin
    Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:666-667 [Conf]
  167. Prasenjit Basu, Sayantan Das, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix
    Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent? [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:668-669 [Conf]
  168. Young-Su Kwon, Chong-Min Kyung
    Functional Coverage Metric Generation from Temporal Event Relation Graph. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:670-671 [Conf]
  169. Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards
    Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:672-673 [Conf]
  170. Hassan Aboushady, L. de Lamarre, N. Beilleau, Marie-Minerve Louërat
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    DATE, 2004, pp:674-675 [Conf]
  171. Fernando De Bernardinis, Alberto L. Sangiovanni-Vincentelli
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    DATE, 2004, pp:676-677 [Conf]
  172. Mohammad Taherzadeh-Sani, Reza Lotfi, Omid Shoaei
    Systematic Design for Optimization of High-Resolution Pipelined ADCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:678-679 [Conf]
  173. José C. García, Juan A. Montiel-Nelson, J. Sosa, Héctor Navarro
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    DATE, 2004, pp:680-681 [Conf]
  174. Ben I. Hounsell, Richard Taylor
    Co-Processor Synthesis: A New Methodology for Embedded Software Acceleration. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:682-683 [Conf]
  175. María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
    Behavioural Bitwise Scheduling Based on Computational Effort Balancing. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:684-685 [Conf]
  176. Andrea Del Re, Alberto Nannarelli, Marco Re
    A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:686-687 [Conf]
  177. Lipeng Cao
    On Transfer Function and Power Consumption Transient Response. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:688-689 [Conf]
  178. Tarvo Raudvere, Ashish Kumar Singh, Ingo Sander, Axel Jantsch
    Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:690-691 [Conf]
  179. Li-C. Wang
    Regression Simulation: Applying Path-Based Learning In Delay Test and Post-Silicon Validation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:692-695 [Conf]
  180. Ali Iranli, Kihwan Choi, Massoud Pedram
    A Game Theoretic Approach to Low Energy Wireless Video Streaming. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:696-697 [Conf]
  181. Luca Benini, Alessandro Ivaldi, Alberto Macii, Enrico Macii
    Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:698-699 [Conf]
  182. Kimish Patel, Enrico Macii, Massimo Poncino
    Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:700-701 [Conf]
  183. Mladen Nikitovic, Mats Brorsson
    A Low Power Strategy for Future Mobile Terminals. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:702-703 [Conf]
  184. Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
    Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:704-705 [Conf]
  185. Luís Rolíndez, Salvador Mir, Guillaume Prenat, Ahcène Bounceur
    A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:706-707 [Conf]
  186. Gildas Leger, Adoración Rueda
    A Digital Test for First-Order [Sigma-Delta] Modulators. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:708-709 [Conf]
  187. James Chin, Mehrdad Nourani
    SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:710-711 [Conf]
  188. Mounir Benabdenbi, Alain Greiner, François Pêcheux, Emmanuel Viaud, Matthieu Tuna
    STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:712-713 [Conf]
  189. Cecilia Metra, T. M. Mak, Martin Omaña
    Are Our Design for Testability Features Fault Secure? [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:714-715 [Conf]
  190. Francis G. Wolff, Christos A. Papachristou, David R. McIntyre
    Test Compression and Hardware Decompression for Scan-Based SoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:716-717 [Conf]
  191. Ashish Srivastava, Dennis Sylvester, David Blaauw
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    DATE, 2004, pp:718-719 [Conf]
  192. Pietro Babighian, Luca Benini, Enrico Macii
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    DATE, 2004, pp:720-723 [Conf]
  193. Frank P. Burns, Delong Shang, Albert Koelmans, Alexandre Yakovlev
    An Asynchronous Synthesis Toolset Using Verilog. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:724-725 [Conf]
  194. Gero Dittmann
    Organizing Libraries of DFG Patterns. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:726-727 [Conf]
  195. Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Cotofana, Jos T. J. van Eijndhoven
    Compositional Memory Systems for Data Intensive Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:728-729 [Conf]
  196. Juha Alakarhu, Jarkko Niittylahti
    Scalar Metric for Temporal Locality and Estimation of Cache Performance. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:730-731 [Conf]
  197. James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois
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    DATE, 2004, pp:732-733 [Conf]
  198. Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo
    Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:734-735 [Conf]
  199. Peter Green, Salah Essa
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    DATE, 2004, pp:736-737 [Conf]
  200. Matthieu Briere, L. Carrel, T. Michalke, Fabien Mieyeville, Ian O'Connor, Frédéric Gaffiot
    Design and Behavioral Modeling Tools for Optical Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:738-739 [Conf]
  201. Sheldon X.-D. Tan, Zhenyu Qi, Hang Li
    Hierarchical Modeling and Simulation of Large Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:740-741 [Conf]
  202. Peter R. Wilson, J. Neil Ross, Andrew D. Brown, Tom J. Kazmierski, Jerzy Baranowski
    Efficient Mixed-Domain Behavioural Modeling of Ferromagnetic Hysteresis Implemented in VHDL-AMS. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:742-743 [Conf]
  203. Manish Handa, Ranga Vemuri
    A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:744-745 [Conf]
  204. Alex Fit-Florea, Miroslav Halas, Fatih Kocan
    Enhancing Reliability of Operational Interconnections in FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:746-747 [Conf]
  205. Miljan Vuletic, Ludovic Righetti, Laura Pozzi, Paolo Ienne
    Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:748- [Conf]
  206. Mirko Loghi, Federico Angiolini, Davide Bertozzi, Luca Benini, Roberto Zafalon
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    DATE, 2004, pp:752-757 [Conf]
  207. Matthias Grünewald, Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert
    A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:758-763 [Conf]
  208. Santiago González Pestana, Edwin Rijpkema, Andrei Radulescu, Kees G. W. Goossens, Om Prakash Gangwal
    Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:764-769 [Conf]
  209. Jiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar, Tiehan Lv
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    DATE, 2004, pp:770-777 [Conf]
  210. Chunjie Duan, Sunil P. Khatri
    Exploiting Crosstalk to Speed up On-Chip Buse. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:778-783 [Conf]
  211. Alexey Glebov, Sergey Gavrilov, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, Murat R. Becer
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    DATE, 2004, pp:784-789 [Conf]
  212. Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang
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    DATE, 2004, pp:790-795 [Conf]
  213. Alessandra Nardi, Alberto L. Sangiovanni-Vincentelli
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    DATE, 2004, pp:796-803 [Conf]
  214. M. A. Abas, Gordon Russell, D. J. Kinniment
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    DATE, 2004, pp:804-809 [Conf]
  215. Harald P. E. Vranken, Ferry Syafei Sapei, Hans-Joachim Wunderlich
    Impact of Test Point Insertion on Silicon Area and Timing during Layout. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:810-815 [Conf]
  216. Hani Rizk, Christos A. Papachristou, Francis G. Wolff
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    DATE, 2004, pp:816-823 [Conf]
  217. Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury
    Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:824-829 [Conf]
  218. Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Ping Chen
    Thermal and Power Integrity Based Power/Ground Networks Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:830-835 [Conf]
  219. Hai Lan, Robert W. Dutton
    Synthesized Compact Models (SCM) of Substrate Noise Coupling Analysis and Synthesis in Mixed-Signal ICs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:836-843 [Conf]
  220. Pierre G. Paulin
    DATE Panel: Chips of the Future: Soft, Crunchy or Hard? [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:844-851 [Conf]
  221. Ismail Kadayif, Mahmut T. Kandemir
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    DATE, 2004, pp:852-857 [Conf]
  222. Andrea Acquaviva, Emanuele Lattanzi, Alessandro Bogliolo
    Power-Aware Network Swapping for Wireless Palmtop PCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:858-863 [Conf]
  223. Nikolaos D. Liveris, Prithviraj Banerjee
    Power Aware Interface Synthesis for Bus-Based SoC Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:864-869 [Conf]
  224. Alex Branover, Rakefet Kol, Ran Ginosar
    Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:870-877 [Conf]
  225. Andrei Radulescu, John Dielissen, Kees G. W. Goossens, Edwin Rijpkema, Paul Wielage
    An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:878-883 [Conf]
  226. Antoine Jalabert, Srinivasan Murali, Luca Benini, Giovanni De Micheli
    ×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:884-889 [Conf]
  227. Mikael Millberg, Erland Nilsson, Rikard Thid, Axel Jantsch
    Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:890-895 [Conf]
  228. Srinivasan Murali, Giovanni De Micheli
    Bandwidth-Constrained Mapping of Cores onto NoC Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:896-903 [Conf]
  229. Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha
    Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:904-909 [Conf]
  230. Shrirang K. Karandikar, Sachin S. Sapatnekar
    Fast Comparisons of Circuit Implementations. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:910-915 [Conf]
  231. Anurag Tiwari, Karen A. Tomko
    Saving Power by Mapping Finite-State Machines into Embedded Memory Blocks in FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:916-921 [Conf]
  232. A. Manoj Kumar, Jayaram Bobba, V. Kamakoti
    MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:922-929 [Conf]
  233. Janusz Rajski, Kan Thapar
    Nanometer Design: What are the Requirements for Manufacturing Test? [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:930-937 [Conf]
  234. Joel R. Phillips, Luis Miguel Silveira
    Poor Man's TBR: A Simple Model Reduction Scheme. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:938-943 [Conf]
  235. Peter Feldmann
    Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:944-947 [Conf]
  236. Rong Jiang, Charlie Chung-Ping Chen
    SCORE: SPICE COmpatible Reluctance Extraction. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:948-953 [Conf]
  237. José Luis Rosselló, Jaume Segura
    A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:954-961 [Conf]
  238. Sridhar Dasika, Sarma B. K. Vrudhula, Kaviraj Chopra, R. Srinivasan
    A Framework for Battery-Aware Sensor Management. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:962-967 [Conf]
  239. Phillip Stanley-Marbell, Diana Marculescu
    Local Decisions and Triggering Mechanisms for Adaptive Fault-Tolerance. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:968-973 [Conf]
  240. Pallav Gupta, Niraj K. Jha
    An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:974-979 [Conf]
  241. Vivek V. Shende, Igor L. Markov, Stephen S. Bullock
    Smaller Two-Qubit Circuits for Quantum Communication and Computation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:980-987 [Conf]
  242. Ingrid Verbauwhede, Patrick Schaumont, Christian Piguet, Bart Kienhuis
    Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:988-995 [Conf]
  243. Andreas Vörg, Martin Radetzki, Wolfgang Rosenstiel
    Measurement of IP Qualification Costs and Benefits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:996-1001 [Conf]
  244. Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai
    Architecture-Level Performance Estimation for IP-Based Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1002-1007 [Conf]
  245. Montek Singh, Michael Theobald
    Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1008-1013 [Conf]
  246. M. Bolado, Hector Posadas, J. Castillo, P. Huerta, Pablo Sánchez, C. Sánchez, H. Fouren, Francisco Blasco
    Platform Based on Open-Source Cores for Industrial Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1014-1019 [Conf]
  247. Newton Cheung, Sri Parameswaran, Jörg Henkel, Jeremy Chan
    MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1020-1027 [Conf]
  248. Paul Pop, Petru Eles, Zebo Peng, Viacheslav Izosimov, Magnus Hellring, Olof Bridal
    Design Optimization of Multi-Cluster Embedded Systems for Real-Time Application. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1027-1033 [Conf]
  249. Yudong Tan, Vincent John Mooney III
    Timing Analysis for Preemptive Multi-Tasking Real-Time Systems with Caches. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1034-1039 [Conf]
  250. Alexander Maxiaguine, Simon Künzli, Lothar Thiele
    Workload Characterization Model for Tasks with Variable Execution Demand. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1040-1045 [Conf]
  251. Marek Jersak, Rafik Henia, Rolf Ernst
    Context-Aware Performance Analysis for Efficient Embedded System Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1046-1051 [Conf]
  252. Stacey Shogan, Bruce R. Childers
    Compact Binaries with Code Compression in a Software Dynamic Translator. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1052-1059 [Conf]
  253. Jennifer Dworak, Brad Cobb, James Wingfield, M. Ray Mercer
    Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1066-1071 [Conf]
  254. Yu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, Yu-Ting Hung
    Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1072-1077 [Conf]
  255. Chandra Tirumurti, Sandip Kundu, Susmita Sur-Kolay, Yi-Shing Chang
    A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1078-1083 [Conf]
  256. Zaid Al-Ars, A. J. van de Goor
    Soft Faults and the Importance of Stresses in Memory Testing. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1084-1091 [Conf]
  257. Chuan Lin, Hai Zhou
    Wire Retiming for System-on-Chip by Fixpoint Computation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1092-1097 [Conf]
  258. Andrew B. Kahng, Igor L. Markov, Sherief Reda
    Boosting: Min-Cut Placement with Improved Signal Delay. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1098-1103 [Conf]
  259. Liang Deng, Martin D. F. Wong
    Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1104-1109 [Conf]
  260. Suvodeep Gupta, Srinivas Katkoori
    A Fast Word-Level Statistical Estimator of Intra-Bus Crosstalk. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1110-1115 [Conf]
  261. Jinjun Xiong, Lei He
    Full-Chip Multilevel Routing for Power and Signal Integrity. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1116-1123 [Conf]
  262. Hans Van Antwerpen, Nikil D. Dutt, Rajesh K. Gupta, Shivajit Mohapatra, Cristiano Pereira, Nalini Venkatasubramanian, Ralph von Vignau
    Energy-Aware System Design for Wireless Multimedia. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1124-1131 [Conf]
  263. Mohamed-Anouar Dziri, Wander O. Cesário, Flávio Rech Wagner, Ahmed Amine Jerraya
    Unified Component Integration Flow for Multi-Processor SoC Design and Validation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1132-1137 [Conf]
  264. Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi
    An Interconnect Channel Design Methodology for High Performance Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1138-1143 [Conf]
  265. Alex Bobrek, Joshua J. Pieper, Jeffrey E. Nelson, JoAnn M. Paul, Donald E. Thomas
    Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1144-1149 [Conf]
  266. Taeweon Suh, Douglas M. Blough, Hsien-Hsin S. Lee
    Supporting Cache Coherence in Heterogeneous Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1150-1157 [Conf]
  267. Ismail Kadayif, Mahmut T. Kandemir, Ibrahim Kolcu
    Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1158-1163 [Conf]
  268. Claudio Pinello, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
    Fault-Tolerant Deployment of Embedded Software for Cost-Sensitive Real-Time Feedback-Control Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1164-1169 [Conf]
  269. Ying Zhang, Krishnendu Chakrabarty
    Task Feasibility Analysis and Dynamic Voltage Scaling in Fault-Tolerant Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1170-1175 [Conf]
  270. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Quasi-Static Scheduling for Real-Time Systems with Hard and Soft Tasks. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1176-1183 [Conf]
  271. Stephen K. Sunter, Adam Osseiran, Adam Cron, Neil Jacobson, Dave Bonnett, Bill Eklow, Carl Barnhart, Ben Bennetts
    Status of IEEE Testability Standards 1149.4, 1532 and 1149.6. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1184-1191 [Conf]
  272. Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska
    Eliminating False Positives in Crosstalk Noise Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1192-1197 [Conf]
  273. Arijit Mondal, P. P. Chakrabarti, Chittaranjan A. Mandal
    A New Approach to Timing Analysis Using Event Propagation and Temporal Logic. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1198-1203 [Conf]
  274. Yi-Lin Hsieh, Tsai-Ming Hsieh
    A New Effective Congestion Model in Floorplan Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1204-1209 [Conf]
  275. Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu
    ULSI Interconnect Length Distribution Model Considering Core Utilization. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1210-1217 [Conf]
  276. Alberto La Rosa, Claudio Passerone, Francesco Gregoretti, Luciano Lavagno
    Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1218-1223 [Conf]
  277. Bingfeng Mei, Serge Vernalde, Diederik Verkest, Rudy Lauwereins
    Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1224-1229 [Conf]
  278. Sami Khawam, Sajid Baloch, Arjun Pai, Imran Ahmed, Nizamettin Aydin, Tughrul Arslan, Fred Westall
    Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1230-1235 [Conf]
  279. Helena Krupnova
    Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and Experience. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1236-1243 [Conf]
  280. Xinping Zhu, Sharad Malik
    Using a Communication Architecture Specification in an Application-Driven Retargetable Prototyping Platform for Multiprocessing. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1244-1249 [Conf]
  281. Nilanjan Banerjee, Praveen Vellanki, Karam S. Chatha
    A Power and Performance Model for Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1250-1255 [Conf]
  282. Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl
    A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1256-1263 [Conf]
  283. Manish Verma, Lars Wehmeyer, Peter Marwedel
    Cache-Aware Scratchpad Allocation Algorithm. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1264-1269 [Conf]
  284. Markus Lorenz, Peter Marwedel
    Phase Coupled Code Generation for DSPs Using a Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1270-1275 [Conf]
  285. Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren
    A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1276-1283 [Conf]
  286. Mohammad H. Tehranipour, Mehrdad Nourani, Krishnendu Chakrabarty
    Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1284-1289 [Conf]
  287. Baris Arslan, Alex Orailoglu
    CircularScan: A Scan Architecture for Test Cost Reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1290-1295 [Conf]
  288. Seongmoon Wang, Xiao Liu, Srimat T. Chakradhar
    Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1296-1301 [Conf]
  289. A. Leininger, Michael Gössel, Peter Muhmenthaler
    Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Code. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1302-1309 [Conf]
  290. Bo Wan, C.-J. Richard Shi
    Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1310-1315 [Conf]
  291. Lihong Feng, Xuan Zeng, Charles Chiang, Dian Zhou, Qiang Fang
    Direct Nonlinear Order Reduction with Variational Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1316-1321 [Conf]
  292. Xin Zhou, Dian Zhou, Jin Liu, Ruiming Li, Xuan Zeng, Charles Chiang
    Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1322-1326 [Conf]
  293. Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
    Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1327-1333 [Conf]
  294. Tom Fitzpatric
    System Verilog for VHDL Users. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1334-1341 [Conf]
  295. Radu Marculescu, Massoud Pedram, Jörg Henkel
    Distributed Multimedia System Design: A Holistic Perspective. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1342-1349 [Conf]
  296. Hassan Sbeyti, Smaïl Niar, Lieven Eeckhout
    Adaptive Prefetching for Multimedia Applications in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1350-1351 [Conf]
  297. Jayaprakash Pisharath, Alok N. Choudhary, Mahmut T. Kandemir
    Data Windows: A Data-Centric Approach for Query Execution in Memory-Resident Databases. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1352-1353 [Conf]
  298. George F. Viamontes, Igor L. Markov, John P. Hayes
    High-Performance QuIDD-Based Simulation of Quantum Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1354-1355 [Conf]
  299. D. K. Reed, Steven P. Levitan, J. Boles, Jose A. Martinez, Donald M. Chiarulli
    An Application of Parallel Discrete Event Simulation Algorithms to Mixed Domain System Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1356-1357 [Conf]
  300. Jing Huang, Mehdi Baradaran Tahoori, Fabrizio Lombardi
    Fault Tolerance of Programmable Switch Blocks. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1358-1359 [Conf]
  301. Egor S. Sogomonyan, Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel
    A New Self-Checking Sum-Bit Duplicated Carry-Select Adder. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1360-1361 [Conf]
  302. Luis Elvira, Ferran Martorell, Xavier Aragonès, José Luis González
    A Macromodelling Methodology for Efficient High-Level Simulation of Substrate Noise Generation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1362-1363 [Conf]
  303. Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri
    Accurate Estimation of Parasitic Capacitances in Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1364-1365 [Conf]
  304. Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha
    GRAAL - A Development Framework for Embedded Graphics Accelerators. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1366-1367 [Conf]
  305. Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Kelvin Lwin, Christos P. Sotiriou
    From Synchronous to Asynchronous: An Automatic Approach. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1368-1369 [Conf]
  306. Oussama Laouamri, Chouki Aktouf
    Enhancing Testability of System on Chips Using Network Management Protocols. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1370-1371 [Conf]
  307. Matheos Lampropoulos, Bashir M. Al-Hashimi, Paul M. Rosinger
    Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1372-1373 [Conf]
  308. Juan L. Aragón, Dan Nicolaescu, Alexander V. Veidenbaum, Ana-Maria Badulescu
    Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1374-1375 [Conf]
  309. André C. Nácul, Tony Givargis
    Dynamic Voltage and Cache Reconfiguration for Low Power. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1376-1379 [Conf]
  310. Maziar Goudarzi, Shaahin Hessabi, Alan Mycroft
    Overhead-Free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1380-1381 [Conf]
  311. Sungjoo Yoo, Mohamed-Wassim Youssef, Aimen Bouchhima, Ahmed Amine Jerraya, Mario Diaz-Nava
    Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1382-1383 [Conf]
  312. Abhinav Agrawal, Niraj K. Jha
    Synthesis of Reversible Logic. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1384-1385 [Conf]
  313. Matthew M. Ziegler, Mircea R. Stan
    A Unified Design Space for Regular Parallel Prefix Adders. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1386-1387 [Conf]
  314. Abusaleh M. Jabir, Dhiraj K. Pradhan
    MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1388-1389 [Conf]
  315. Mario R. Casu, Luca Macchiarulo
    Issues in Implementing Latency Insensitive Protocols. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1390-1391 [Conf]
  316. Tim Schattkowsky, Wolfgang Müller 0003
    Model-Based Specification and Execution of Embedded Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1392-1393 [Conf]
  317. Satnam Singh
    A Demonstration of Co-Design and Co-Verification in a Synchronous Language. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1394-1395 [Conf]
  318. Shukang Zhou, Bruce R. Childers, Naveen Kumar
    Profile Guided Management of Code Partitions for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1396-1399 [Conf]
  319. Rong Jiang, Charlie Chung-Ping Chen
    Realizable Reduction for Electromagnetically Coupled RLMC Interconnects. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1400-1401 [Conf]
  320. Giuseppe S. Garcea, N. P. van der Meijs, Kees-Jan van der Kolk, Ralph H. J. M. Otten
    Statistically Aware Buffer Planning. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1402-1403 [Conf]
  321. S. Bernardini, Jean Michel Portal, P. Masson
    A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1404-1405 [Conf]
  322. Josep Rius Vázquez, José Pineda de Gyvez
    Power Supply Noise Monitor for Signal Integrity Faults. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1406-1407 [Conf]
  323. Mehdi Baradaran Tahoori, Fabrizio Lombardi
    Testing of Quantum Dot Cellular Automata Based Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1408-1409 [Conf]
  324. Jacob R. Minz, Mohit Pathak, Sung Kyu Lim
    Net and Pin Distribution for 3D Package Global Routing. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1410-1411 [Conf]
  325. Markus Olbrich, Erich Barke
    Placement Using a Localization Probability Model (LPM). [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1412- [Conf]
  326. Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost
    CMOS Structures Suitable for Secured Hardware. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1414-1415 [Conf]
  327. Kambiz Rahimi, Seth Bridges, Chris Diorio
    Timing Correction and Optimization with Adaptive Delay Sequential Element. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1416- [Conf]
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