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Conferences in DBLP

Design, Automation, and Test in Europe (date)
2006 (conf/date/2006p)

  1. Rene Penning de Vries
    EDA challenges in the converging application world. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1- [Conf]
  2. Walden C. Rhines
    Sociology of design and EDA. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:2- [Conf]
  3. Martino Ruggiero, Alessio Guerri, Davide Bertozzi, Francesco Poletti, Michela Milano
    Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:3-8 [Conf]
  4. Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
    Efficient link capacity and QoS design for network-on-chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:9-14 [Conf]
  5. Stefano Bertozzi, Andrea Acquaviva, Davide Bertozzi, Antonio Poggiali
    Supporting task migration in multi-processor systems-on-chip: a feasibility study. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:15-20 [Conf]
  6. Xuan Zeng, Lihong Feng, Yangfeng Su, Wei Cai, Dian Zhou, Charles Chiang
    Time domain model order reduction by wavelet collocation method. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:21-26 [Conf]
  7. Quming Zhou, Kai Sun, Kartik Mohanram, Danny C. Sorensen
    Large power grid analysis using domain decomposition. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:27-32 [Conf]
  8. J. Balachandran, Steven Brebels, G. Carchon, T. Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne
    Analysis and modeling of power grid transmission lines. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:33-38 [Conf]
  9. Baohua Wang, Pinaki Mazumder
    A logarithmic full-chip thermal analysis algorithm based on multi-layer Green's function. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:39-44 [Conf]
  10. Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai
    Large scale RLC circuit analysis using RLCG-MNA formulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:45-46 [Conf]
  11. Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff
    Soft delay error analysis in logic circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:47-52 [Conf]
  12. Tsu-Wei Tseng, Jin-Fu Li, Da-Ming Chang
    A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:53-58 [Conf]
  13. Daniele Rossi, Carlo Steiner, Cecilia Metra
    Analysis of the impact of bus implemented EDCs on on-chip SSN. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:59-64 [Conf]
  14. Nektarios Kranitis, A. Merentitis, N. Laoutaris, G. Theodorou, Antonis M. Paschalis, Dimitris Gizopoulos, Constantin Halatsis
    Optimal periodic testing of intermittent faults in embedded pipelined processor applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:65-70 [Conf]
  15. Sobeeh Almukhaizim, Yiorgos Makris
    Berger code-based concurrent error detection in asynchronous burst-mode machines. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:71-72 [Conf]
  16. Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
    Two-phase resonant clocking for ultra-low-power hearing aid applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:73-78 [Conf]
  17. Se-Joong Lee, Kwanho Kim, Hyejung Kim, Namjun Cho, Hoi-Jun Yoo
    A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:79-80 [Conf]
  18. Cristiano Niclass, Maximilian Sergio, Edoardo Charbon
    A single photon avalanche diode array fabricated in deep-submicron CMOS technology. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:81-86 [Conf]
  19. Jon Friedman
    MATLAB/Simulink for automotive systems design. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:87-88 [Conf]
  20. Mirko Conrad, Heiko Dörr
    Model-based development of in-vehicle software. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:89-90 [Conf]
  21. Klaus Lamberg
    Model-based testing of automotive electronics. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:91- [Conf]
  22. John Heighton
    Designing signal processing systems for FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:92- [Conf]
  23. Yves Vanderperren, Wim Dehaene
    From UML/SysML to Matlab/Simulink: current state and future perspectives. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:93- [Conf]
  24. Emmanuel Viaud, François Pêcheux, Alain Greiner
    An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:94-99 [Conf]
  25. Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Damien Lyonnard, Chuck Pilkington
    Exploiting TLM and object introspection for system-level simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:100-105 [Conf]
  26. Ali Habibi, Sofiène Tahar, Amer Samarah, Donglin Li, Otmane Aït Mohamed
    Efficient assertion based verification using TLM. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:106-111 [Conf]
  27. Joseph D'Errico, Wei Qin
    Constructing portable compiled instruction-set simulators: an ADL-driven approach. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:112-117 [Conf]
  28. Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli
    A methodology for mapping multiple use-cases onto networks on chips. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:118-123 [Conf]
  29. Federico Angiolini, Paolo Meloni, Salvatore Carta, Luca Benini, Luigi Raffo
    Contrasting a NoC and a traditional interconnect fabric with layout awareness. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:124-129 [Conf]
  30. Krishnan Srinivasan, Karam S. Chatha
    A low complexity heuristic for design of custom network-on-chip architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:130-135 [Conf]
  31. Thilo Pionteck, Carsten Albrecht, Roman Koch
    A dynamically reconfigurable packet-switched network-on-chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:136-137 [Conf]
  32. Vahid Majidzadeh, Omid Shoaei
    Arbitrary design of high order noise transfer function for a novel class of reduced-sample-rate sigma-delta-pipeline ADCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:138-143 [Conf]
  33. Mohammad Yavari, Omid Shoaei, Ángel Rodríguez-Vázquez
    Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:144-149 [Conf]
  34. Gerd Vandersteen, Stephane Bronckers, Petr Dobrovolný, Yves Rolain
    Systematic stability-analysis method for analog circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:150-155 [Conf]
  35. Hui Zhang, Yang Zhao, Alex Doboli
    ALAMO: an improved alpha-space based methodology for modeling process parameter variations in analog circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:156-161 [Conf]
  36. V. Giannini, Pierluigi Nuzzo, Fernando De Bernardinis, Jan Craninckx, Boris Come, Stefano D'Amico, Andrea Baschirotto
    A synthesis tool for power-efficient base-band filter design. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:162-163 [Conf]
  37. Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Dennis Sylvester
    An efficient static algorithm for computing the soft error rates of combinational circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:164-169 [Conf]
  38. Martin Omaña, José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
    Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:170-175 [Conf]
  39. U. Krautz, Matthias Pflanz, Christian Jacobi 0002, H. W. Tast, Kai Weber, Heinrich Theodor Vierhaus
    Evaluating coverage of error detection logic for soft errors using formal methods. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:176-181 [Conf]
  40. N. Ignat, B. Nicolescu, Yvon Savaria, Gabriela Nicolescu
    Soft-error classification and impact analysis on real-time operating systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:182-187 [Conf]
  41. H. Shrikumar
    40Gbps de-layered silicon protocol engine for TCP record. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:188-193 [Conf]
  42. Amilcar do Carmo Lucas, Sven Heithecker, Peter Rüffer, Rolf Ernst, Holger Rückert, Gerhard Wischermann, Karin Gebel, Reinhard Fach, Wolfgang Huther, Stefan Eichner, Gunter Scheller
    A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:194-199 [Conf]
  43. Torben Brack, Frank Kienle, Norbert Wehn
    Disclosing the LDPC code decoder design space. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:200-205 [Conf]
  44. Robert G. Dimond, Oskar Mencer, Wayne Luk
    Automating processor customisation: optimised memory access and resource sharing. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:206-211 [Conf]
  45. Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi
    Automatic identification of application-specific functional units with architecturally visible storage. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:212-217 [Conf]
  46. Johann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay K. Verma
    Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:218-223 [Conf]
  47. Ahmad Zmily, Christos Kozyrakis
    Simultaneously improving code size, performance, and energy in embedded processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:224-229 [Conf]
  48. Gunar Schirner, Rainer Dömer
    Quantitative analysis of transaction level models for the AMBA bus. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:230-235 [Conf]
  49. Simon Künzli, Francesco Poletti, Luca Benini, Lothar Thiele
    Combining simulation and formal methods for system-level performance analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:236-241 [Conf]
  50. Alexander Viehl, Timo Schönwald, Oliver Bringmann, Wolfgang Rosenstiel
    Formal performance analysis and simulation of UML/SysML models for ESL design. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:242-247 [Conf]
  51. Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf
    Performance evaluation for system-on-chip architectures using trace-based transaction level simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:248-253 [Conf]
  52. Radu Marculescu, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli
    Is "Network" the next "Big Idea" in design? [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:254-256 [Conf]
  53. Goran Frehse, Bruce H. Krogh, Rob A. Rutenbar
    Verifying analog oscillator circuits using forward/backward abstraction refinement. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:257-262 [Conf]
  54. Ting Mei, Jaijeet S. Roychowdhury
    Efficient AC analysis of oscillators using least-squares methods. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:263-268 [Conf]
  55. Trent McConaghy, Georges G. E. Gielen
    Double-strength CAFFEINE: fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit introns. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:269-274 [Conf]
  56. Ewout Martens, Georges G. E. Gielen
    Top-down heterogeneous synthesis of analog and mixed-signal systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:275-280 [Conf]
  57. Jose A. Martinez, Steven P. Levitan, Donald M. Chiarulli
    Nonlinear model order reduction using remainder functions. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:281-282 [Conf]
  58. Huiying Yang, Ranga Vemuri
    Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:283-284 [Conf]
  59. Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
    Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:285-290 [Conf]
  60. Zhiyuan He, Zebo Peng, Petru Eles
    Power constrained and defect-probability driven SoC test scheduling with test set partitioning. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:291-296 [Conf]
  61. Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara
    Power-constrained test scheduling for multi-clock domain SoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:297-302 [Conf]
  62. Chunsheng Liu, Zach Link, Dhiraj K. Pradhan
    Reuse-based test access and integrated test scheduling for network-on-chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:303-308 [Conf]
  63. Sandip Kundu
    A design for failure analysis (DFFA) technique to ensure incorruptible signatures. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:309-310 [Conf]
  64. Pallav Gupta, Niraj K. Jha, Loganathan Lingappan
    Test generation for combinational quantum cellular automata (QCA) circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:311-316 [Conf]
  65. Afshin Abdollahi, Massoud Pedram
    Analysis and synthesis of quantum circuits by using quantum decision diagrams. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:317-322 [Conf]
  66. Fei Su, William L. Hwang, Krishnendu Chakrabarty
    Droplet routing in the synthesis of digital microfluidic biochips. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:323-328 [Conf]
  67. Andrew J. Ricketts, Kevin M. Irick, Narayanan Vijaykrishnan, Mary Jane Irwin
    Priority scheduling in digital microfluidics-based biochips. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:329-334 [Conf]
  68. Debayan Bhaduri, Sandeep K. Shukla, Deji Coker, Valerie Taylor, Paul Graham, Maya Gokhale
    A hybrid framework for design and analysis of fault-tolerant architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:335-336 [Conf]
  69. Jacob R. Minz, Somaskanda Thyagaraja, Sung Kyu Lim
    Optical routing for 3D system-on-package. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:337-338 [Conf]
  70. Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest
    Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:339-344 [Conf]
  71. Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven
    Compositional, efficient caches for a chip multi-processor. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:345-350 [Conf]
  72. Stijn Eyerman, Lieven Eeckhout, Koen De Bosschere
    Efficient design space exploration of high performance embedded out-of-order processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:351-356 [Conf]
  73. Hans Vandierendonck, Philippe Manet, Jean-Didier Legat
    Application-specific reconfigurable XOR-indexing to eliminate cache conflict misses. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:357-362 [Conf]
  74. Minwook Ahn, Jonghee W. Yoon, Yunheung Paek, Yoonjin Kim, Mary Kiemb, Kiyoung Choi
    A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:363-368 [Conf]
  75. Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis
    Compiler-driven FPGA-area allocation for reconfigurable computing. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:369-374 [Conf]
  76. Paulo Sérgio B. do Nascimento, Manoel Eusebio de Lima
    Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:375-380 [Conf]
  77. Ying Yi, Ioannis Nousias, Mark Milward, Sami Khawam, Tughrul Arslan, Iain Lindsay
    System-level scheduling on instruction cell based reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:381-386 [Conf]
  78. Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, R. Sommer, Michael Pronath, A. Ripp
    DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:387-392 [Conf]
  79. Ying Wei, Hua Tang, Alex Doboli
    Systematic methodology for designing reconfigurable Delta-Sigma modulator topologies for multimode communication systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:393-398 [Conf]
  80. Mohammad Yavari, Omid Shoaei, Ángel Rodríguez-Vázquez
    Double-sampling single-loop sigma-delta modulator topologies for broadband applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:399-404 [Conf]
  81. Kambiz K. Moez, Mohamed I. Elmasry
    A 10-GHz 15-dB four-stage distributed amplifier in 0.18 µm CMOS process. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:405-409 [Conf]
  82. José C. García, Juan A. Montiel-Nelson, Saeid Nooshabadi
    Bootstrapped full--swing CMOS driver for low supply voltage operation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:410-411 [Conf]
  83. Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda
    An effective technique for minimizing the cost of processor software-based diagnosis in SoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:412-417 [Conf]
  84. Kai Yang, Kwang-Ting Cheng
    Timing-reasoning-based delay fault diagnosis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:418-423 [Conf]
  85. Yung-Chieh Lin, Kwang-Ting Cheng
    Multiple-fault diagnosis based on single-fault activation and single-output observation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:424-429 [Conf]
  86. Jun Zhou, Hans-Joachim Wunderlich
    Software-based self-test of processors under power constraints. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:430-435 [Conf]
  87. Yu Huang, Keith Gallie
    Diagnosis of defects on scan enable and clock trees. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:436-437 [Conf]
  88. Hyeonjoong Cho, Binoy Ravindran, E. Douglas Jensen
    Lock-free synchronization for dynamic embedded real-time systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:438-443 [Conf]
  89. Ernesto Wandeler, Alexander Maxiaguine, Lothar Thiele
    Performance analysis of greedy shapers in real-time systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:444-449 [Conf]
  90. Rafik Henia, Rolf Ernst
    Improved offset-analysis using multiple timing-references. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:450-455 [Conf]
  91. Zhijian Lu, Yan Zhang, Mircea R. Stan, John Lach, Kevin Skadron
    Procrastinating voltage scheduling with discrete frequency sets. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:456-461 [Conf]
  92. Guang Yang, Xi Chen, Felice Balarin, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli
    Communication and co-simulation infrastructure for heterogeneous system integration. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:462-467 [Conf]
  93. Torsten Kempf, Kingshuk Karuri, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
    A SW performance estimation framework for early system-level-design using fine-grained instrumentation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:468-473 [Conf]
  94. Víctor Reyes, Wido Kruijtzer, Tomás Bautista, Ghiath Alkadi, Antonio Núñez
    A unified system-level modeling and simulation environment for MPSoC design: MPEG-4 decoder case study. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:474-479 [Conf]
  95. M. Streubühr, J. Falk, Christian Haubelt, Jürgen Teich, Rainer Dorsch, Thomas Schlipf
    Task-accurate performance modeling in SystemC for real-time multi-processor architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:480-481 [Conf]
  96. Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Olivier Benny, Damien Lyonnard, Bruno Lavigueur, David Lo
    Distributed object models for multi-processor SoC's, with application to low-power multimedia wireless systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:482-487 [Conf]
  97. Tim Kogel, Matthew Braun
    Virtual prototyping of embedded platforms for wireless and multimedia. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:488-490 [Conf]
  98. Luca Benini
    Application specific NoC design. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:491-495 [Conf]
  99. Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt Jr.
    Automatic insertion of low power annotations in RTL for pipelined microprocessors. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:496-501 [Conf]
  100. Bren Mochocki, Kanishka Lahiri, Srihari Cadambi
    Power analysis of mobile 3D graphics. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:502-507 [Conf]
  101. Nathaniel Pettis, Jason Ridenour, Yung-Hsiang Lu
    Automatic run-time selection of power policies for operating systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:508-513 [Conf]
  102. Changjiu Xian, Yung-Hsiang Lu
    Energy reduction by workload adaptation in a multi-process environment. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:514-519 [Conf]
  103. Jongsun Park, Jung Hwan Choi, Kaushik Roy
    Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:520-521 [Conf]
  104. Brock J. LaMeres, Sunil P. Khatri
    Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:522-527 [Conf]
  105. Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
    Statistical timing analysis with path reconvergence and spatial correlations. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:528-532 [Conf]
  106. Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
    Non-gaussian statistical interconnect timing analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:533-538 [Conf]
  107. Shahin Nazarian, Massoud Pedram
    Cell delay analysis based on rate-of-current change. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:539-544 [Conf]
  108. Frank Liu
    A practical method to estimate interconnect responses to variabilities. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:545-546 [Conf]
  109. C. Sebeke, C. Jung, Klaus Harbich, S. Fuchs, J. Schwarz, Peter Göhner
    Test and reliability challenges in automotive microelectronics. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:547- [Conf]
  110. Sri Kanajan, Haibo Zeng, Claudio Pinello, Alberto L. Sangiovanni-Vincentelli
    Exploring trade-off's between centralized versus decentralized automotive architectures using a virtual integration environment. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:548-553 [Conf]
  111. T. Weber
    Management of complex automotive communication networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:554-555 [Conf]
  112. Andreas Herkersdorf, Walter Stechele
    AutoVision: flexible processor architecture for video-assisted driving. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:556- [Conf]
  113. Klaus D. Müller-Glaser
    Domain specific model driven design for automotive electronic control units. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:557- [Conf]
  114. Pascal Dégardins
    Electric and electronic vehicle architecture assessment. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:558- [Conf]
  115. Patrick Leteinturier
    Automotive semi-conductor trend & challenges. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:559- [Conf]
  116. Junhyung Um, Woo-Cheol Kwon, Sungpack Hong, Young-Taek Kim, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, Taewhan Kim
    A systematic IP and bus subsystem modeling for platform-based system design. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:560-564 [Conf]
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    Design with race-free hardware semantics. [Citation Graph (0, 0)][DBLP]
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    Comfortable modeling of complex reactive systems. [Citation Graph (0, 0)][DBLP]
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    Modeling multiple input switching of CMOS gates in DSM technology using HDMR. [Citation Graph (0, 0)][DBLP]
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    HDL models of ferromagnetic core hysteresis using timeless discretisation of the magnetic slope. [Citation Graph (0, 0)][DBLP]
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  134. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
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    Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking. [Citation Graph (0, 0)][DBLP]
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    Online RF checkers for diagnosing multi-gigahertz automatic test boards on low cost ATE platforms. [Citation Graph (0, 0)][DBLP]
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    Pseudorandom functional BIST for linear and nonlinear MEMS. [Citation Graph (0, 0)][DBLP]
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    On-chip 8GHz non-periodic high-swing noise detector. [Citation Graph (0, 0)][DBLP]
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    Battery-aware code partitioning for a text to speech system. [Citation Graph (0, 0)][DBLP]
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    Performance optimization for energy-aware adaptive checkpointing in embedded real-time systems. [Citation Graph (0, 0)][DBLP]
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    Software annotations for power optimization on mobile devices. [Citation Graph (0, 0)][DBLP]
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  143. Mahmut T. Kandemir, Guangyu Chen, Feihui Li, Mary Jane Irwin, Ibrahim Kolcu
    Activity clustering for leakage management in SPMs. [Citation Graph (0, 0)][DBLP]
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    COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC. [Citation Graph (0, 0)][DBLP]
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    Synthesis of fault-tolerant schedules with transparency/performance trade-offs for distributed embedded systems. [Citation Graph (0, 0)][DBLP]
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    Communication architecture optimization: making the shortest path shorter in regular networks-on-chip. [Citation Graph (0, 0)][DBLP]
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    Buffer space optimisation with communication synthesis and traffic shaping for NoCs. [Citation Graph (0, 0)][DBLP]
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    Cooptimization of interface hardware and software for I/O controllers. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:724-725 [Conf]
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    Cross disciplinary aspects (4G wireless special day). [Citation Graph (0, 0)][DBLP]
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  151. Uwe Lambrette, Booz Allen Hamilton
    SoC: fuelling the hopes of the mobile industry. [Citation Graph (0, 0)][DBLP]
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    Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms. [Citation Graph (0, 0)][DBLP]
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  153. Douglas Densmore, Adam Donlin, Alberto L. Sangiovanni-Vincentelli
    FPGA architecture characterization for system level performance analysis. [Citation Graph (0, 0)][DBLP]
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  154. Alexandros Bartzas, Stylianos Mamagkakis, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
    Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications. [Citation Graph (0, 0)][DBLP]
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  155. Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran
    Customization of application specific heterogeneous multi-pipeline processors. [Citation Graph (0, 0)][DBLP]
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  156. Benny Thörnberg, Mattias O'Nils
    Impact of bit-width specification on the memory hierarchy for a real-time video processing system. [Citation Graph (0, 0)][DBLP]
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  157. Jérémie Guillot, Emmanuel Boutillon, Q. Ren, Maciej J. Ciesielski, D. Gomez-Prado, Serkan Askar
    Efficient factorization of DSP transforms using taylor expansion diagrams. [Citation Graph (0, 0)][DBLP]
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  158. Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C. N. Sze
    Integrated placement and skew optimization for rotary clocking. [Citation Graph (0, 0)][DBLP]
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  159. Min-Seok Kim, Jiang Hu
    Associative skew clock routing for difficult instances. [Citation Graph (0, 0)][DBLP]
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  160. Shantanu Dutt, Hasan Arslan
    Efficient timing-driven incremental routing for VLSI circuits using DFS and localized slack-satisfaction computations. [Citation Graph (0, 0)][DBLP]
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  161. Jing Huang, Mariam Momenzadeh, Fabrizio Lombardi
    Defect tolerance of QCA tiles. [Citation Graph (0, 0)][DBLP]
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  162. Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Mohammad Ashraful Alam, Kaushik Roy
    Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits. [Citation Graph (0, 0)][DBLP]
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  163. Sanjukta Bhanja, Marco Ottavi, Fabrizio Lombardi, Salvatore Pontarelli
    Novel designs for thermally robust coplanar crossing in QCA. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:786-791 [Conf]
  164. Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
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    A time-triggered ethernet (TTE) switch. [Citation Graph (0, 0)][DBLP]
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  166. Martin Schoeberl
    A time predictable Java processor. [Citation Graph (0, 0)][DBLP]
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  167. Marco A. Wehrmeister, Carlos Eduardo Pereira, Leandro Buss Becker
    Optimizing the generation of object-oriented real-time embedded applications based on the real-time specification for Java. [Citation Graph (0, 0)][DBLP]
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  168. Enrico Giunchiglia, Massimo Narizzano, Armando Tacchella
    Quantifier structure in search based procedures for QBFs. [Citation Graph (0, 0)][DBLP]
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  169. HoonSang Jin, Fabio Somenzi
    Strong conflict analysis for propositional satisfiability. [Citation Graph (0, 0)][DBLP]
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  170. Namrata Shekhar, Priyank Kalla, Florian Enescu
    Equivalence verification of arithmetic datapaths with multiple word-length operands. [Citation Graph (0, 0)][DBLP]
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  171. 4G applications, architectures, design methodology and tools for MPSoC. [Citation Graph (0, 0)][DBLP]
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  172. Ashutosh Chakraborty, Prassanna Sithambaram, K. Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino
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  173. Giacomo Paci, Paul Marchal, Francesco Poletti, Luca Benini
    Exploring "temperature-aware" design in low-power MPSoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:838-843 [Conf]
  174. Yonghong Yang, Zhenyu (Peter) Gu, Changyun Zhu, Li Shang, Robert P. Dick
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    DATE, 2006, pp:844-849 [Conf]
  175. Feng Wang 0004, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
    On-chip bus thermal analysis and optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:850-855 [Conf]
  176. Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy
    Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:856-861 [Conf]
  177. Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia
    Low power synthesis of dynamic logic circuits using fine-grained clock gating. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:862-867 [Conf]
  178. Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii
    Enabling fine-grain leakage management by voltage anchor insertion. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:868-873 [Conf]
  179. Stylianos Mamagkakis, David Atienza, Christophe Poucet, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias
    Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems. [Citation Graph (0, 0)][DBLP]
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  180. Andrea Alimonda, Andrea Acquaviva, Salvatore Carta, Alessandro Pisano
    A control theoretic approach to run-time energy optimization of pipelined processing in MPSoCs. [Citation Graph (0, 0)][DBLP]
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  181. Eric Wong, Sung Kyu Lim
    3D floorplanning with thermal vias. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:878-883 [Conf]
  182. Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
    Timing-driven cell layout de-compaction for yield optimization by critical area minimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:884-889 [Conf]
  183. Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang
    Lens aberration aware timing-driven placement. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:890-895 [Conf]
  184. Bram Kruseman, Manuel Heiligers
    On test conditions for the detection of open defects. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:896-901 [Conf]
  185. José Luis Rosselló, Jaume Segura
    A compact model to identify delay faults due to crosstalk. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:902-906 [Conf]
  186. Irith Pomeranz, Sudhakar M. Reddy
    Generation of broadside transition fault test sets that detect four-way bridging faults. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:907-912 [Conf]
  187. Jeffrey E. Nelson, Thomas Zanon, Rao Desineni, Jason G. Brown, N. Patil, Wojciech Maly, R. D. (Shawn) Blanton
    Extraction of defect density and size distributions from wafer sort test results. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:913-918 [Conf]
  188. Hanno Scharwächter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    An interprocedural code optimization technique for network processors using hardware multi-threading support. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:919-924 [Conf]
  189. Sumesh Udayakumaran, Rajeev Barua
    An integrated scratch-pad allocator for affine and non-affine code. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:925-930 [Conf]
  190. Guilin Chen, Ozcan Ozturk, Mahmut T. Kandemir, Mustafa Karaköy
    Dynamic scratch-pad memory management for irregular array access patterns. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:931-936 [Conf]
  191. Keoncheol Shin, Jungeun Kim, Seonggun Kim, Hwansoo Han
    Restructuring field layouts for embedded memory systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:937-942 [Conf]
  192. Po-Kuan Huang, Soheil Ghiasi
    Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:943-944 [Conf]
  193. Hae-woo Park, Kyoungjoo Oh, Soyoung Park, Myoung-min Sim, Soonhoi Ha
    Dynamic code overlay of SDF-modeled programs on low-end embedded systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:945-946 [Conf]
  194. Balasubramanian Sethuraman, Ranga Vemuri
    optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:947-952 [Conf]
  195. Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung, Philip Heng Wai Leong, Stephen J. Motley
    Hardware efficient architectures for Eigenvalue computation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:953-958 [Conf]
  196. Chidamber Kulkarni, Gordon J. Brebner
    Memory centric thread synchronization on platform FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:959-964 [Conf]
  197. Yang Qu, Juha-Pekka Soininen, Jari Nurmi
    A parallel configuration model for reducing the run-time reconfiguration overhead. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:965-969 [Conf]
  198. Paul J. M. Havinga
    Wireless sensor networks and beyond. [Citation Graph (0, 0)][DBLP]
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  199. Amre El-Hoiydi, Claude Arm, R. Caseiro, Stefan Cserveny, Jean-Dominique Decotignie, Christian C. Enz, F. Giroud, S. Gyger, E. Leroux, Thierry Melly, Vincent Peiris, F. Pengg, P.-D. Pfister, N. Raemy, A. Ribordy, D. Ruffieux, P. Volet
    The ultra low-power wiseNET system. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:971-976 [Conf]
  200. Jan Beutel
    Fast-prototyping using the BTnode platform. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:977-982 [Conf]
  201. Qikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy
    Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:983-988 [Conf]
  202. Christian Schuster, Jean-Luc Nagel, Christian Piguet, Pierre-André Farine
    Architectural and technology influence on the optimal total power consumption. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:989-994 [Conf]
  203. Behnam Amelifard, Farzan Fallah, Massoud Pedram
    Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:995-1000 [Conf]
  204. Kaushal R. Gandhi, Nihar R. Mahapatra
    Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1001-1006 [Conf]
  205. Nicola Bombieri, Franco Fummi, Graziano Pravadelli
    On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1007-1012 [Conf]
  206. Felice Balarin, Roberto Passerone
    Functional verification methodology based on formal interface specification and transactor generation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1013-1018 [Conf]
  207. Ian G. Harris
    A coverage metric for the validation of interacting processes. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1019-1024 [Conf]
  208. Vasco Jerinic, Jan Langer, Ulrich Heinkel, Dietmar Müller
    New methods and coverage metrics for functional verification. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1025-1030 [Conf]
  209. Alexander Krupp, Wolfgang Mueller
    Classification trees for random tests and functional coverage. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1031-1032 [Conf]
  210. Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
    Efficient test-data compression for IP cores using multilevel Huffman coding. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1033-1038 [Conf]
  211. Ilia Polian, Hideo Fujiwara
    Functional constraints vs. test compression in scan-based delay testing. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1039-1044 [Conf]
  212. Gang Zeng, Hideo Ito
    Concurrent core test for SOC using shared test set and scan chain disable. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1045-1050 [Conf]
  213. Seongmoon Wang, Kedarnath J. Balakrishnan, Srimat T. Chakradhar
    Efficient unknown blocking using LFSR reseeding. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1051-1052 [Conf]
  214. Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei, Kwang-Ting Cheng
    Coverage loss by using space compactors in presence of unknown values. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1053-1054 [Conf]
  215. Hui Cheng, Steve Goddard
    Online energy-aware I/O device scheduling for hard real-time systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1055-1060 [Conf]
  216. Heng-Ruey Hsu, Jian-Jia Chen, Tei-Wei Kuo
    Multiprocessor synthesis for periodic hard real-time tasks under a given energy constraint. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1061-1066 [Conf]
  217. Hadda Cherroun, Alain Darte, Paul Feautrier
    Scheduling under resource constraints using dis-equations. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1067-1072 [Conf]
  218. Zhe Ma, Francky Catthoor
    Scalable performance-energy trade-off exploration of embedded real-time systems on multiprocessor platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1073-1078 [Conf]
  219. Donald Chai, Andreas Kuehlmann
    Building a better Boolean matcher and symmetry detector. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1079-1084 [Conf]
  220. Cristian Soviani, Olivier Tardieu, Stephen A. Edwards
    Optimizing sequential cycles through Shannon decomposition and retiming. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1085-1090 [Conf]
  221. Christoph Albrecht
    Efficient incremental clock latency scheduling for large circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1091-1096 [Conf]
  222. Subodh M. Reddy, Gustavo R. Wilke, Rajeev Murgai
    Analyzing timing uncertainty in mesh-based clock architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1097-1102 [Conf]
  223. Alvise Bonivento, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
    Platform-based design of wireless sensor networks for industrial applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1103-1107 [Conf]
  224. Vlado Handziski, Andreas Köpke, Andreas Willig, Adam Wolisz
    An environment for controlled experiments with in-house sensor networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1108- [Conf]
  225. Philippe Bonnet, Martin Leopold, K. Madsen
    Hogthrob: towards a sensor network infrastructure for sow monitoring (wireless sensor network special day). [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1109- [Conf]
  226. Lakshmi N. Chakrapani, Bilge E. S. Akgul, Suresh Cheemalavagu, Pinar Korkmaz, Krishna V. Palem, Balasubramanian Seshasayee
    Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1110-1115 [Conf]
  227. Mark M. Budnik, Kaushik Roy
    Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1116-1121 [Conf]
  228. Yen-Jen Chang
    An ultra low-power TLB design. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1122-1127 [Conf]
  229. Peng Rong, Massoud Pedram
    Determining the optimal timeout values for a power-managed system based on the theory of Markovian processes: offline and online algorithms. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1128-1133 [Conf]
  230. David W. Matula, Lee D. McFearin
    A formal model and efficient traversal algorithm for generating testbenches for verification of IEEE standard floating point division. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1134-1138 [Conf]
  231. Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
    On the relation between simulation-based and SAT-based diagnosis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1139-1144 [Conf]
  232. Federico Angiolini, Jianjiang Ceng, Rainer Leupers, Federico Ferrari, Cesare Ferri, Luca Benini
    An integrated open framework for heterogeneous MPSoC design space exploration. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1145-1150 [Conf]
  233. Dohyung Kim, Soonhoi Ha, Rajesh Gupta
    Parallel co-simulation using virtual synchronization with redundant host execution. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1151-1156 [Conf]
  234. Hiroaki Nakamura, Naoto Sato, Naoshi Tabuchi
    An efficient and portable scheduler for RTOS simulation and its certified integration to SystemC. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1157-1158 [Conf]
  235. Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard
    Minimizing test power in SRAM through reduction of pre-charge activity. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1159-1164 [Conf]
  236. Vishal Suthar, Shantanu Dutt
    Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1165-1170 [Conf]
  237. Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi
    A concurrent testing method for NoC switches. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1171-1176 [Conf]
  238. David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre
    A secure scan design methodology. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1177-1178 [Conf]
  239. Chen He, Margarida F. Jacome
    RAS-NANO: a reliability-aware synthesis framework for reconfigurable nanofabrics. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1179-1184 [Conf]
  240. Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer, Adam Kaplan, Philip Brisk, Majid Sarrafzadeh
    Layout driven data communication optimization for high level synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1185-1190 [Conf]
  241. Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos
    Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1191-1196 [Conf]
  242. Sanghyun Park, Eugene Earlie, Aviral Shrivastava, Alex Nicolau, Nikil Dutt, Yunheung Paek
    Automatic generation of operation tables for fast exploration of bypasses in embedded processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1197-1202 [Conf]
  243. Soumya Pandit, Sougata Kar, Chittaranjan A. Mandal, Amit Patra
    High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1203-1204 [Conf]
  244. Chao Wang, Zijiang Yang, Franjo Ivancic, Aarti Gupta
    Disjunctive image computation for embedded software verification. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1205-1210 [Conf]
  245. Smitha Shyam, Valeria Bertacco
    Distance-guided hybrid verification with GUIDO. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1211-1216 [Conf]
  246. Sayantan Das, Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti
    What lies between design intent coverage and model checking? [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1217-1222 [Conf]
  247. Jounaïdi Ben Hassen, Sofiène Tahar
    On the numerical verification of probabilistic rewriting systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1223-1224 [Conf]
  248. Görschwin Fey, Daniel Große, Rolf Drechsler
    Avoiding false negatives in formal verification for protocol-driven blocks. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1225-1226 [Conf]
  249. Enrico Macii, Massoud Pedram, Dirk Friebel, Robert C. Aitken, Antun Domic, Roberto Zafalon
    Low-power design tools: are EDA vendors taking this matter seriously? [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1227- [Conf]
  250. Daniel Karlsson, Petru Eles, Zebo Peng
    Formal verification of systemc designs using a petri-net based representation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1228-1233 [Conf]
  251. Roma Kane, Panagiotis Manolios, Sudarshan K. Srinivasan
    Monolithic verification of deep pipelines with collapsed flushing. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1234-1239 [Conf]
  252. Heon-Mo Koo, Prabhat Mishra
    Functional test generation using property decompositions for validation of pipelined processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1240-1245 [Conf]
  253. Katell Morin-Allory, Dominique Borrione
    Proven correct monitors from PSL specifications. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1246-1251 [Conf]
  254. Zaid Al-Ars, Said Hamdioui, A. J. van de Goor
    Space of DRAM fault models and corresponding testing. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1252-1257 [Conf]
  255. Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
    Automatic march tests generations for static linked faults in SRAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1258-1263 [Conf]
  256. Irith Pomeranz, Sudhakar M. Reddy
    Test compaction for transition faults under transparent-scan. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1264-1269 [Conf]
  257. Zhanglei Wang, Krishnendu Chakrabarty, Michael Gössel
    Test set enrichment using a probabilistic fault model and the theory of output deviations. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1270-1275 [Conf]
  258. Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Tahoori, David R. Kaeli
    Vulnerability analysis of L2 cache elements to single event upsets. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1276-1281 [Conf]
  259. Soontae Kim
    Area-efficient error protection for caches. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1282-1287 [Conf]
  260. Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh
    Microarchitectural floorplanning under performance and thermal tradeoff. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1288-1293 [Conf]
  261. Anup Hosangadi, Farzan Fallah, Ryan Kastner
    Optimizing high speed arithmetic circuits using three-term extraction. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1294-1299 [Conf]
  262. Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa
    Efficient minimization of fully testable 2-SPP networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1300-1305 [Conf]
  263. Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
    Pre-synthesis optimization of multiplications to improve circuit performance. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1306-1311 [Conf]
  264. Yi-Yu Liu, TingTing Hwang
    Crosstalk-aware domino logic synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1312-1317 [Conf]
  265. Wolfgang Klingauf, Hagen Gädke, Robert Günzel
    TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1318-1323 [Conf]
  266. Tero Arpinen, Petri Kukkala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen
    Configurable multiprocessor platform with RTOS for distributed execution of UML 2.0 designed applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1324-1329 [Conf]
  267. Olivier Muller, Amer Baghdadi, Michel Jézéquel
    ASIP-based multiprocessor SoC design for simple and double binary turbo decoding. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1330-1335 [Conf]
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