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Conferences in DBLP

Design, Automation, and Test in Europe (date)
2006 (conf/date/2006)

  1. Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Architectures for efficient face authentication in embedded systems. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:1-6 [Conf]
  2. Guido Bertoni, Luca Breveglieri, Pasqualina Fragneto, Gerardo Pelosi, L. Sportiello
    Software implementation of Tate pairing over GF(2m). [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:7-11 [Conf]
  3. Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang
    Optimization of regular expression pattern matching circuits on FPGA. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:12-17 [Conf]
  4. Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee
    Satisfiability-based framework for enabling side-channel attacks on cryptographic software. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:18-23 [Conf]
  5. Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang
    An 830mW, 586kbps 1024-bit RSA chip design. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:24-29 [Conf]
  6. Dmitry Akselrod, Asaf Ashkenazi, Yossi Amon
    Platform independent debug port controller architecture with security protection for multi-processor system-on-chip ICs. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:30-35 [Conf]
  7. Francisco-Javier Veredas, Michael Scheppler, Hans-Jörg Pfleiderer
    Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:36-41 [Conf]
  8. Maurice Meijer, Rohini Krishnan, Martijn T. Bennebroek
    Energy-efficient FPGA interconnect design. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:42-47 [Conf]
  9. Maurizio Martina, Guido Masera, Andrea Molino, Fabrizio Vacca, Luca Sterpone, Massimo Violante
    A new approach to compress the configuration information of programmable devices. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:48-51 [Conf]
  10. Javier Davila, Alfonso de Torres, Jose Manuel Sanchez, Marcos Sanchez-Elez, Nader Bagherzadeh, F. Rivera
    Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys). [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:52-57 [Conf]
  11. G. Kappen, Tobias G. Noll
    Application specific instruction processor based implementation of a GNSS receiver on an FPGA. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:58-63 [Conf]
  12. Michael Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo
    A methodology for FPGA to structured-ASIC synthesis and verification. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:64-69 [Conf]
  13. Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P. Chakrabarti
    Synthesis of system verilog assertions. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:70-75 [Conf]
  14. Ali Habibi, Haja Moinudeen, Sofiène Tahar
    Generating finite state machines from SystemC. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:76-81 [Conf]
  15. Jan-Hendrik Oetjens, Joachim Gerlach, Wolfgang Rosenstiel
    Flexible specification and application of rule-based transformations in an automotive design flow. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:82-87 [Conf]
  16. Giuseppe Bonfini, Monica Chiavacci, Riccardo Mariani, Egidio Pescari
    A mixed-signal verification kit for verification of analogue-digital circuits. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:88-93 [Conf]
  17. Pierluigi Daglio
    A complete and fully qualified design flow for verification of mixed-signal SoC with embedded flash memories. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:94-99 [Conf]
  18. Juanjo Noguera, Luis Baldez, Narcis Simon, Lluis Abello
    Software-friendly HW/SW co-simulation: an industrial case study. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:100-105 [Conf]
  19. Franco Fummi, Davide Quaglia, Fabio Ricciato, Maura Turolla
    Modeling and simulation of mobile gateways interacting with wireless sensor networks. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:106-111 [Conf]
  20. Vassilis Papaefstathiou, Ioannis Papaefstathiou
    A hardware-engine for layer-2 classification in low-storage, ultra-high bandwidth environments. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:112-117 [Conf]
  21. Daniele Lo Iacono, J. Zory, Ettore Messina, N. Piazzese, G. Saia, A. Bettinelli
    ASIP architecture for multi-standard wireless terminals. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:118-123 [Conf]
  22. Federico Quaglio, Fabrizio Vacca, Cristiano Castellano, Alberto Tarable, Guido Masera
    Interconnection framework for high-throughput, flexible LDPC decoders. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:124-129 [Conf]
  23. John Dielissen, Andries Hekstra, Vincent Berg
    Low cost LDPC decoder for DVB-S2. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:130-135 [Conf]
  24. Michele Sama, Vincenzo Pacella, Elisabetta Farella, Luca Benini, Bruno Riccò
    3dID: a low-power, low-cost hand motion capture device. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:136-141 [Conf]
  25. Christopher K. Lennard, Victor Berman, Saverio Fazzari, Mark Indovina, Cary Ussery, Marino Strik, John Wilson, Olivier Florent, François Rémond, Pierre Bricaud
    Industrially proving the SPIRIT consortium specifications for design chain integration. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:142-147 [Conf]
  26. Frits Steenhof, Harry Duque, Björn Nilsson, Kees Goossens, Rafael Peset Llopis
    Networks on chips for high-end consumer-electronics TV system architectures. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:148-153 [Conf]
  27. Luciano Bononi, Nicola Concer
    Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:154-159 [Conf]
  28. G. Campobello, M. Castano, C. Ciofi, Daniele Mangano
    GALS networks on chip: a new solution for asynchronous delay-insensitive links. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:160-165 [Conf]
  29. Florin Dumitrascu, Iuliana Bacivarov, Lorenzo Pieralisi, Marius Bonaciu, Ahmed Amine Jerraya
    Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:166-171 [Conf]
  30. Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta, Melvin A. Breuer
    STAX: statistical crosstalk target set compaction. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:172-177 [Conf]
  31. Kuo-Hsing Cheng, Yu-lung Lo
    A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:178-182 [Conf]
  32. Kai Richter, Rolf Ernst
    How OEMs and suppliers can face the network integration challenges. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:183-188 [Conf]
  33. Fabiano Costa Carvalho, Carlos Eduardo Pereira, Elias Teodoro Silva Jr., Edison Pignaton Freitas
    A practical implementation of the fault-tolerant daisy-chain clock synchronization algorithm on CAN. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:189-194 [Conf]
  34. G. Zarri, F. Colucci, F. Dupuis, R. Mariani, M. Pasquariello, G. Risaliti, C. Tibaldi
    On the verification of automotive protocols. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:195-200 [Conf]
  35. F. Baronti, P. D'Abramo, M. Knaipp, R. Minixhofer, R. Roncella, Roberto Saletti, M. Schrems, R. Serventi, V. Vescoli
    FlexRay transceiver in a 0.35 µm CMOS high-voltage technology. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:201-205 [Conf]
  36. Andreas Raabe, Stefan Hochgürtel, Joachim K. Anlauf, Gabriel Zachmann
    Space-efficient FPGA-accelerated collision detection for virtual prototyping. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:206-211 [Conf]
  37. Sergio Saponara, Pierangelo Terreni
    Mixed-signal design of a digital input power amplifier for automotive audio applications. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:212-216 [Conf]
  38. N. Bannow, K. Haug, Wolfgang Rosenstiel
    Automatic systemC design configuration for a faster evaluation of different partitioning alternatives. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:217-218 [Conf]
  39. L. Serafini, F. Carrai, T. Ramacciotti, V. Zolesi
    Multi-sensor configurable platform for automotive applications. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:219-220 [Conf]
  40. Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia
    Design and implementation of a modular and portable IEEE 754 compliant floating-point unit. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:221-226 [Conf]
  41. Sutjipto Arifin, Peter Y. K. Cheung
    A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentation. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:227-232 [Conf]
  42. Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
    ASIP design and synthesis for non linear filtering in image processing. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:233-238 [Conf]
  43. Chingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang
    A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:239-243 [Conf]
  44. Nicolas Mäding, Jens Leenstra, Juergen Pille, R. Sautter, S. Büttner, S. Ehrenreich, W. Haller
    The vector fixed point unit of the synergistic processor element of the cell architecture processor. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:244-248 [Conf]
  45. Ju-Ho Sohn, Jeong-Ho Woo, Jerald Yoo, Hoi-Jun Yoo
    Design and test of fixed-point multimedia co-processor for mobile applications. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:249-253 [Conf]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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