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Conferences in DBLP

Design, Automation, and Test in Europe (date)
2004 (conf/date/2005)

  1. Sebastián López, Gustavo Marrero Callicó, José Francisco López, Roberto Sarmiento
    A High Quality/Low Computational Cost Technique for Block Matching Motion Estimation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:2-7 [Conf]
  2. Jeong-Taek Kong
    SoC in Nanoera: Challenges and Endless Possibility. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:2- [Conf]
  3. Garry Hughes
    Striking a New Balance in the Nanometer Era: First-Time-Right and Time-to-Market Demands Versus Technology Challenges. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:3- [Conf]
  4. Nastaran Baradaran, Pedro C. Diniz
    A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:6-11 [Conf]
  5. Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk
    Hardware Acceleration of Hidden Markov Model Decoding for Person Detection. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:8-13 [Conf]
  6. Yoonjin Kim, Mary Kiemb, Chulsoo Park, Jinyong Jung, Kiyoung Choi
    Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:12-17 [Conf]
  7. Hendrik Eeckhaut, Harald Devos, Benjamin Schrauwen, Mark Christiaens, Dirk Stroobandt
    A Hardware-Friendly Wavelet Entropy Codec for Scalable Video. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:14-19 [Conf]
  8. Roman L. Lysecky, Frank Vahid
    A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:18-23 [Conf]
  9. Artur Burchard, Ewa Hekstra-Nowacka, Atul Chauhan
    A Real-Time Streaming Memory Controller. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:20-25 [Conf]
  10. Ray C. C. Cheung, Wayne Luk, Peter Y. K. Cheung
    Reconfigurable Elliptic Curve Cryptosystems on a Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:24-29 [Conf]
  11. Walter Stechele, L. Alvado Cárcel, Stephan Herrmann, J. Lidón Simón
    A Coprocessor for Accelerating Visual Information Processing. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:26-31 [Conf]
  12. Rui Rodrigues, João M. P. Cardoso
    An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:30-31 [Conf]
  13. Sandro V. Silva, Sergio Bampi
    Area and Throughput Trade-Offs in the Design of Pipelined Discrete Wavelet Transform Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:32-37 [Conf]
  14. N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin
    FPGA Architecture for Multi-Style Asynchronous Logic. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:32-33 [Conf]
  15. Georges G. E. Gielen, Wim Dehaene, Phillip Christie, Dieter Draxelmayr, Edmond Janssens, Karen Maex, Ted Vucurevich
    Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:36-42 [Conf]
  16. Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, C. Anguille, Michel Bardouillet, Christian Buatois, Jean-Baptiste Rigaud
    Hardware Engines for Bus Encryption: A Survey of Existing Techniques. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:40-45 [Conf]
  17. Sandeep Kumar Goel, Erik Jan Marinissen
    On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:44-49 [Conf]
  18. Daniel Thull, Roberto Sannino
    Performance Considerations for an Embedded Implementation of OMA DRM 2. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:46-51 [Conf]
  19. Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chakrabarty
    Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:50-55 [Conf]
  20. Alessandro Cilardo, Antonino Mazzeo, Nicola Mazzocca, Luigi Romano
    A Novel Unified Architecture for Public-Key Cryptography. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:52-57 [Conf]
  21. Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press
    Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:56-61 [Conf]
  22. Kris Tiri, Ingrid Verbauwhede
    A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:58-63 [Conf]
  23. Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno
    Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:62-63 [Conf]
  24. Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Dimitrios N. Serpanos, Yuan Xie
    Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:64-69 [Conf]
  25. Stephen A. Edwards
    The Challenges of Hardware Synthesis from C-Like Languages. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:66-67 [Conf]
  26. Alexander G. Dean
    Software Thread Integration and Synthesis for Real-Time Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:68-69 [Conf]
  27. Ian Oliver
    Applying UML and MDA to Real Systems Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:70-71 [Conf]
  28. Zoya Dyka, Peter Langendoerfer
    Area Efficient Hardware Implementation of Elliptic Curve Cryptography by Iteratively Applying Karatsuba's Method. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:70-75 [Conf]
  29. Diana Marculescu
    Energy Bounds for Fault-Tolerant Nanoscale Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:74-79 [Conf]
  30. Hala A. Farouk, Magdy Saeb
    An Improved FPGA Implementation of the Modified Hybrid Hiding Encryption Algorithm (MHHEA) for Data Communication Security. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:76-81 [Conf]
  31. Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin
    DVS for On-Chip Bus Designs Based on Timing Error Correction. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:80-85 [Conf]
  32. Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. Kamakoti
    FPGA based Agile Algorithm-On-Demand Co-Processor. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:82-83 [Conf]
  33. Le Cai, Yung-Hsiang Lu
    Joint Power Management of Memory and Disk. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:86-91 [Conf]
  34. Wayne Wolf
    Multimedia Applications of Multiprocessor Systems-on-Chips. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:86-89 [Conf]
  35. Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
    Assertion-Based Design Exploration of DVS in Network Processor Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:92-97 [Conf]
  36. Keith Holt
    Wireless LAN: Past, Present, and Future. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:92-93 [Conf]
  37. Raúl Blázquez, Fred Lee, David D. Wentzloff, Brian P. Ginsburg, Johnna Powell, Anantha Chandrakasan
    Direct Conversion Pulsed UWB Transceiver Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:94-95 [Conf]
  38. Tajana Simunic
    Power Saving Techniques for Wireless LANs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:96-97 [Conf]
  39. Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis
    Instruction Scheduling for Dynamic Hardware Configurations. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:100-105 [Conf]
  40. Frank Kienle, Torben Brack, Norbert Wehn
    A Synthesizable IP Core for DVB-S2 LDPC Code Decoding. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:100-105 [Conf]
  41. Javier Resano, Daniel Mozos, Francky Catthoor
    A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:106-111 [Conf]
  42. Andrew Duller, Daniel Towner, Gajinder Panesar, Alan Gray, Will Robbins
    picoArray Technology: The Tool's Story. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:106-111 [Conf]
  43. Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers
    Optimized Generation of Data-Path from C Codes for FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:112-117 [Conf]
  44. Ioannis Papaefstathiou, Theofanis Orphanoudakis, George Kornaros, Christopher Kachris, Ioannis Mavroidis, Aristides Nikologiannis
    Queue Management in Network Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:112-117 [Conf]
  45. Massimo Conti, Daniele Moretti
    System Level Analysis of the Bluetooth Standard. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:118-123 [Conf]
  46. Ewout Martens, Georges G. E. Gielen
    Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:120-125 [Conf]
  47. Andrés Takach, Bryan Bowyer, Thomas Bollaert
    C Based Hardware Design for Wireless Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:124-129 [Conf]
  48. Fang Liu, Jacob J. Flomenberg, Devaka V. Yasaratne, Sule Ozev
    Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:126-131 [Conf]
  49. Andreas Raabe, Blazej Bartyzel, Joachim K. Anlauf, Gabriel Zachmann
    Hardware Accelerated Collision Detection - An Architecture and Simulation Results. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:130-135 [Conf]
  50. Hratch Mangassarian, Mohab Anis
    On Statistical Timing Analysis with Inter- and Intra-Die Variations. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:132-137 [Conf]
  51. Hannu Heusala, Jussi Liedes
    Modeling of a Reconfigurable OFDM IP Block Family For an RF System Simulator. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:136-137 [Conf]
  52. Young-Taek Kim, Taehun Kim, Youngduk Kim, Chulho Shin, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo
    Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:138-139 [Conf]
  53. Raoul F. Badaoui, Ranga Vemuri
    Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:138-143 [Conf]
  54. Wayne Lyons
    Meeting the Embedded Design Needs of Automotive Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:142-147 [Conf]
  55. Koichiro Noguchi, Makoto Nagata
    On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:146-151 [Conf]
  56. A. Mayer, H. Siebert, Klaus D. McDonald-Maier
    Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:148-152 [Conf]
  57. David C. Keezer, C. Gray, A. M. Majid, N. Taher
    Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:152-157 [Conf]
  58. Carl Jeffrey, Reuben Cutajar, Stephen Prosser, M. Lickess, Andrew Richardson, Stephen Riches
    The Integration of On-Line Monitoring and Reconfiguration Functions using IEEE1149.4 Into a Safety Critical Automotive Electronic Control Unit. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:153-158 [Conf]
  59. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Noise Figure Evaluation Using Low Cost BIST. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:158-163 [Conf]
  60. Pavel Horsky
    LC Oscillator Driver for Safety Critical Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:159-164 [Conf]
  61. Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi
    Specification Test Compaction for Analog Circuits and MEMS. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:164-169 [Conf]
  62. Jan Staschulat, Rolf Ernst, Andreas Schulze, Fabian Wolf
    Context Sensitive Performance Analysis of Automotive Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:165-170 [Conf]
  63. Rabeb Kheriji, V. Danelon, Jean-Louis Carbonéro, Salvador Mir
    Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:170-171 [Conf]
  64. Dirk Ziegenbein, Peter Braun 0003, Ulrich Freund, Andreas Bauer 0002, Jan Romberg, Bernhard Schätz
    AutoMoDe - Model-Based Development of Automotive Software. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:171-177 [Conf]
  65. Pekka Syri, Juha Häkkinen, Markku Moilanen
    EEE 1149.4 Compatible ABMs for Basic RF Measurements. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:172-173 [Conf]
  66. Carlos Eduardo Savioli, Claudio C. Czendrodi, José Vicente Calvano, Antonio Carneiro de Mesquita Filho
    Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:174-175 [Conf]
  67. Massimo Conti
    SystemC Analysis of a New Dynamic Power Management Architectur. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:177-178 [Conf]
  68. Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:178-183 [Conf]
  69. Steve Chappell, Alistair Macarthur, Dan Preston, Dave Olmstead, Bob Flint, Chris Sullivan
    Exploiting Real-Time FPGA Based Adaptive Systems Technology for Real-Time Sensor Fusion in Next Generation Automotive Safety Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:180-185 [Conf]
  70. Jung-Chun Kao, Radu Marculescu
    Energy-Aware Routing for E-Textile Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:184-189 [Conf]
  71. Luca Fanucci, A. Giambastiani, Francesco Iozzi, Corrado Marino, A. Rocchi
    Platform Based Design for Automotive Sensor Conditioning. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:186-191 [Conf]
  72. Arijit Ghosh, Tony Givargis
    LORD: A Localized, Reactive and Distributed Protocol for Node Scheduling in Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:190-195 [Conf]
  73. Paolo Amato, Nicola Cesario, M. Di Meglio, Francesco Pirozzi
    Realization of a Virtual Lambda Sensor on a Fixed Precision System. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:192-197 [Conf]
  74. Bruno Bougard, Francky Catthoor, Denis C. Daly, Anantha Chandrakasan, Wim Dehaene
    Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:196-201 [Conf]
  75. Claudio Stagni, Carlotta Guiducci, Massimo Lanzoni, Luca Benini, Bruno Riccò
    Hardware-Software Design of a Smart Sensor for Fully-Electronic DNA Hybridization Detection. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:198-203 [Conf]
  76. Vivek Rai, Rabi N. Mahapatra
    Lifetime Modeling of a Sensor Network. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:202-203 [Conf]
  77. Momchil Milev, Rod Burt
    A Tool and Methodology for AC-Stability Analysis of Continuous-Time Closed-Loop Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:204-208 [Conf]
  78. José Luis Rosselló, V. Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura
    A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:206-211 [Conf]
  79. Kay-Uwe Kirstein, Jan Sedivý, Tomi Salo, Christoph Hagleitner, Tobias Vancura, Andreas Hierlemann
    A CMOS-Based Tactile Sensor for Continuous Blood Pressure Monitoring. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:210-214 [Conf]
  80. Kay-Uwe Kirstein, Jan Sedivý, Tomi Salo, Christoph Hagleitner, Tobias Vancura, Andreas Hierlemann
    A CMOS-Based Tactile Sensor for Continuous Blood Pressure Monitoring. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:210-214 [Conf]
  81. Hassan Hassan, Mohab Anis, Antoine El Daher, Mohamed I. Elmasry
    Activity Packing in FPGAs for Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:212-217 [Conf]
  82. Johannes Sturm, Martin Leifhelm, Harald Schatzmayr, Stefan Groiss, Horst Zimmermann
    Optical Receiver IC for CD/DVD/Blue-Laser Application. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:215-218 [Conf]
  83. Johannes Sturm, Martin Leifhelm, Harald Schatzmayr, Stefan Groiss, Horst Zimmermann
    Optical Receiver IC for CD/DVD/Blue-Laser Application. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:215-218 [Conf]
  84. Suresh Srinivasan, Lin Li, Narayanan Vijaykrishnan
    Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:218-223 [Conf]
  85. Terje N. Andersen, Atle Briskemyr, Frode Telstø, Johnny Bjørnsen, Thomas E. Bonnerud, Bjørnar Hernes, Øystein Moldsvor
    A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18mum Digital CMOS. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:219-222 [Conf]
  86. Terje N. Andersen, Atle Briskemyr, Frode Telstø, Johnny Bjørnsen, Thomas E. Bonnerud, Bjørnar Hernes, Øystein Moldsvor
    A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18mum Digital CMOS. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:219-222 [Conf]
  87. Christoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner
    A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13?m Digital CMOS. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:223-226 [Conf]
  88. Christoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner
    A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13?m Digital CMOS. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:223-226 [Conf]
  89. Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
    Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:224-229 [Conf]
  90. Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda
    Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:228-233 [Conf]
  91. Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda
    Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:228-233 [Conf]
  92. Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
    Leakage-Aware Interconnect for On-Chip Network. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:230-231 [Conf]
  93. Aline Mello, Leandro Möller, Ney Calazans, Fernando Gehm Moraes
    MultiNoC: A Multiprocessing System Enabled by a Network on Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:234-239 [Conf]
  94. Vincent Nollet, Théodore Marescaux, Prabhat Avasare, Jean-Yves Mignolet
    Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:234-239 [Conf]
  95. Aline Mello, Leandro Möller, Ney Calazans, Fernando Gehm Moraes
    MultiNoC: A Multiprocessing System Enabled by a Network on Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:234-239 [Conf]
  96. Dan Hillman
    Using Mobilize Power Management IP for Dynamic & Static Power Reduction in SoC at 130 nm. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:240-246 [Conf]
  97. Austin Hung, William D. Bishop, Andrew A. Kennings
    Symmetric Multiprocessing on Programmable Chips Made Easy. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:240-245 [Conf]
  98. Dan Hillman
    Using Mobilize Power Management IP for Dynamic & Static Power Reduction in SoC at 130 nm. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:240-246 [Conf]
  99. Nicolas Genko, David Atienza, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida, Francky Catthoor
    A Complete Network-On-Chip Emulation Framework. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:246-251 [Conf]
  100. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:247-252 [Conf]
  101. Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:247-252 [Conf]
  102. Vincent Nollet, Prabhat Avasare, Jean-Yves Mignolet, Diederik Verkest
    Low Cost Task Migration Initiation in a Heterogeneous MP-SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:252-253 [Conf]
  103. Tero Rissa, Adam Donlin, Wayne Luk
    Evaluation of SystemC Modelling of Reconfigurable Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:253-258 [Conf]
  104. Tero Rissa, Adam Donlin, Wayne Luk
    Evaluation of SystemC Modelling of Reconfigurable Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:253-258 [Conf]
  105. Sander Stuijk, Twan Basten, Bart Mesman, Marc Geilen
    Predictable Embedding of Large Data Structures in Multiprocessor Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:254-255 [Conf]
  106. Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici
    Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:258-263 [Conf]
  107. Michael Ullmann, Wansheng Jin, Jürgen Becker
    Hardware Support for QoS-based Function Allocation in Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:259-264 [Conf]
  108. Michael Ullmann, Wansheng Jin, Jürgen Becker
    Hardware Support for QoS-based Function Allocation in Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:259-264 [Conf]
  109. Hua Tang, Ying Wei, Alex Doboli
    MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:264-269 [Conf]
  110. Michele Borgatti, Andrea Capello, Umberto Rossi, Jean-Luc Lambert, Imed Moussa, Franco Fummi, Graziano Pravadelli
    An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:266-271 [Conf]
  111. Michele Borgatti, Andrea Capello, Umberto Rossi, Jean-Luc Lambert, Imed Moussa, Franco Fummi, Graziano Pravadelli
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  115. Ludovic Barrandon, S. Crand, Dominique Houzet
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  121. Yasushi Umezawa, Takeshi Shimizu
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  126. Jonathan R. Carter, Sule Ozev, Daniel J. Sorin
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  127. Ghazanfar Asadi, Mehdi Baradaran Tahoori
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  129. Arne Hamann, Rolf Ernst
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  130. Jennifer L. Wong, Weiping Liao, Fei Li, Lei He, Miodrag Potkonjak
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  131. Fernando Rincón, Francisco Moya, Jesús Barba, Juan Carlos López
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  135. Ali Iranli, Hanif Fatemi, Massoud Pedram
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  141. Jae-Gon Lee, Moo-Kyoung Chung, Ki-Yong Ahn, Sang-Heon Lee, Chong-Min Kyung
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  142. Ambar A. Gadkari, S. Ramesh
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  145. Maxim Teslenko, Elena Dubrova
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  146. Alan Mishchenko, Robert K. Brayton
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  148. G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain
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  149. Andrés Martinelli, Elena Dubrova
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  150. Igor L. Markov, Dmitri Maslov
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  151. Guowu Yang, William N. N. Hung, Xiaoyu Song, Marek A. Perkowski
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  155. Eric Liau, Doris Schmitt-Landsiedel
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  156. Laurent Lopez, Jean Michel Portal, Didier Née
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  162. Karsten Albers, Frank Slomka
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  164. César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel
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  180. Yervant Zorian, Bill Frerichs, Dennis Wassung, Jim Ensel, Guri Stark, Mike Gianfagna, Kamalesh N. Ruparel
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  184. Balkaran S. Gill, Michael Nicolaidis, Francis G. Wolff, Christos A. Papachristou, Steven L. Garverick
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  185. Lars Wehmeyer, Peter Marwedel
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  186. Ingomar Wenzel, Bernhard Rieder, Raimund Kirner, Peter P. Puschner
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  187. Claire Burguière, Christine Rochange
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  188. Reinhold Heckmann, Christian Ferdinand
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    DATE, 2005, pp:618-619 [Conf]
  189. Jawad Khan, Ranga Vemuri
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  190. Kris Tiri, Ingrid Verbauwhede
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  192. Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne
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  193. Takeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami, Katsuhiro Seta, Toshiyuki Furusawa
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    DATE, 2005, pp:798-803 [Conf]
  225. Oreste Villa, Patrick Schaumont, Ingrid Verbauwhede, Matteo Monchiero, Gianluca Palermo
    Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:804-805 [Conf]
  226. Ilya Issenin, Nikil D. Dutt
    FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:808-813 [Conf]
  227. Ozcan Ozturk, Mahmut T. Kandemir
    Nonuniform Banking for Reducing Memory Energy Consumption. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:814-819 [Conf]
  228. Vinil Varghese, Tom Chen, Peter M. Young
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    DATE, 2005, pp:820-825 [Conf]
  229. Sankalp Kallakuri, Alex Doboli, Eugene A. Feinberg
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    DATE, 2005, pp:826-827 [Conf]
  230. Pu Hanlai, Ling Ming, Jin Jing
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    DATE, 2005, pp:828-829 [Conf]
  231. Tim Schattkowsky
    UML 2.0 - Overview and Perspectives in SoC Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:832-833 [Conf]
  232. Stephen J. Mellor, John R. Wolfe, Campbell McCausland
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    DATE, 2005, pp:834-835 [Conf]
  233. Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata
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    DATE, 2005, pp:836-837 [Conf]
  234. Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty
    Rapid Generation of Thermal-Safe Test Schedules. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:840-845 [Conf]
  235. Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
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    DATE, 2005, pp:846-851 [Conf]
  236. Baosheng Wang, Yuejian Wu, André Ivanov
    A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:852-857 [Conf]
  237. Ghenadie Bodean, D. Bodean, A. Labunetz
    New Schemes for Self-Testing RAM. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:858-859 [Conf]
  238. B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, P. Hsu, J. Cho, J. Park, H. Chao, Shianling Wu
    At-Speed Logic BIST for IP Cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:860-861 [Conf]
  239. Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Peng
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    DATE, 2005, pp:864-869 [Conf]
  240. Mahmut T. Kandemir, Guilin Chen
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    DATE, 2005, pp:870-875 [Conf]
  241. Torsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout
    A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:876-881 [Conf]
  242. Ozcan Ozturk, Hendra Saputra, Mahmut T. Kandemir, Ibrahim Kolcu
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    DATE, 2005, pp:882-887 [Conf]
  243. Ryan Mannion, Harry Hsieh, Susan Cotterell, Frank Vahid
    System Synthesis for Networks of Programmable Blocks. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:888-893 [Conf]
  244. Thilo Streichert, Christian Haubelt, Jürgen Teich
    Distributed HW/SW-Partitioning for Embedded Reconfigurable Networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:894-895 [Conf]
  245. Pierre Bomel, Eric Martin, Emmanuel Boutillon
    Synchronization Processor Synthesis for Latency Insensitive Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:896-897 [Conf]
  246. Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Thermal-Aware Task Allocation and Scheduling for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:898-899 [Conf]
  247. Kristofer Vorwerk, Andrew A. Kennings
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    DATE, 2005, pp:902-907 [Conf]
  248. Charles Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky
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    DATE, 2005, pp:908-913 [Conf]
  249. Hua Wang, Miguel Miranda, Wim Dehaene, Francky Catthoor, Karen Maex
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    DATE, 2005, pp:914-919 [Conf]
  250. Christophe Alexandre, Hugo Clément, Jean-Paul Chaput, Marek Sroka, Christian Masson, Remy Escassut
    TSUNAMI: An Integrated Timing-Driven Place And Route Research Platform. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:920-921 [Conf]
  251. Amitava Bhaduri, Ranga Vemuri
    Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:922-923 [Conf]
  252. Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy
    Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:926-931 [Conf]
  253. Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven
    Compositional Memory Systems for Multimedia Communicating Tasks. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:932-937 [Conf]
  254. Judita Kruse, Clive Thomsen, Rolf Ernst, Thomas Volling, Thomas Spengler
    Introducing Flexible Quantity Contracts into Distributed SoC and Embedded System Design Processes. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:938-943 [Conf]
  255. Mario R. Casu, Luca Macchiarulo
    A New System Design Methodology for Wire Pipelined SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:944-945 [Conf]
  256. Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
    A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:946-947 [Conf]
  257. Wolfgang Rosenstiel, Reinaldo A. Bergamaschi, Frank Ghenassia, Thorsten Groetker, Masamichi Kawarabayashi, Marinus C. van Lier, Albrecht Mayer, Mike Meredith, Mark Milligan, Stuart Swan
    Is there a Market for SystemC Tools? [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:950- [Conf]
  258. Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen
    Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:952-957 [Conf]
  259. Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif
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    DATE, 2005, pp:958-963 [Conf]
  260. Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang
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    DATE, 2005, pp:964-969 [Conf]
  261. Jinjun Xiong, King Ho Tam, Lei He
    Buffer Insertion Considering Process Variation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:970-975 [Conf]
  262. Baohua Wang, Pinaki Mazumder
    EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:976-981 [Conf]
  263. Cristiano Forzan, Davide Pandini
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    DATE, 2005, pp:982-983 [Conf]
  264. Ajith Chandy, Tom Chen
    Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:984-985 [Conf]
  265. Paul Zuber, Armin Windschiegl, Raúl Medina Beltán de Otálora, Walter Stechele, Andreas Herkersdorf
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    DATE, 2005, pp:986-987 [Conf]
  266. M. M. Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi
    Implicit and Exact Path Delay Fault Grading in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:990-995 [Conf]
  267. Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman
    Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:996-1001 [Conf]
  268. Kameshwar Chandrasekar, Michael S. Hsiao
    Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1002-1007 [Conf]
  269. Irith Pomeranz, Sudhakar M. Reddy
    The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1008-1013 [Conf]
  270. Raja K. K. R. Sandireddy, Vishwani D. Agrawal
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    DATE, 2005, pp:1014-1019 [Conf]
  271. Zaid Al-Ars, Said Hamdioui, Georg Mueller, A. J. van de Goor
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    DATE, 2005, pp:1020-1021 [Conf]
  272. Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre
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    DATE, 2005, pp:1022-1023 [Conf]
  273. Mahmut T. Kandemir, Feihui Li, Guilin Chen, Guangyu Chen, Ozcan Ozturk
    Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1026-1031 [Conf]
  274. Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin
    BB-GC: Basic-Block Level Garbage Collection. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1032-1037 [Conf]
  275. Jacques Combaz, Jean-Claude Fernandez, Thierry Lepley, Joseph Sifakis
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    DATE, 2005, pp:1038-1043 [Conf]
  276. Massimo Baleani, Alberto Ferrari, Leonardo Mangeruca, Alberto L. Sangiovanni-Vincentelli, Ulrich Freund, Erhard Schlenker, Hans-Jörg Wolff
    Correct-by-Construction Transformations across Design Environments for Model-Based Embedded Software Development. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1044-1049 [Conf]
  277. Elaine Cheong, Jie Liu
    galsC: A Language for Event-Driven Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1050-1055 [Conf]
  278. Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Compiler-Directed Instruction Duplication for Soft Error Detection. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1056-1057 [Conf]
  279. Tadashi Takeuchi
    OS Debugging Method Using a Lightweight Virtual Machine Monitor. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1058-1059 [Conf]
  280. Nikolaos Kavvadias, Spiridon Nikolaidis
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    DATE, 2005, pp:1060-1061 [Conf]
  281. Abhishek Somani, Partha Pratim Chakrabarti, Amit Patra
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    DATE, 2005, pp:1064-1069 [Conf]
  282. Tom Eeckelaert, Trent McConaghy, Georges G. E. Gielen
    Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1070-1075 [Conf]
  283. Gerd Vandersteen, Ludwig De Locht, Snezana Jenei, Yves Rolain, Rik Pintelon
    Estimating Scalable Common-Denominator Laplace-Domain MIMO Models in an Errors-in-Variables Framework. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1076-1081 [Conf]
  284. Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen
    CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1082-1087 [Conf]
  285. Mengmeng Ding, Ranga Vemuri
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    DATE, 2005, pp:1088-1089 [Conf]
  286. Nicolò Manaresi, Gianni Medoro, Melanie Abonnenc, Vincent Auger, Paul Vulto, Aldo Romani, Luigi Altomare, Marco Tartagni, Roberto Guerrieri
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    DATE, 2005, pp:1092-1093 [Conf]
  287. Malay K. Ganai, Aarti Gupta, Pranav Ashar
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    DATE, 2005, pp:1096-1101 [Conf]
  288. Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, Li-C. Wang, Kwang-Ting Cheng, Kuang-Chien Chen
    An Efficient Sequential SAT Solver With Improved Search Strategies. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1102-1107 [Conf]
  289. Zhaohui Fu, Yinlei Yu, Sharad Malik
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    DATE, 2005, pp:1108-1113 [Conf]
  290. Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin
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    DATE, 2005, pp:1116-1117 [Conf]
  291. Chung-Jr Lian, Yu-Wen Huang, Hung-Chi Fang, Yung-Chi Chang, Liang-Gee Chen
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    DATE, 2005, pp:1118-1119 [Conf]
  292. Cheng-Wen Wu
    SOC Testing Methodology and Practice. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1120-1121 [Conf]
  293. Ilia Polian, Alejandro Czutro, Bernd Becker
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    DATE, 2005, pp:1124-1129 [Conf]
  294. Kedarnath J. Balakrishnan, Nur A. Touba
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    DATE, 2005, pp:1130-1135 [Conf]
  295. Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy
    A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1136-1141 [Conf]
  296. Lei Li, Krishnendu Chakrabarty
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    DATE, 2005, pp:1142-1147 [Conf]
  297. Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
    C Compiler Retargeting Based on Instruction Semantics Models. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1150-1155 [Conf]
  298. Guilin Chen, Mahmut T. Kandemir, Mustafa Karaköy
    A Constraint Network Based Approach to Memory Layout Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1156-1161 [Conf]
  299. Mohammed Javed Absar, Francky Catthoor
    Compiler-Based Approach for Exploiting Scratch-Pad in Presence of Irregular Array Access. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1162-1167 [Conf]
  300. Elena Dubrova
    Structural Testing Based on Minimum Kernels. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1168-1173 [Conf]
  301. Srinivasan Murali, Giovanni De Micheli
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    DATE, 2005, pp:1176-1181 [Conf]
  302. Kees Goossens, John Dielissen, Om Prakash Gangwal, Santiago González Pestana, Andrei Radulescu, Edwin Rijpkema
    A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1182-1187 [Conf]
  303. Stergios Stergiou, Federico Angiolini, Salvatore Carta, Luigi Raffo, Davide Bertozzi, Giovanni De Micheli
    ast pipes Lite: A Synthesis Oriented Design Library For Networks on Chips. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1188-1193 [Conf]
  304. Fei Su, Krishnendu Chakrabarty, Vamsee K. Pamula
    Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1196-1201 [Conf]
  305. Fei Su, Krishnendu Chakrabarty
    Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1202-1207 [Conf]
  306. Dmitri Maslov, Christina Young, D. Michael Miller, Gerhard W. Dueck
    Quantum Circuit Simplification Using Templates. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1208-1213 [Conf]
  307. Kyosun Kim, Kaijie Wu, Ramesh Karri
    owards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1214-1219 [Conf]
  308. Roland Thewes, Christian Paulus, Meinrad Schienle, Franz Hofmann, Alexander Frey, Ralf Brederlow, M. Augustyniak, Martin Jenkner, Björn Eversmann, Petra Schindler-Bauer, Melanie Atzesberger, Birgit Holzapfl, Gottfried Beer, Thomas Haneder, Hans-Christian Hanke
    CMOS-Based Biosensor Arrays. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1222-1223 [Conf]
  309. Tobias Bjerregaard, Jens Sparsø
    A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1226-1231 [Conf]
  310. Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew Wingard
    A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1232-1237 [Conf]
  311. Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
    A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1238-1243 [Conf]
  312. Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
    ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1246-1251 [Conf]
  313. Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
    Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1252-1257 [Conf]
  314. Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie
    Reliability-Centric High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1258-1263 [Conf]
  315. Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Eugene Earlie
    PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1264-1269 [Conf]
  316. Sobeeh Almukhaizim, Yiorgos Makris
    Concurrent Error Detection in Asynchronous Burst-Mode Controllers. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1272-1277 [Conf]
  317. Cristiana Bolchini, Fabio Salice, Donatella Sciuto, Luigi Pomante
    Reliable System Specification for Self-Checking Data-Paths. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1278-1283 [Conf]
  318. Hamidreza Hashempour, Luca Schiano, Fabrizio Lombardi
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    DATE, 2005, pp:1284-1289 [Conf]
  319. Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda
    On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1290-1295 [Conf]
  320. Christian Jacobi 0002, Kai Weber, Viresh Paruthi, Jason Baumgartner
    Automatic Formal Verification of Fused-Multiply-Add FPUs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1298-1303 [Conf]
  321. Panagiotis Manolios, Sudarshan K. Srinivasan
    Refinement Maps for Efficient Verification of Processor Models. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1304-1309 [Conf]
  322. K. C. Shashidhar, Maurice Bruynooghe, Francky Catthoor, Gerda Janssens
    Functional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source Code. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1310-1315 [Conf]
  323. Brock J. LaMeres, Sunil P. Khatri
    Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1318-1323 [Conf]
  324. Zhuo Li, Weiping Shi
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    DATE, 2005, pp:1324-1329 [Conf]
  325. Xun Liu, Yuantao Peng, Marios C. Papaefthymiou
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    DATE, 2005, pp:1330-1335 [Conf]
  326. Raymond Campagnolo
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    DATE, 2005, pp:1338-1339 [Conf]
  327. Kay-Uwe Kirstein, Yue Li, Martin Zimmermann, Cyril Vancura, Tormod Volden, Wan Ho Song, Jan Lichtenberg, Andreas Hierlemann
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    DATE, 2005, pp:1340-1341 [Conf]
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