Conferences in DBLP
(ddecs) Ketan Paranjape Multi-Site Collaboration in System on Chip Design and Validation: The Intel Experience. [Citation Graph (0, 0)][DBLP ] Conf ] Jaume Segura CMOS Testing at the End of the Roadmap: Challenges and Opportunities. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre-André Mudry , Guillaume Zufferey , Gianluca Tempesti An Hybrid Genetic Algorithm for Constrained Hardware-Software Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Ralf Wimmer , Marc Herbstritt , Bernd Becker Minimization of Large State Spaces using Symbolic Branching Bisimulation. [Citation Graph (0, 0)][DBLP ] Conf ] Jochen Eisinger , Ilia Polian , Bernd Becker , Alexander Metzner , Stephan Thesing , Reinhard Wilhelm Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Félix Tobajas , Roberto Esper-Chaín , Raúl Regidor , O. Santana , R. Sarmiento A Low Power 2.5 Gbps 1: 32 Deserializer in SiGe BiCMOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Kristian Granhaug , Snorre Aunet Six Subthreshold Full Adder Cells Characterized in 90 nm CMOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Abid Rashid , Frank H. P. Fitzek , Ole Olsen , Morten Gade , Yannick Le Moullec A Low Complexity, High Speed, Regular and Flexible Reed Solomon Decoder for Wireless Communication. [Citation Graph (0, 0)][DBLP ] Conf ] András Timár , Ábel Vámos , György Bognár Comprehensive Design of a High Frequency PLL Synthesizer for ZigBee Application. [Citation Graph (0, 0)][DBLP ] Conf ] Alex Ngouanga , Gilles Sassatelli , Lionel Torres , André Soares , Altamiro Amadeu Susin A Contextual Resources use: a Proof of Concept through the APACHES' Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Z. Stamenkovic , C. Wolf , G. Schoof , Jiri Gaisler LEON-2: General Purpose Processor for a Wireless Engine. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Sterpone , Massimo Violante ReCoM: A New Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Ari Kulmala , Erno Salminen , Olli Lehtoranta , Timo D. Hämäläinen , Marko Hännikäinen Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder. [Citation Graph (0, 0)][DBLP ] Conf ] Eero Aho , Jarno Vanne , Timo D. Hämäläinen Parallel Memory Architecture for Arbitrary Stride Accesses. [Citation Graph (0, 0)][DBLP ] Conf ] Grzegorz Pastuszak Architecture Design for the Context Formatter in the H.264/AVC Encoder. [Citation Graph (0, 0)][DBLP ] Conf ] Lukas Ruckay Recognition of DRM Signal in Frequency Domain and Hardware Demands. [Citation Graph (0, 0)][DBLP ] Conf ] V. V. Belkin , S. G. Sharshunov ISA Based Functional Test Generation with Application to Self-Test of RISC Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Youssef Serrestou , Vincent Beroulle , Chantal Robach How to Improve a Set of Design Validation Data by Using Mutation-based Test. [Citation Graph (0, 0)][DBLP ] Conf ] Jiri Kadlec , Martin Danek Design and Verification Methodology for Reconfigurable Designs in Atmel FPSLIC. [Citation Graph (0, 0)][DBLP ] Conf ] György Bognár , Gyula Horváth , Zoltán Szucs , Vladimir Székely Die Attach Quality Testing by Fully Contact-less Measurement Method. [Citation Graph (0, 0)][DBLP ] Conf ] Tomás Martínek , Jan Korenek , Otto Fucík , Matej Lexa A Flexible Technique for the Automatic Design of Approximate String Matching Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Lukás Sekanina , Lukás Starecek , Zdenek Kotásek Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Harri Lampinen , Pauli Perälä , Olli Vainio Design of a Scalable Asynchronous Dataflow Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Guoyan Zhang , Ronan Farrell Embedded Built-In-Test Detection Circuit for Radio Frequency Systems and Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jarosla Skarvada Test Scheduling for SoC under Power Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Johannes Goplen Lomsdalen , Renè Jensen , Yngvar Berg Self-refreshing Multiple Valued Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Jiri Bucek , Robert Lorencz Comparing Subtraction-Free and Traditional AMI. [Citation Graph (0, 0)][DBLP ] Conf ] Pavel Kubalík , Radek Dobias , Hana Kubatova Dependability Computation for Fault Tolerant Reconfigurable Duplex System. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Chang Hsia , Wen-Ching Lee A New 6-bit Flash A/D Converter Using Novel Two-Step Structure. [Citation Graph (0, 0)][DBLP ] Conf ] Ondrej Subrt , Pravoslav Martínek A Novel Design Evaluation Concept Applied to Switched-Current Algorithmic A/D Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Yves Joannon , Vincent Beroulle , Rami Khouri , Chantal Robach , Smail Tedjini , Jean-Louis Carbonéro Behavioral Modeling of WCDMA Transceiver with VHDL-AMS Language. [Citation Graph (0, 0)][DBLP ] Conf ] Manuel J. Barragan Asian , Diego Vázquez , Adoración Rueda A Sinewave Analyzer for Mixed-Signal BIST Applications in a 0.35µm Technology. [Citation Graph (0, 0)][DBLP ] Conf ] L. Balado , E. Lupon , L. García , Rosa Rodríguez-Montañés , Joan Figueras Lissajous Based Mixed-Signal Testing for N-Observable Signals. [Citation Graph (0, 0)][DBLP ] Conf ] P. Malosek , Viera Stopjaková PCA Data Preprocessing for Neural Network-based Detection of Parametric Defects in Analog IC. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Vock , Ulrich Flogaus , Hans Martin von Staudt Productivity and Code Quality Improvement of Mixed-Signal Test Software by Applying Software Engineering Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Régis Leveugle , V. Maingot On the Use of Information Redundancy When Designing Secure Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Reouven Elbaz , Lionel Torres , Gilles Sassatelli , Pierre Guillemin , Michel Bardouillet PE-ICE: Parallelized Encryption and Integrity Checking Engine. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Novotný , Jan Schmidt Normal Basis Multipliers of General Digit Width Applicable in Elliptic Curve Cryptography. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed Abbas , Makoto Ikeda , Kunihiro Asada Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow. [Citation Graph (0, 0)][DBLP ] Conf ] Aki Penttinen , Rafal Jastrzebski , Riku Pölläanen , Olli Pyrhönen Run-Time Debugging and Monitoring of FPGA Circuits Using Embedded Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Geguang Pu , Jifeng He , Zongyan Qiu An Optimal Lower-Bound Algorithm for the High-Level Synthesis Scheduling Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Piotr Dziurzanski , W. Bielecki , Konrad Trifunovic , M. Kleszczonek A System for Transforming an ANSI C Code with OpenMP Directives into a SystemC Description. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Armengaud Low Level Bus Traffic Replay for the Test and Debugging of Time-Triggered Communication Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Alfredo Benso , Alberto Bosio , Stefano Di Carlo , Giorgio Di Natale , Paolo Prinetto A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] René Kothe , Christian Galke , S. Schultke , H. Froeschke , S. Gaede , Heinrich Theodor Vierhaus Hardware/Software Based Hierarchical Self Test for SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Josef Strnadel Power-Constrained, Sessionless SoC Test Scheduling Based on Exploration of I-Schedule State-Space. [Citation Graph (0, 0)][DBLP ] Conf ] Xuan-Tu Tran , Vincent Beroulle , Jean Durupt , Chantal Robach , François Bertrand Design-for-Test of Asynchronous Networks-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Cecilia Metra , Daniele Rossi , Martin Omaña , José Manuel Cazeaux , T. M. Mak Can Clock Faults be Detected Through Functional Test? [Citation Graph (0, 0)][DBLP ] Conf ] André V. Fidalgo , Gustavo R. Alves , José M. Ferreira A Modified Debugging Infrastructure to Assist Real Time Fault Injection Campaigns. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Krasniewski Low-Cost Concurrent Error Detection for FSMs Implemented Using Embedded Memory Blocks of FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Heikki Kariniemi , Jari Nurmi Fault-Tolerant 2-D Mesh Network-on-Chip for Multi-Processor System-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre Vanhauwaert , Régis Leveugle , Philippe Roche A Flexible SoPC-based Fault Injection Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Gilson I. Wirth , Michele G. Vieira , Egas Henes Neto , Fernanda Gusmão de Lima Kastensmidt Generation and Propagation of Single Event Transients in CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] S. Biswas , S. Mukhopadhyay , P. Patra , D. Sarkar Concurrent Testing of Digital Circuits for Advanced Fault Models. [Citation Graph (0, 0)][DBLP ] Conf ] René Kothe , Heinrich Theodor Vierhaus , Torsten Coym , Wolfgang Vermeiren , Bernd Straube Embedded Self Repair by Transistor and Gate Level Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] José M. Fernandes , Marcelino B. Santos , Arlindo L. Oliveira , João C. Teixeira Probabilistic Testability Analysis and DFT Methods at RTL. [Citation Graph (0, 0)][DBLP ] Conf ] Mario García-Valderas , Marta Portela-García , Celia López-Ongil , Luis Entrena-Arrontes An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories. [Citation Graph (0, 0)][DBLP ] Conf ] S. V. Yarmolik , B. Sokol Optimal Memory Address Seeds for Pattern Sensitive Faults Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Jirí Jaros , Václav Dvorák Evolutionary Design of OAB and AAB Communication Schedules for Networking Systems on Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Milos Ohlídal , Josef Schwarz Collective Communication AAB for Regular and Irregular Topology Based on Prediction of Conflicts. [Citation Graph (0, 0)][DBLP ] Conf ] Hsin-Chou Chi , Chia-Ming Wu , Sung-Tze Wu A Switch Supporting Circuit and Packet Switching for On-Chip Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Simlastík , Peter Malík , Tomás Pikula , Marcel Baláz FPGA Implementation of a Fast MDCT Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Tomasz Garbolino , Michal Kopec , Krzysztof Gucwa , Andrzej Hlawiczka Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Bernardi , Michelangelo Grosso Test Considerations about the Structured ASIC Paradigm. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Bucci , Raimondo Luzzi A Leakage-based Random Bit Generator with On-line Fault Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Vladislav Nagy , Viera Stopjaková New Current Monitor Using Auto Zero Voltage Comparator for IDD Testing of Mixed-signal Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Zbysek Gajda A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Zbynek Mader , Michal Jarkovský SOC Diagnostic Design Using RESPIN Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Younggap You , Yong-Dae Kim , Jong Hwa Choi Dynamic Decimal Adder Circuit Design by using the Carry Lookahead. [Citation Graph (0, 0)][DBLP ] Conf ] Johannes Goplen Lomsdalen , Renè Jensen , Yngvar Berg Multiple Valued Counter. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Stáva , Ondrej Novák HW Implementation of the Backtrace Algorithm with Conflict-Driven Dynamic Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] Gergely Perlaky , Gábor Mezösi , Imre Zolomy Sensor Powering with Integrated MOS Compatible Solar Cell Array. [Citation Graph (0, 0)][DBLP ] Conf ] Luigi Dilillo , Patrick Girard , Serge Pravossoudovitch , Arnaud Virazel , Magali Bastian March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Gurgen Harutunyan , Valery A. Vardanian , Yervant Zorian Minimal March-Based Fault Location Algorithm with Partial Diagnosis for all Static Faults in Random Access Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Petr Fiser , Hana Kubatova Multiple-Vector Column-Matching BIST Design Method. [Citation Graph (0, 0)][DBLP ] Conf ] Leos Kafka , Ondrej Novák FPGA-based Fault Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] F. Guerreiro , Jorge Semião , A. Pierce , Marcelino B. Santos , I. M. Teixeira , João Paulo Teixeira Functional-Oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Tomas Pecenka , Zdenek Kotásek , Lukás Sekanina FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties. [Citation Graph (0, 0)][DBLP ] Conf ] 