Conferences in DBLP
Committees. [Citation Graph (0, 0)][DBLP ] Conf ] Title Page. [Citation Graph (0, 0)][DBLP ] Conf ] Message from the Symposium Chairs. [Citation Graph (0, 0)][DBLP ] Conf ] Copyright. [Citation Graph (0, 0)][DBLP ] Conf ] Mehdi Baradaran Tahoori Defects, Yield, and Design in Sublithographic Nano-electronics. [Citation Graph (0, 0)][DBLP ] Conf ] Zhaojun Wo , Israel Koren , Maciej J. Ciesielski An ILP Formulation for Yield-driven Architectural Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Xingguo Xiong , Yu-Liang Wu , Wen-Ben Jone Design and Analysis of Self-Repairable MEMS Accelerometer. [Citation Graph (0, 0)][DBLP ] Conf ] Jinkyu Lee , Nur A. Touba Low Power BIST Based on Scan Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Samuel I. Ward , Chris Schattauer , Nur A. Touba Using Statistical Transformations to Improve Compression for Linear Decompressors. [Citation Graph (0, 0)][DBLP ] Conf ] Jeremy Lee , Mohammad Tehranipoor , Chintan Patel , Jim Plusquellic Securing Scan Design Using Lock and Key Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Masaru Fukushi , Yusuke Fukushima , Susumu Horiguchi A Genetic Approach for the Reconfiguration of Degradable Processor Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Breveglieri , Israel Koren , Paolo Maistri Incorporating Error Detection and Online Reconfiguration into a Regular Architecture for the Advanced Encryption Standard. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Lung Su , Yi-Ting Yeh , Cheng-Wen Wu An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement. [Citation Graph (0, 0)][DBLP ] Conf ] Haruhiko Kaneko Error Control Coding for Semiconductor Memory Systems in the Space Radiation Environment. [Citation Graph (0, 0)][DBLP ] Conf ] S. Bayat-Sarmadi , M. Anwar Hasan Concurrent Error Detection of Polynomial Basis Multiplication over Extension Fields using a Multiple-bit Parity Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Gian-Carlo Cardarilli , Salvatore Pontarelli , Marco Re , Adelio Salsano A Self Checking Reed Solomon Encoder: Design and Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Jien-Chung Lo , Yu-Lun Wan , Eiji Fujiwara Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes. [Citation Graph (0, 0)][DBLP ] Conf ] B. Saillet , Jean Michel Portal , Didier Née Flash Memory Cell: Parametric Test Data Reconstruction for Process Monitoring. [Citation Graph (0, 0)][DBLP ] Conf ] Cory Jung , Mohammad Hadi Izadi , Michelle L. La Haye Noise Analysis of Fault Tolerant Active Pixel Sensors. [Citation Graph (0, 0)][DBLP ] Conf ] Glenn H. Chapman , Israel Koren , Zahava Koren , Jozsef Dudas , Cory Jung On-Line Identification of Faults in Fault-Tolerant Imagers. [Citation Graph (0, 0)][DBLP ] Conf ] Glenn H. Chapman , Vijay K. Jain , Shekhar Bhansali Inter-Plane Via Defect Detection Using the Sensor Plane in 3-D Heterogeneous Sensor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Cecilia Metra , Martin Omaña , Daniele Rossi , José Manuel Cazeaux , T. M. Mak The Other Side of the Timing Equation: a Result of Clock Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Lei Wu , D. M. H. Walker A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Nisar Ahmed , Mohammad Tehranipoor Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Mariam Momenzadeh , Jing Huang , Fabrizio Lombardi Defect Characterization and Tolerance of QCA Sequential Devices and Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Mariam Momenzadeh , Marco Ottavi , Fabrizio Lombardi Modeling QCA Defects at Molecular-level in Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Zachary D. Patitz , Nohpill Park , Minsu Choi , Fred J. Meyer QCA-Based Majority Gate Design under Radius of Effect-Induced Faults. [Citation Graph (0, 0)][DBLP ] Conf ] David M. Horan , Richard A. Guinee A Novel Pulse Echo Correlation Tool for Transmission Path Testing and Fault Finding using Pseudorandom Binary Sequences. [Citation Graph (0, 0)][DBLP ] Conf ] Cristian Grecu , Partha Pratim Pande , Baosheng Wang , André Ivanov , Res Saleh Methodologies and Algorithms for Testing Switch-Based NoC Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto Gomez , Alejandro Giron , Víctor H. Champac Test of Interconnection Opens Considering Coupling Signals. [Citation Graph (0, 0)][DBLP ] Conf ] Gian-Carlo Cardarilli , Salvatore Pontarelli , Marco Re , Adelio Salsano FPGA oriented design of parity sharing RS codecs. [Citation Graph (0, 0)][DBLP ] Conf ] Mahdi Fazeli , Reza Farivar , Seyed Ghassem Miremadi A Software-Based Concurrent Error Detection Technique for PowerPC Processor-based Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] G. Cellere , A. Paccagnella , A. Visconti , M. Bonanomi Soft Errors induced by single heavy ions in Floating Gate memory arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Kyung Ki Kim , Jing Huang , Yong-Bin Kim , Fabrizio Lombardi On the Modeling and Analysis of Jitter in ATE Using Matlab. [Citation Graph (0, 0)][DBLP ] Conf ] Kyung Ki Kim , Yong-Bin Kim , Fabrizio Lombardi Data Dependent Jitter (DDJ) Characterization Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad Tehranipoor Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Schüler , Luigi Carro Reliable Digital Circuits Design using Sigma-Delta Modulated Signals. [Citation Graph (0, 0)][DBLP ] Conf ] D. P. Vasudevan , Parag K. Lala A Technique for Modular Design of Self-Checking Carry-Select Adder. [Citation Graph (0, 0)][DBLP ] Conf ] Cristiana Bolchini , Antonio Miele , Fabio Salice , Donatella Sciuto A model of soft error effects in generic IP processors. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Ostrovsky , Ilya Levin Implementation of Concurrent Checking Circuits by Independent Sub-circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Daniele Rossi , Martin Omaña , Fabio Toma , Cecilia Metra Multiple Transient Faults in Logic: An Issue for Next Generation ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Fang Yu , Chung-Hung Tsai , Yao-Wen Huang , D. T. Lee , Hung-Yau Lin , Sy-Yen Kuo Efficient Exact Spare Allocation via Boolean Satisfiability. [Citation Graph (0, 0)][DBLP ] Conf ] Jia Di , Parag K. Lala , D. P. Vasudevan On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Bhushan Vaidya , Mehdi Baradaran Tahoori Delay Test Generation with All Reachable Output Propagation and Multiple Excitations. [Citation Graph (0, 0)][DBLP ] Conf ] Pedram A. Riahi , Zainalabedin Navabi , Fabrizio Lombardi Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Zhuo Zhang , Sudhakar M. Reddy , Irith Pomeranz On Generating Pseudo-Functional Delay Fault Tests for Scan Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmad A. Al-Yamani , Narendra Devta-Prasanna , Arun Gunda Should Illinois-Scan Based Architectures be Centralized or Distributed? [Citation Graph (0, 0)][DBLP ] Conf ] Leonard Lee , Sean Wu , Charles H.-P. Wen , Li-C. Wang On Generating Tests to Cover Diverse Worst-Case Timing Corners. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Zhang 0002 Computing Cache Vulnerability to Transient Errors and Its Implication. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Sterpone , Massimo Violante A design flow for protecting FPGA-based systems against single event upsets. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Bernardi , Leticia Maria Veiras Bolzani , Maurizio Rebaudengo , Matteo Sonza Reorda , Massimo Violante An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors. [Citation Graph (0, 0)][DBLP ] Conf ] Jeetendra Kumar , Mehdi Baradaran Tahoori A Low Power Soft Error Suppression Technique for Dynamic Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Hossein Asadi , Mehdi Baradaran Tahoori Soft Error Modeling and Protection for Sequential Elements. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Recovery During Concurrent On-Line Testing of Identical Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Song Peng , Rajit Manohar Efficient Failure Detection in Pipelined Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ernesto Sánchez , Matteo Sonza Reorda , Giovanni Squillero On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Masato Kitakami , Manabu Sueishi Fault-Tolerant Wormhole Switching with Backtracking Capability. [Citation Graph (0, 0)][DBLP ] Conf ] Hyukjune Chung , Antonio Ortega Analysis and Testing for Error Tolerant Motion Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] In Suk Chong , Antonio Ortega Hardware Testing For Error Tolerant Multimedia Compression based on Linear Transforms. [Citation Graph (0, 0)][DBLP ] Conf ] Miltiadis Hatzimihail , Mihalis Psarakis , George Xenoulis , Dimitris Gizopoulos , Antonis M. Paschalis Software-Based Self-Test for Pipelined Processors: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Enkelejda Tafaj , Paul M. Rosinger , Bashir M. Al-Hashimi , Krishnendu Chakrabarty Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling. [Citation Graph (0, 0)][DBLP ] Conf ] Chunsheng Liu , Kugesh Veeraraghavant , Vikram Iyengar Thermal-Aware Test Scheduling and Hot Spot Temperature Minimization for Core-Based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Shaolei Quan , Meng-Yao Liu , Chin-Long Wey Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress. [Citation Graph (0, 0)][DBLP ] Conf ] Yukiya Miura Characteristics of Fault Diagnosis for Analog Circuits Based on Preset Test. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Wieckowski , John Liobe , Quentin Diduck , Martin Margala A New Test Methodology For DNL Error In Flash ADC's. [Citation Graph (0, 0)][DBLP ] Conf ] Sadeka Ali , Gregory Briggs , Martin Margala A High Frequency, Low Jitter Auto-Calibration Phase-Locked Loop with Built-in-Self-Test. [Citation Graph (0, 0)][DBLP ] Conf ] 