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Conferences in DBLP

Defect and Fault Tolerance in VLSI Systems (dft)
1993 (conf/dft/1993)

  1. A. Dell'Acqua, M. Hansen, S. Inkinen, B. Lofstedt, J. P. Vanuxem, Christer Svensson, Jiren Yuan, H. Hentzell, L. Del Buono, J. David, J. F. Genat, H. Lebbolo, O. LeDortz, P. Nayman, A. Savoy-Navarro, R. Zitoun, Cesare Alippi, Luca Breveglieri, Luigi Dadda, Vincenzo Piuri, Fabio Salice, Mariagiovanna Sami, Renato Stefanelli, P. Cattaneo, G. Fumagalli, G. Goggi, S. Brigati, Umberto Gatti, Franco Maloberti, Guido Torelli, P. Carlson, A. Kerek, Goran Appelquist, S. Berglund, C. Bohm, Magnus Engström, N. Yamdagni, Rolf Sundblad, I. Höglund, S. T. Persson
    System Level Policies for Fault Tolerance Issues in the FERMI Project. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:1-8 [Conf]
  2. R. Rochet, Régis Leveugle, Gabriele Saucier
    Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC Codes. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:9-16 [Conf]
  3. Liangkung Lin, G. Robert Redinbo
    Block Implementation of Fault-Tolerant LMS Adaptive FIR Filters. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:17-24 [Conf]
  4. Hee Yong Youn, Kyung Ook Lee
    Fault-Tolerant Sorting Using VLSI Processor Arrays. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:25-32 [Conf]
  5. Gian-Carlo Cardarilli, M. Di Zenzo, Pat O. Pistilli, Adelio Salsano
    A High Speed Reed-Solomon Encoder-Decoder for Fault Tolerant Solid State Disks. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:33-40 [Conf]
  6. Lisa Guerra, Miodrag Potkonjak, Jan M. Rabaey
    High Level Synthesis Techniques for Efficient Built-In-Self Repair. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:41-48 [Conf]
  7. Hannu Kari, Heikki Saikkonen, Fabrizio Lombardi
    Detection of Defective Media in Disks. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:49-55 [Conf]
  8. Hussain Al-Asaad, Elias S. Manolakos
    A Two-Phase Reconfiguration Strategy for Extracting Linear Arrays Out of Two-Dimensional Architectures. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:56-63 [Conf]
  9. Chor Ping Low, Hon Wai Leong
    On the Reconfiguration of Degradable VLSI/WSI Arrays. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:64-71 [Conf]
  10. Chouki Aktouf, Chantal Robach, Guy Mazaré, J. Johansson
    Functional Testing and Reconfiguration of MIMD Machines. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:72-79 [Conf]
  11. Hideo Ito
    A Defect-Tolerant Design for WSI Interconnection Networks and Its Application to Hypercube. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:80-87 [Conf]
  12. José Salinas, Fabrizio Lombardi
    On the Reconfigurable Operation of Arrays with Defects for Image Processing. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:88-95 [Conf]
  13. A. Kerek
    Front-end Electronics in the Radiation Environment of LHC. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:96-100 [Conf]
  14. Víctor H. Champac, Antonio Rubio, Joan Figueras
    Analysis of the Floating Gate Defect in CMOS. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:101-108 [Conf]
  15. Antonio Casimiro, M. Simões, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS Designs. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:109-116 [Conf]
  16. Hua Xue, Chennian Di, Jochen A. G. Jess
    Fast Multi-Layer Critical Area Computation. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:117-124 [Conf]
  17. Enrico Ferrati, Magneti Marelli
    TEh Reliability of the Integrated Circuits in Automotive Industry. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:125-126 [Conf]
  18. Randall S. Collica
    A Logistic Regression Yield Model for SRAM Bit Fail Patterns. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:127-135 [Conf]
  19. Charles H. Stapper, J. A. Patrick, R. J. Rosner
    Yield Model for ASIC and Processor Chips. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:136-143 [Conf]
  20. J. Crépeau, Claude Thibeault, Yvon Savaria
    Some Results on Yield and Local Design Rule Relaxation. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:144-151 [Conf]
  21. Frederic Duvivier, M. Rivier, B. Burtschy, J. J. Charlot
    Use of a Segmentation Technique to Analyze the Variability of the Yield of a Mature CMOS SRAM. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:152-158 [Conf]
  22. Zahava Koren, Israel Koren
    Does the Floorplan of a Chip Affect Its Yield? [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:159-166 [Conf]
  23. Israel A. Wagner, Israel Koren
    An Interactive Yield Estimator as a VLSI CAD Tool. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:167-174 [Conf]
  24. Venkat K. R. Chiluvuri, Israel Koren
    Topological Optimization of PLAs for Yield Enhancement. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:175-182 [Conf]
  25. Eiji Fujiwara, Masaharu Tanaka
    A Defect-Tolerant WSI File Memory System Using Address Permutation Scheme for Spare Allocation. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:183-190 [Conf]
  26. Giacomo Buonanno, Franco Fummi, Donatella Sciuto
    Fault Detection in Sequential Circuits through Functional Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:191-198 [Conf]
  27. M. Rullán, F. C. Blom, J. Oliver, C. Ferrer
    Layout Level Design for Testability Strategy Applied to a CMOS Cell Library. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:199-206 [Conf]
  28. Michel Renovell, Joan Figueras
    Current Testing Viability in Dynamic CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:207-214 [Conf]
  29. David Wessels, Jon C. Muzio
    Probabilistic Identification of Critical Components for Circuit Delays. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:215-222 [Conf]
  30. Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza
    Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:223-230 [Conf]
  31. Graham Frearson
    The T9000 Transputer: A Practical Example of the Application of Standard Test Techniques. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:231-238 [Conf]
  32. Egor S. Sogomonyan, Michael Gössel
    Design of Self-Parity Combinational Circuits for Self-testing and On-line Detection. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:239-246 [Conf]
  33. Xiaoling Sun, Micaela Serra
    Design and Implementation of a Merged On-Line and Off-Line Self Textable Architecture. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:247-254 [Conf]
  34. Dah-Yea Wei, Jung Hwan Kim, T. R. N. Rao
    Complete Tests in Algorithm-Based Fault-Tolerant Matrix Operations on Processor Arrays. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:255-262 [Conf]
  35. Jien-Chung Lo, Eiji Fujiwara
    A Probabilistic Measurement for Totally Self-Checking Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:263-270 [Conf]
  36. Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
    Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional Block. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:271-278 [Conf]
  37. Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò
    A Highly Testable 1-out-of-3 CMOS Checker. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:279-286 [Conf]
  38. Yuang-Ming Hsu, Earl E. Swartzlander Jr.
    VLSI Concurrent Error Correcting Adders and Multipliers. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:287-294 [Conf]
  39. D. Taylor, P. S. A. Evans, D. Marland
    Functional Testing of Linear Circuits Using Transient Response Analysis. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:295-302 [Conf]
  40. Alessandra Fanni, Alessandro Giua, Enrico Sandoli
    Neural Networks for Multiple Fault Diagnosis in Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:303-310 [Conf]
  41. P. Nicolau, J. Barbosa, M. Saraiva, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Realistic Fault Analysis of CMOS Analog Building Blocks. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:311-318 [Conf]
  42. Manoj Sachdev
    Catastrophic Defects Oriented Testability Analysis of a Class AB Amplifier. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:319-326 [Conf]
  43. Nagendra Kumar, Philippe O. Pouliquen, Andreas G. Andreou
    Device Mismatch Limitations on the Performance of a Hamming Distance Classifier. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:327-334 [Conf]
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