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Conferences in DBLP

Defect and Fault Tolerance in VLSI Systems (dft)
2001 (conf/dft/2001)

  1. Israel Koren, Zahava Koren, Glenn H. Chapman
    Advanced Fault-Tolerance Techniques for a Color Digital Camera-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:3-10 [Conf]
  2. S. K. Tewksbury
    Challenges Facing Practical DFT for MEMS. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:11-17 [Conf]
  3. Yves Audet, Glenn H. Chapman
    Design of a Self-Correcting Active Pixel Sensor. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:18-0 [Conf]
  4. Thomas S. Barnett, Adit D. Singh, Victor P. Nelson
    Yield-Reliability Modeling for Fault Tolerant Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:29-38 [Conf]
  5. Neil Harrison
    A Simple via Duplication Tool for Yield Enhancement. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:39-47 [Conf]
  6. Tianxu Zhao, Yue Hao, Peijun Ma, Taifeng Chen
    Relation between Reliability and Yield of IC's Based on Discrete Defect Distribution Model. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:48-0 [Conf]
  7. Hans A. R. Manhaeve, Stefaan Kerckenaere
    An On-Chip Detection Circuit for the Verification of IC Supply Connections. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:57-65 [Conf]
  8. Parag K. Lala, Alvernon Walker
    On-Line Error Detectable Carry-Free Adder Design. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:66-71 [Conf]
  9. Shugang Wei, Kensuke Shimizu
    Error Detection of Arithmetic Circuits Using a Residue Checker with Signed-Digit Number System. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:72-77 [Conf]
  10. Tat Ngai, Earl E. Swartzlander Jr., Chen He
    Enhanced Concurrent Error Correcting Arithmetic Unit Design Using Alternating Logic. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:78-83 [Conf]
  11. Régis Leveugle, R. Cercueil
    High Level Modifications of VHDL Descriptions for On-Line Test or Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:84-0 [Conf]
  12. J. H. Jiang, Shih-Chieh Chang, Wen-Ben Jone
    Embedded Core Testing Using Broadcast Test Architecture. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:95-103 [Conf]
  13. Janusz Sosnowski
    Analyzing BIST Robustness. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:104-109 [Conf]
  14. Ondrej Novák, Jiri Nosek
    Test Pattern Decompression Using a Scan Chain. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:110-115 [Conf]
  15. Xiaowei Li, Huawei Li, Yinghua Min
    Reducing Power Dissipation during At-Speed Test Application. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:116-0 [Conf]
  16. Shu-Yi Yu, Edward J. McCluskey
    Permanent Fault Repair for FPGAs with Limited Redundant Area. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:125-133 [Conf]
  17. Itsuo Takanami
    Built-in Self-Reconfiguring Systems for Fault Tolerant Mesh-Connected Processor Arrays by Direct Spare Replacement. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:134-142 [Conf]
  18. Nobuo Tsuda
    ABL-Tree: A Constant Diameter Interconnection Network for Reconfigurable Processor Arrays Capable of Distributed Communication . [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:143-148 [Conf]
  19. John M. Emmert, Jason A. Cheatham
    On-Line Incremental Routing for Interconnect Fault Tolerance in FPGAs Minus the Router . [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:149-0 [Conf]
  20. Xiao-Tao Chen, Wei-Kang Huang, Nohpill Park, Fred J. Meyer, Fabrizio Lombardi
    Novel Approaches for Fault Detection in Two-Dimensional Combinational Arrays. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:161-169 [Conf]
  21. Cristiana Bolchini, Fabio Salice
    A Software Methodology for Detecting Hardware Faults in VLIW Data Paths. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:170-175 [Conf]
  22. Seok-Bum Ko, Tian Xia, Jien-Chung Lo
    Efficient Parity Prediction in FPGA. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:176-181 [Conf]
  23. Nahmsuk Oh, Edward J. McCluskey
    Procedure Call Duplication: Minimization of Energy Consumption with Constrained Error Detection Latency. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:182-0 [Conf]
  24. Monica Alderighi, Fabio Casini, Sergio D'Angelo, Davide Salvi, Giacomo R. Sechi
    A Fault-Tolerance Strategy for an FPGA-Based Multi-stage Interconnection Network in a Multi-sensor System for Space Application. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:191-199 [Conf]
  25. Kaijie Wu, Ramesh Karri
    Idle Cycles Based Concurrent Error Detection of RC6 Encryption. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:200-205 [Conf]
  26. Wei-Je Huang, Subhasish Mitra, Edward J. McCluskey
    Fast Run-Time Fault Location in Dependable FPGA-Based Applications. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:206-214 [Conf]
  27. Jayabrata Ghosh-Dastidar, Nur A. Touba
    Improving Diagnostic Resolution of Delay Faults in FPGAs by Exploiting Reconfigurability. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:215-220 [Conf]
  28. Xiaoling Sun, Jian Xu, Pieter M. Trouborst
    Testing Xilinx XC4000 Configurable Logic Blocks with Carry Logic Modules. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:221-0 [Conf]
  29. J. Gracia, J. C. Baraza, Daniel Gil, Pedro J. Gil
    Comparison and Application of Different VHDL-Based Fault Injection Techniques. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:233-241 [Conf]
  30. Régis Leveugle
    A Low-Cost Hardware Approach to Dependability Validation of Ips. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:242-249 [Conf]
  31. Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:250-258 [Conf]
  32. Raoul Velazco, Régis Leveugle, O. Calvo
    Upset-Like Fault Injection in VHDL Descriptions: A Method and Preliminary Results. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:259-0 [Conf]
  33. Farzin Karimi, Fabrizio Lombardi
    Parallel Testing of Multi-port Static Random Access Memories for BIST. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:271-279 [Conf]
  34. Paul Lee, Alfred Chen, Dilip Mathew
    A Speed-Dependent Approach for Delta IDDQ Implementation. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:280-286 [Conf]
  35. Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada
    Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:287-0 [Conf]
  36. Kazuteru Namba, Eiji Fujiwara
    Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:299-307 [Conf]
  37. Amir Kazéminéjad, Eric Belhaire
    Fast, Minimal Decoding Complexity, System Level, Binary Systematic (41, 32) Single-Error-Correcting Codes for On-Chip DRAM Applications. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:308-313 [Conf]
  38. Stanislaw J. Piestrak, Abbas Dandache, Fabrice Monteiro
    Design of Fault-Secure Encoders for a Class of Systematic Error Correcting Codes. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:314-0 [Conf]
  39. Xiangdong Xuan, Abhijit Chatterjee
    Sensitivity and Reliability Evaluation for Mixed-Signal ICs under Electromigration and Hot-Carrier Effects. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:323-328 [Conf]
  40. Alvernon Walker
    A Step Response Based Mixed-Signal BIST Approach . [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:329-337 [Conf]
  41. Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell
    Analog BIST Generator for ADC Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:338-346 [Conf]
  42. Mandeep Singh, Israel Koren
    Reliability Enhancement of Analog-to-Digital Converters (ADCs). [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:347-0 [Conf]
  43. Cecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak
    Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:357-365 [Conf]
  44. Pradeep Nagaraj, Shambhu Upadhaya, Kamran Zarrineh, R. Dean Adams
    Defect Analysis and a New Fault Model for Multi-port SRAMs. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:366-374 [Conf]
  45. Mykola Blyzniuk, Irena Kazymyra
    Development of the Special Software Tools for the Defect/Fault Analysis in the Complex Gates from Standard Cell Library. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:375-383 [Conf]
  46. Witold A. Pleskacz, Dominik Kasprowicz, Tomasz Oleszczak, Wieslaw Kuzmicz
    CMOS Standard Cells Characterization for Defect Based Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:384-0 [Conf]
  47. A. Matrosova, Sergey Ostanin, Ilya Levin
    Survivable Self-Checking Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:395-402 [Conf]
  48. Marco Ottavi, Gian-Carlo Cardarilli, D. Cellitti, Salvatore Pontarelli, Marco Re, Adelio Salsano
    Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:403-411 [Conf]
  49. Eleftherios Kolonis, Michael Nicolaidis
    Fail-Safe Synchronization Circuit for Duplicated Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:412-417 [Conf]
  50. Andreas Steininger, Christoph Scherrer
    How to Tune the MTTF of a Fail-Silent System. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:418-0 [Conf]
  51. Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim
    Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:427-435 [Conf]
  52. Naotake Kamiura, Masashi Tomita, Teijiro Isokawa, Nobuyuki Matsui
    On Variable-Shift-Based Fault Compensation of Fuzzy Controllers. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:436-444 [Conf]
  53. John M. Emmert, Stanley Baumgart, Pankaj Kataria, Andrew M. Taylor, Charles E. Stroud, Miron Abramovici
    On-Line Fault Tolerance for FPGA Interconnect with Roving STARs. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:445-454 [Conf]
  54. Salvatore Pontarelli, Gian-Carlo Cardarilli, A. Malvoni, Marco Ottavi, Marco Re, Adelio Salsano
    System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:455-460 [Conf]
  55. Ahmad A. Al-Yamani, Nahmsuk Oh, Edward J. McCluskey
    Performance Evaluation of Checksum-Based ABFT. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:461-0 [Conf]
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002