Conferences in DBLP
Witold A. Pleskacz , Wojciech Maly Improved Yield Model for Submicron Domain. [Citation Graph (0, 0)][DBLP ] Conf ] Sandra Levasseur , Frederic Duvivier Application of a yield model merging critical areas and defectivity to industrial products. [Citation Graph (0, 0)][DBLP ] Conf ] Gerard A. Allan , Anthony J. Walton Efficient critical area estimation for arbitrary defect shapes. [Citation Graph (0, 0)][DBLP ] Conf ] Fernando M. Gonçalves , Isabel C. Teixeira , João Paulo Teixeira Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Zhan Chen , Israel Koren Crosstalk Minimization in Three-Layer HVH Channel Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Pascal Bichebois , Pierre Mathery Analysis of Defect to Yield Correlation on Memories: Method, Algorithms and Limits. [Citation Graph (0, 0)][DBLP ] Conf ] Anil Gandhi , Stacy Hall , Ron Harris An examination of empirically derived within-die local probabilities of failure. [Citation Graph (0, 0)][DBLP ] Conf ] Witold A. Pleskacz , Wojciech Maly , Hans T. Heineken Detection of Yield Trends. [Citation Graph (0, 0)][DBLP ] Conf ] Allan Y. Wong A Statistical Approach To Identify Semiconductor Process Equipment Related Yield Problems. [Citation Graph (0, 0)][DBLP ] Conf ] D. G. Ashen , Fred J. Meyer , Nohpill Park , Fabrizio Lombardi Testing of programmable logic devices (PLD) with faulty resources. [Citation Graph (0, 0)][DBLP ] Conf ] Fabrizio Ferrandi , Franco Fummi , Laura Pozzi , Mariagiovanna Sami Configuration-Specific Test Pattern Extraction for Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Chouki Aktouf , Ghassan Al Hayek , Chantal Robach Concurrent testing of VLSI digital signal processors using mutation based testing. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen J. Spinks , Chris D. Chalk , Ian M. Bell , Mark Zwolinski Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Yau Guo , Jien-Chung Lo , Cecilia Metra Fast and area-time efficient Berger code checkers. [Citation Graph (0, 0)][DBLP ] Conf ] Stanislaw J. Piestrak Design of encoders and self-testing checkers for some systematic unidirectional error detecting codes. [Citation Graph (0, 0)][DBLP ] Conf ] Xrysovalantis Kavousianos , Dimitris Nikolos , G. Sidiropoulos Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Cecilia Metra , Michele Favalli , Bruno Riccò Compact and low power on-line self-testing voting scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Kafrouni , Claude Thibeault , Yvon Savaria A Cost Model for VLSI / MCM Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Yves Gagnon , Yvon Savaria , Michel Meunier , Claude Thibeault Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model. [Citation Graph (0, 0)][DBLP ] Conf ] Israel Koren , Zahava Koren Analysis of a Hybrid Defect-Tolerance Scheme for High-Density Memory ICs. [Citation Graph (0, 0)][DBLP ] Conf ] John R. Samson Jr. , Wilfrido A. Moreno , Fernando J. Falquez Validating fault tolerant designs using laser fault injection (LFI). [Citation Graph (0, 0)][DBLP ] Conf ] Wei Liang Huang , Fred J. Meyer , Fabrizio Lombardi Multiple fault detection in logic resources of FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] X. Wendling , H. Chauvet , Lionel Revéret , R. Rochet , Régis Leveugle Automatic and Optimized Synthesis of Dataparts with Fault Detection or Tolerance Capabilities. [Citation Graph (0, 0)][DBLP ] Conf ] Cristiana Bolchini , Giacomo Buonanno , M. Cozzini , Donatella Sciuto , Renato Stefanelli Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Alfredo Benso , Paolo Prinetto , Maurizio Rebaudengo , Matteo Sonza Reorda , Jaan Raik , Raimund Ubar Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. [Citation Graph (0, 0)][DBLP ] Conf ] Itsuo Takanami , Tadayoshi Horita Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Nobuo Tsuda Fault-Tolerant Hierarchical Interconnection Networks Constructed by Additional Bypass Linking with Graph-Node Coloring. [Citation Graph (0, 0)][DBLP ] Conf ] Michele Favalli , Cecilia Metra Low-level error recovery mechanism for self-checking sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] W. Lynn Gallagher , Earl E. Swartzlander Jr. Fast Error-Correcting Newton-Raphson Dividers Using Time Shared TMR. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoling Sun , Wes Tutak Error Identification and Data Recovery in MISR-based Data Compaction. [Citation Graph (0, 0)][DBLP ] Conf ] F. Distante , Mariagiovanna Sami , Renato Stefanelli Harvesting Through Array Partitioning: A Solution to Achieve Defect Tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Alvernon Walker , Algernon P. Henry , Parag K. Lala An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher G. Knight , Adit D. Singh , Victor P. Nelson An IDDQ Sensor for Concurrent Timing Error Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Cristiana Bolchini , Donatella Sciuto , Fabio Salice Designing Networks with Error Detection Properties through the Fault-Error Relation. [Citation Graph (0, 0)][DBLP ] Conf ] Anna Antola , Vincenzo Piuri , Mariagiovanna Sami Semi-Concurrent Error Detection in Data Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Gössel , Sebastian T. J. Fenn , David Taylor On-line error detection for finite field multipliers. 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