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Conferences in DBLP

Defect and Fault Tolerance in VLSI Systems (dft)
1997 (conf/dft/1997)

  1. Witold A. Pleskacz, Wojciech Maly
    Improved Yield Model for Submicron Domain. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:2-10 [Conf]
  2. Sandra Levasseur, Frederic Duvivier
    Application of a yield model merging critical areas and defectivity to industrial products. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:11-19 [Conf]
  3. Gerard A. Allan, Anthony J. Walton
    Efficient critical area estimation for arbitrary defect shapes. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:20-28 [Conf]
  4. Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
    Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:29-37 [Conf]
  5. Zhan Chen, Israel Koren
    Crosstalk Minimization in Three-Layer HVH Channel Routing. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:38-43 [Conf]
  6. Pascal Bichebois, Pierre Mathery
    Analysis of Defect to Yield Correlation on Memories: Method, Algorithms and Limits. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:44-52 [Conf]
  7. Anil Gandhi, Stacy Hall, Ron Harris
    An examination of empirically derived within-die local probabilities of failure. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:53-61 [Conf]
  8. Witold A. Pleskacz, Wojciech Maly, Hans T. Heineken
    Detection of Yield Trends. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:62-68 [Conf]
  9. Allan Y. Wong
    A Statistical Approach To Identify Semiconductor Process Equipment Related Yield Problems. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:69-75 [Conf]
  10. D. G. Ashen, Fred J. Meyer, Nohpill Park, Fabrizio Lombardi
    Testing of programmable logic devices (PLD) with faulty resources. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:76-84 [Conf]
  11. Fabrizio Ferrandi, Franco Fummi, Laura Pozzi, Mariagiovanna Sami
    Configuration-Specific Test Pattern Extraction for Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:85-93 [Conf]
  12. Chouki Aktouf, Ghassan Al Hayek, Chantal Robach
    Concurrent testing of VLSI digital signal processors using mutation based testing. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:94-99 [Conf]
  13. Stephen J. Spinks, Chris D. Chalk, Ian M. Bell, Mark Zwolinski
    Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:100-109 [Conf]
  14. Yu-Yau Guo, Jien-Chung Lo, Cecilia Metra
    Fast and area-time efficient Berger code checkers. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:110-118 [Conf]
  15. Stanislaw J. Piestrak
    Design of encoders and self-testing checkers for some systematic unidirectional error detecting codes. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:119-127 [Conf]
  16. Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos
    Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n Codes. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:128-136 [Conf]
  17. Cecilia Metra, Michele Favalli, Bruno Riccò
    Compact and low power on-line self-testing voting scheme. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:137-147 [Conf]
  18. Michel Kafrouni, Claude Thibeault, Yvon Savaria
    A Cost Model for VLSI / MCM Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:148-156 [Conf]
  19. Yves Gagnon, Yvon Savaria, Michel Meunier, Claude Thibeault
    Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:157-165 [Conf]
  20. Israel Koren, Zahava Koren
    Analysis of a Hybrid Defect-Tolerance Scheme for High-Density Memory ICs. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:166-174 [Conf]
  21. John R. Samson Jr., Wilfrido A. Moreno, Fernando J. Falquez
    Validating fault tolerant designs using laser fault injection (LFI). [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:175-185 [Conf]
  22. Wei Liang Huang, Fred J. Meyer, Fabrizio Lombardi
    Multiple fault detection in logic resources of FPGAs. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:186-194 [Conf]
  23. X. Wendling, H. Chauvet, Lionel Revéret, R. Rochet, Régis Leveugle
    Automatic and Optimized Synthesis of Dataparts with Fault Detection or Tolerance Capabilities. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:195-203 [Conf]
  24. Cristiana Bolchini, Giacomo Buonanno, M. Cozzini, Donatella Sciuto, Renato Stefanelli
    Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:204-211 [Conf]
  25. Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar
    Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:212-217 [Conf]
  26. Itsuo Takanami, Tadayoshi Horita
    Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:218-226 [Conf]
  27. Nobuo Tsuda
    Fault-Tolerant Hierarchical Interconnection Networks Constructed by Additional Bypass Linking with Graph-Node Coloring. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:227-233 [Conf]
  28. Michele Favalli, Cecilia Metra
    Low-level error recovery mechanism for self-checking sequential circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:234-242 [Conf]
  29. W. Lynn Gallagher, Earl E. Swartzlander Jr.
    Fast Error-Correcting Newton-Raphson Dividers Using Time Shared TMR. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:243-251 [Conf]
  30. Xiaoling Sun, Wes Tutak
    Error Identification and Data Recovery in MISR-based Data Compaction. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:252-260 [Conf]
  31. F. Distante, Mariagiovanna Sami, Renato Stefanelli
    Harvesting Through Array Partitioning: A Solution to Achieve Defect Tolerance. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:261-271 [Conf]
  32. Alvernon Walker, Algernon P. Henry, Parag K. Lala
    An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:272-280 [Conf]
  33. Christopher G. Knight, Adit D. Singh, Victor P. Nelson
    An IDDQ Sensor for Concurrent Timing Error Detection. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:281-289 [Conf]
  34. Cristiana Bolchini, Donatella Sciuto, Fabio Salice
    Designing Networks with Error Detection Properties through the Fault-Error Relation. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:290-297 [Conf]
  35. Anna Antola, Vincenzo Piuri, Mariagiovanna Sami
    Semi-Concurrent Error Detection in Data Paths. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:298-306 [Conf]
  36. Michael Gössel, Sebastian T. J. Fenn, David Taylor
    On-line error detection for finite field multipliers. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:307-312 [Conf]
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