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Conferences in DBLP
- Pedram Khademsameni, Marek Syrzycki
Manufacturability Analysis of Analog CMOS ICs through Examination of Multiple Layout Solutions. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:3-11 [Conf]
- Arman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi
Effect of Static Power Dissipation in Burn-In Environment on Yield of VLSI. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:12-19 [Conf]
- B. M. Maziarz, V. K. Jain
Yield Estimates for the TESH Multicomputer Network. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:20-30 [Conf]
- Pierluigi Civera, Luca Macchiarulo, Massimo Violante
A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:31-39 [Conf]
- Hamidreza Hashempour, Yong-Bin Kim, Nohpill Park
A Test-Vector Generation Methodology for Crosstalk Noise Faults. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:40-50 [Conf]
- Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri
A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption Standard. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:51-59 [Conf]
- Cristiana Bolchini, Fabio Salice, Donatella Sciuto
Designing Self-Checking FPGAs through Error Detection Codes. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:60-68 [Conf]
- Jimson Mathew, Elena Dubrova
Self-Checking 1-out-of-n CMOS Current-Mode Checker. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:69-77 [Conf]
- Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan
Partially Duplicated Code-Disjoint Carry-Skip Adder. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:78-86 [Conf]
- Kartik Mohanram, Nur A. Touba
Input Ordering in Concurrent Checkers to Reduce Power Consumption. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:87-98 [Conf]
- Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis
New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:99-107 [Conf]
- Raoul Velazco, A. Corominas, P. Ferreyra
Injecting Bit Flip Faults by Means of a Purely Software Approach: A Case Studied. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:108-116 [Conf]
- Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang
Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:117-128 [Conf]
- Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
Scan Architecture for Shift and Capture Cycle Power Reduction. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:129-137 [Conf]
- Ranganathan Sankaralingam, Nur A. Touba
Inserting Test Points to Control Peak Power During Scan Testing. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:138-146 [Conf]
- Ching-Hwa Cheng
Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino Circuits. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:147-158 [Conf]
- Kedarnath J. Balakrishnan, Nur A. Touba
Matrix-Based Test Vector Decompression Using an Embedded Processor. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:159-165 [Conf]
- Farzin Karimi, Waleed Meleis, Zainalabedin Navabi, Fabrizio Lombardi
Data Compression for System-on-Chip Testing Using ATE. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:166-176 [Conf]
- Jennifer Dworak, James Wingfield, Brad Cobb, Sooryong Lee, Li-C. Wang, M. Ray Mercer
Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:177-185 [Conf]
- Hamidreza Hashempour, Fred J. Meyer, Fabrizio Lombardi
Test Time Reduction in a Manufacturing Environment by Combining BIST and ATE. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:186-194 [Conf]
- Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey
Testing Digital Circuits with Constraints. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:195-206 [Conf]
- Cecilia Metra, Stefano Di Francescantonio, Giuseppe Marrale
On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:207-215 [Conf]
- Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:216-224 [Conf]
- Francisco Rodríguez, José Carlos Campelo, Juan José Serrano
A Memory Overhead valuation of the Interleaved Signature Instruction Stream. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:225-232 [Conf]
- Fabio Salice, Mariagiovanna Sami, Renato Stefanelli
Fault-Tolerant CAM Architectures: A Design Framework. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:233-244 [Conf]
- Lörinc Antoni, Régis Leveugle, Béla Fehér
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:245-253 [Conf]
- Sara Blanc, J. Gracia, Pedro J. Gil
A Fault Hypothesis Study on the TTP/C Using VHDL-Based and Pin-Level Fault Injection Techniques. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:254-262 [Conf]
- Matteo Sonza Reorda, Massimo Violante
Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:263-274 [Conf]
- Susumu Horiguchi, Yasuyuki Miura
Performance of Deadlock-Free Adaptive Routing for Hierarchical Interconnection Network TESH. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:275-283 [Conf]
- Xiaoling Sun, A. Alimohammad, Pieter M. Trouborst
Modeling of FPGA Local/Global Interconnect Resources and Derivation of Minimal Test Configurations. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:284-292 [Conf]
- Fabrizio Lombardi, Nohpill Park
Testing Layered Interconnection Networks. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:293-304 [Conf]
- Yuichi Hamamura, Kazunori Nemoto, Takaaki Kumazawa, Hisafumi Iwata, Kousuke Okuyama, Shiro Kamohara, Aritoshi Sugimoto
Repair Yield Simulation with Iterative Critical Area Analysis for Different Types of Failure. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:305-313 [Conf]
- Bing Qiu, Yvon Savaria, Meng Lu, Chunyan Wang, Claude Thibeault
Yield Modeling of a WSI Telecom Router Architecture. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:314-324 [Conf]
- Ozgur Sinanoglu, Alex Orailoglu
Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:325-333 [Conf]
- Dan Zhao, Shambhu J. Upadhyaya
Adaptive Test Scheduling in SoC's by Dynamic Partitioning. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:334-344 [Conf]
- Thomas Verdel, Yiorgos Makris
Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:345-353 [Conf]
- Stanislaw J. Piestrak
Feasibility Study of Designing TSC Sequential Circuits with 100% Fault Coverage. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:354-364 [Conf]
- A. Castelnuovo, Alessandro Fin, Franco Fummi, F. Sforza
Emulation-Based Design Errors Identification. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:365-371 [Conf]
- Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
A New Functional Fault Model for FPGA Application-Oriented Testing. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:372-380 [Conf]
- Sagar S. Sabade, D. M. H. Walker
Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:381-389 [Conf]
- Witold A. Pleskacz, Tomasz Borejko, Wieslaw Kuzmicz
CMOS Standard Cells Characterization for IDDQ Testing. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:390-398 [Conf]
- Tian Xia, Jien-Chung Lo
On-Chip Jitter Measurement for Phase Locked Loops. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:399-407 [Conf]
- Viera Stopjaková, D. Micusík, Lubica Benusková, Martin Margala
Neural Networks-Based Parametric Testing of Analog IC. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:408-418 [Conf]
- Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri
Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:419-427 [Conf]
- Y. Chang, Minsu Choi, Nohpill Park, Fabrizio Lombardi
Repairability Evaluation of Embedded Multiple Region DRAMs. [Citation Graph (0, 0)][DBLP]
DFT, 2002, pp:428-436 [Conf]
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