Conferences in DBLP
Adit D. Singh , David R. Lakin II , Gaurav Sinha , Phil Nigh Binning for IC Quality: Experimental Studies on the SEMATECH Data. [Citation Graph (0, 0)][DBLP ] Conf ] Leon J. P. Vogels , M. W. C. Dohmen , P. Van Duijvenboden , Robert A. Latimer , J. D. O. Heffernan A Yield Improvement Program Using Process Control and Process Optimization for Particle Reduction Using In Situ Particle Monitoring on a Semitool Magnum. [Citation Graph (0, 0)][DBLP ] Conf ] Sandrine Barberan , Frederic Duvivier Management of Critical Areas and Defectivity Data for Yield Trend Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Israel Koren , Zahava Koren Yield and Routing Objectives in Floorplanning. [Citation Graph (0, 0)][DBLP ] Conf ] Neil Harrison Orphan Metal Removal as an Element of DFM. [Citation Graph (0, 0)][DBLP ] Conf ] Gerard A. Allan A Comparison of Efficient Dot Throwing and Shape Shifting Extra Material Critical Area Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Zhan Chen , Fook-Luen Heng A Fast Minimum Layout Perturbation Algorithm for Electromigration Reliability Enhancement. [Citation Graph (0, 0)][DBLP ] Conf ] Glenn H. Chapman FPGA Design for Decimeter Scale Integration (DMSI). [Citation Graph (0, 0)][DBLP ] Conf ] Suriyaprakash Natarajan , Melvin A. Breuer , Sandeep K. Gupta Process Variations and their Impact on Circuit Operation. [Citation Graph (0, 0)][DBLP ] Conf ] Dhamin Al-Khalili , Saman Adham , Come Rozon , Moazzem Hossain , D. Racz Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] James F. Plusquellic , Donald M. Chiarulli , Steven P. Levitan Characterization of CMOS Defects using Transient Signal Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay R. Sar-Dessai , D. M. H. Walker Accurate Fault Modeling and Fault Simulation of Resistive Bridges. [Citation Graph (0, 0)][DBLP ] Conf ] Xiao Sun , Carmie Hull Functional Verification Coverage vs. Physical Stuck-at Fault Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Alfredo Benso , Maurizio Rebaudengo , Matteo Sonza Reorda , Pierluigi Civera An Integrated HW and SW Fault Injection Environment for Real-Time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Claude Thibeault Increasing Current Testing Resolution. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitrios Kagaris , Spyros Tragoudas , Amitava Majumdar On-Chip Test Embedding for Multi-Weighted Random LFSRs. [Citation Graph (0, 0)][DBLP ] Conf ] Avinash Munshi , Fred J. Meyer , Fabrizio Lombardi A New Method for Testing EEPLA's. [Citation Graph (0, 0)][DBLP ] Conf ] Th. Haniotakis , Dimitris Nikolos , Y. Tsiatouhas C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Wenyi Feng , Fred J. Meyer , Wei-Kang Huang , Fabrizio Lombardi On the Complexity of Sequential Testing in Configurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Cecilia Metra , Michele Favalli , Bruno Riccò Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Donatella Sciuto , Cristina Silvano , Renato Stefanelli Systematic AUED Codes for Self-Checking Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Yau Guo , Jien-Chung Lo Challenges of Built-In Current Sensor Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Claude Thibeault , Luc Boisvert On the Current Behavior of Faulty and Fault-Free ICs and the Impact on Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Jayabrata Ghosh-Dastidar , Nur A. Touba A Systematic Approach for Diagnosing Multiple Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Yuejian Wu Diagnosis of Scan Chain Failures. [Citation Graph (0, 0)][DBLP ] Conf ] W. Lynn Gallagher , Earl E. Swartzlander Jr. Error-Correcting Goldschmidt Dividers Using Time Shared TMR. [Citation Graph (0, 0)][DBLP ] Conf ] Sergio D'Angelo , Cecilia Metra , S. Pastore , A. Pogutz , Giacomo R. Sechi Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-Based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Audet , Steve Masson , Yvon Savaria Reducing Fault Sensitivity of Microprocessor-Based Systems by Modifying Workload Structure. [Citation Graph (0, 0)][DBLP ] Conf ] Samuel Norman Hamilton , Alex Orailoglu Transient and Intermittent Fault Recovery without Rollback. [Citation Graph (0, 0)][DBLP ] Conf ] Jien-Chung Lo Highly Reliable Systems with Differential Built-In Current Sensors. [Citation Graph (0, 0)][DBLP ] Conf ] Anurag Gupta , Kanad Chakraborty , Pinaki Mazumder A Silicon Compiler for Fault-Tolerant ROMs. [Citation Graph (0, 0)][DBLP ] Conf ] Susumu Horiguchi , Issei Numata Self-Reconfiguration Scheme of 3D-Mesh Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Silvia Chiusano , Fulvio Corno , Matteo Sonza Reorda , Roberto Vietti A System for Evaluating On-Line Testability at the RT-level. [Citation Graph (0, 0)][DBLP ] Conf ] Anna Antola , Vincenzo Piuri , Mariagiovanna Sami High-level Synthesis of Data Paths with Concurrent Error Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Alex Orailoglu Graceful Degradation in Synthesis of VLSI ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Broglia , Giacomo Buonanno , Mariagiovanna Sami , M. Selvini Designing for Yield: A Defect-Tolerant Approach to High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaowei Li , Paul Y. S. Cheung High-Level BIST Synthesis for Delay Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Boni , Andrea Pierazzi Yield Enhancement by Multi-level Linear Modeling of Non-Idealities in an Interpolated Flash ADCs. [Citation Graph (0, 0)][DBLP ] Conf ] Pramodchandran N. Variyam , Abhijit Chatterjee Specification-Driven Test Design for Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Alfred V. Gomes , Ramakrishna Voorakaranam , Abhijit Chatterjee Modular Fault Simulation of Mixed Signal Circuits with Fault Ranking by Severity. [Citation Graph (0, 0)][DBLP ] Conf ] Serge N. Demidenko , Vincenzo Piuri , Vyacheslav N. Yarmolik , A. Shmidman BIST Module for Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] 