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Conferences in DBLP

Defect and Fault Tolerance in VLSI Systems (dft)
1999 (conf/dft/1999)

  1. Arunshankar Venkataraman, Israel Koren
    Determination of Yield Bounds Prior to Routing. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:4-13 [Conf]
  2. Julie D. Segal, Sergei Bakarian, Ron Ross
    Impact of Simulation Parameters on Critical Area Analysis. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:14-0 [Conf]
  3. Glenn H. Chapman, Yves Audet
    Creating 35 mm Camera Active Pixel Sensors. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:22-30 [Conf]
  4. Markus Rudack, Dirk Niggemeyer
    Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:31-39 [Conf]
  5. Nobuhiro Tomabechi
    Multi-Dimensional Subsystem-Dividing for Yield Enhancement in Defect-Tolerant WSI Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:40-45 [Conf]
  6. Stuart L. Riley
    Limitations to Estimating Yield Based on In-Line Defect Measurements. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:46-54 [Conf]
  7. Witold A. Pleskacz
    Yield Estimation of VLSI Circuits with Downscaled Layouts. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:55-60 [Conf]
  8. Frederic Duvivier
    Automatic Detection of Spatial Signature on Wafermaps in a High Volume Production. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:61-0 [Conf]
  9. James F. Plusquellic, Amy Germida, Zheng Yan
    8-Bit Multiplier Simulation Experiments Investigating the Use of Power Supply Transient Signals for the Detection of CMOS Defects. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:68-76 [Conf]
  10. Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone
    Charge Sharing Fault Detection for CMOS Domino Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:77-85 [Conf]
  11. Spyros Tragoudas, N. Denny
    Testing for Path Delay Faults Using Test Points. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:86-94 [Conf]
  12. Y. Tsiatouhas, Th. Haniotakis
    A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:95-100 [Conf]
  13. Sule Ozev, Alex Orailoglu
    Low-Cost Test for Large Analog IC's. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:101-0 [Conf]
  14. Wenyi Feng, Fred J. Meyer, Fabrizio Lombardi
    Novel Control Pattern Generators for Interconnect Testing with Boundary Scan. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:112-120 [Conf]
  15. Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou
    Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:121-129 [Conf]
  16. Dimitrios Kagaris, Spyros Tragoudas
    LFSR/SR Pseudo-Exhaustive TPG in Fewer Test Cycles. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:130-138 [Conf]
  17. Marco Brazzarola, Franco Fummi
    Power Characterization of LFSRs. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:139-147 [Conf]
  18. Xiaodong Zhang, Kaushik Roy
    Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:148-0 [Conf]
  19. Stefano Bertazzoni, Gian-Carlo Cardarilli, D. Piergentili, Marcello Salmeri, Adelio Salsano, Domenico Di Giovenale, G. C. Grande, P. Marinucci, S. Sperandei, S. Bartalucci, G. Mazzenga, M. Ricci, V. Bidoli, D. de Francesco, P. G. Picozza, A. Rovelli
    Failure Tests on 64 Mb SDRAM in Radiation Environment. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:158-164 [Conf]
  20. Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu
    RAMSES: A Fast Memory Fault Simulator. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:165-173 [Conf]
  21. Marco Brera, Fabrizio Ferrandi, Donatella Sciuto, Franco Fummi
    Increase the Behavioral Fault Model Accuracy Using High-Level Synthesis Information. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:174-180 [Conf]
  22. Firas Khadour, Xiaoling Sun
    Fast Signature Simulation for PPSFP Simulators. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:181-0 [Conf]
  23. Nohpill Park, Fabrizio Lombardi
    Stratified Testing of Multichip Module Systems under Uneven Known-Good-Yield. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:192-200 [Conf]
  24. Jin-Fu Li, Cheng-Wen Wu
    Testable and Fault Tolerant Design for FFT Networks. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:201-209 [Conf]
  25. Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante
    Soft-Error Detection through Software Fault-Tolerance Techniques. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:210-218 [Conf]
  26. Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaudengo, Massimo Violante
    Optimal Vector Selection for Low Power BIST. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:219-226 [Conf]
  27. Markus Seuring, Michael Gössel
    A Structural Approach for Space Compaction for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:227-0 [Conf]
  28. Parag K. Lala, Anup Singh, Alvernon Walker
    A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:238-246 [Conf]
  29. Cristiana Bolchini, Luigi Pomante, Donatella Sciuto, Fabio Salice
    A Synthesis Methodology Aimed at Improving the Quality of TSC Devices. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:247-255 [Conf]
  30. W. Lynn Gallagher, Earl E. Swartzlander Jr.
    Power Consumption in Fast Dividers Using Time Shared TMR. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:256-264 [Conf]
  31. Vincenzo Piuri, Earl E. Swartzlander Jr.
    Time-Shared Modular Redundancy for Fault-Tolerant FFT Processors. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:265-273 [Conf]
  32. Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Vincenzo Piuri
    Implementing a Self-Checking Neural System for Photon Event Identification by SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:274-0 [Conf]
  33. Kiattichai Saowapa, Haruhiko Kaneko, Eiji Fujiwara
    Systematic Deletion/Insertion Error Correcting Codes with Random Error Correction Capability. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:284-292 [Conf]
  34. William D. Armitage, Jien-Chung Lo
    Erasure Error Correction with Hardware Detection. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:293-301 [Conf]
  35. Gian-Carlo Cardarilli, Stefano Bertazzoni, Marcello Salmeri, Adelio Salsano, P. Marinucci
    Design of Fault-Tolerant Solid State Mass Memory. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:302-310 [Conf]
  36. Yasunao Katayama, Eric J. Stuckey, Sumio Morioka, Zhao Wu
    Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:311-318 [Conf]
  37. C. Wickman, Duncan G. Elliott, Bruce F. Cockburn
    Cost Models for Large File Memory DRAMs with ECC and Bad Block Marking. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:319-0 [Conf]
  38. Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra
    Transient and Permanent Fault Diagnosis for FPGA-Based TMR Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:330-338 [Conf]
  39. Yiorgos Makris, Alex Orailoglu
    A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:339-347 [Conf]
  40. Fred J. Meyer, Fabrizio Lombardi, Jun Zhao
    Good Processor Identification in Two-Dimensional Grids. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:348-356 [Conf]
  41. Sasikumar Cherubal, Abhijit Chatterjee
    A Methodology for Efficient Simulation and Diagnosis of Mixed-Signal Systems Using Error Waveforms. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:357-0 [Conf]
  42. Wenyi Feng, Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi
    Reconfiguration of One-Time Programmable FPGAs with Faulty Logic Resources. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:368-376 [Conf]
  43. Abderrahim Doumar, Satoshi Kaneko, Hideo Ito
    Defect and Fault Tolerance FPGAs by Shifting the Configuration Data. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:377-385 [Conf]
  44. John Lach, William H. Mangione-Smith, Miodrag Potkonjak
    Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:386-394 [Conf]
  45. Sumito Nakano, Naotake Kamiura, Yutaka Hata, Nobuyuki Matsui
    Reconfiguration of Two-Dimensional Meshes Embedded in Faulty Hypercubes. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:395-403 [Conf]
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