Conferences in DBLP
Arunshankar Venkataraman , Israel Koren Determination of Yield Bounds Prior to Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Julie D. Segal , Sergei Bakarian , Ron Ross Impact of Simulation Parameters on Critical Area Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Glenn H. Chapman , Yves Audet Creating 35 mm Camera Active Pixel Sensors. [Citation Graph (0, 0)][DBLP ] Conf ] Markus Rudack , Dirk Niggemeyer Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Nobuhiro Tomabechi Multi-Dimensional Subsystem-Dividing for Yield Enhancement in Defect-Tolerant WSI Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Stuart L. Riley Limitations to Estimating Yield Based on In-Line Defect Measurements. [Citation Graph (0, 0)][DBLP ] Conf ] Witold A. Pleskacz Yield Estimation of VLSI Circuits with Downscaled Layouts. [Citation Graph (0, 0)][DBLP ] Conf ] Frederic Duvivier Automatic Detection of Spatial Signature on Wafermaps in a High Volume Production. [Citation Graph (0, 0)][DBLP ] Conf ] James F. Plusquellic , Amy Germida , Zheng Yan 8-Bit Multiplier Simulation Experiments Investigating the Use of Power Supply Transient Signals for the Detection of CMOS Defects. [Citation Graph (0, 0)][DBLP ] Conf ] Ching-Hwa Cheng , Shih-Chieh Chang , Jinn-Shyan Wang , Wen-Ben Jone Charge Sharing Fault Detection for CMOS Domino Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Spyros Tragoudas , N. Denny Testing for Path Delay Faults Using Test Points. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Tsiatouhas , Th. Haniotakis A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Sule Ozev , Alex Orailoglu Low-Cost Test for Large Analog IC's. [Citation Graph (0, 0)][DBLP ] Conf ] Wenyi Feng , Fred J. Meyer , Fabrizio Lombardi Novel Control Pattern Generators for Interconnect Testing with Boundary Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Xrysovalantis Kavousianos , Dimitris Bakalis , Haridimos T. Vergos , Dimitris Nikolos , George Alexiou Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitrios Kagaris , Spyros Tragoudas LFSR/SR Pseudo-Exhaustive TPG in Fewer Test Cycles. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Brazzarola , Franco Fummi Power Characterization of LFSRs. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaodong Zhang , Kaushik Roy Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Stefano Bertazzoni , Gian-Carlo Cardarilli , D. Piergentili , Marcello Salmeri , Adelio Salsano , Domenico Di Giovenale , G. C. Grande , P. Marinucci , S. Sperandei , S. Bartalucci , G. Mazzenga , M. Ricci , V. Bidoli , D. de Francesco , P. G. Picozza , A. Rovelli Failure Tests on 64 Mb SDRAM in Radiation Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Feng Wu , Chih-Tsun Huang , Cheng-Wen Wu RAMSES: A Fast Memory Fault Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Brera , Fabrizio Ferrandi , Donatella Sciuto , Franco Fummi Increase the Behavioral Fault Model Accuracy Using High-Level Synthesis Information. [Citation Graph (0, 0)][DBLP ] Conf ] Firas Khadour , Xiaoling Sun Fast Signature Simulation for PPSFP Simulators. [Citation Graph (0, 0)][DBLP ] Conf ] Nohpill Park , Fabrizio Lombardi Stratified Testing of Multichip Module Systems under Uneven Known-Good-Yield. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Fu Li , Cheng-Wen Wu Testable and Fault Tolerant Design for FFT Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Maurizio Rebaudengo , Matteo Sonza Reorda , Marco Torchiano , Massimo Violante Soft-Error Detection through Software Fault-Tolerance Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Fulvio Corno , Matteo Sonza Reorda , Maurizio Rebaudengo , Massimo Violante Optimal Vector Selection for Low Power BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Markus Seuring , Michael Gössel A Structural Approach for Space Compaction for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Parag K. Lala , Anup Singh , Alvernon Walker A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Cristiana Bolchini , Luigi Pomante , Donatella Sciuto , Fabio Salice A Synthesis Methodology Aimed at Improving the Quality of TSC Devices. [Citation Graph (0, 0)][DBLP ] Conf ] W. Lynn Gallagher , Earl E. Swartzlander Jr. Power Consumption in Fast Dividers Using Time Shared TMR. [Citation Graph (0, 0)][DBLP ] Conf ] Vincenzo Piuri , Earl E. Swartzlander Jr. Time-Shared Modular Redundancy for Fault-Tolerant FFT Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Monica Alderighi , Sergio D'Angelo , Giacomo R. Sechi , Vincenzo Piuri Implementing a Self-Checking Neural System for Photon Event Identification by SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Kiattichai Saowapa , Haruhiko Kaneko , Eiji Fujiwara Systematic Deletion/Insertion Error Correcting Codes with Random Error Correction Capability. [Citation Graph (0, 0)][DBLP ] Conf ] William D. Armitage , Jien-Chung Lo Erasure Error Correction with Hardware Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Gian-Carlo Cardarilli , Stefano Bertazzoni , Marcello Salmeri , Adelio Salsano , P. Marinucci Design of Fault-Tolerant Solid State Mass Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Yasunao Katayama , Eric J. Stuckey , Sumio Morioka , Zhao Wu Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention. [Citation Graph (0, 0)][DBLP ] Conf ] C. Wickman , Duncan G. Elliott , Bruce F. Cockburn Cost Models for Large File Memory DRAMs with ECC and Bad Block Marking. [Citation Graph (0, 0)][DBLP ] Conf ] Sergio D'Angelo , Giacomo R. Sechi , Cecilia Metra Transient and Permanent Fault Diagnosis for FPGA-Based TMR Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Yiorgos Makris , Alex Orailoglu A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Fred J. Meyer , Fabrizio Lombardi , Jun Zhao Good Processor Identification in Two-Dimensional Grids. [Citation Graph (0, 0)][DBLP ] Conf ] Sasikumar Cherubal , Abhijit Chatterjee A Methodology for Efficient Simulation and Diagnosis of Mixed-Signal Systems Using Error Waveforms. [Citation Graph (0, 0)][DBLP ] Conf ] Wenyi Feng , Xiao-Tao Chen , Fred J. Meyer , Fabrizio Lombardi Reconfiguration of One-Time Programmable FPGAs with Faulty Logic Resources. [Citation Graph (0, 0)][DBLP ] Conf ] Abderrahim Doumar , Satoshi Kaneko , Hideo Ito Defect and Fault Tolerance FPGAs by Shifting the Configuration Data. [Citation Graph (0, 0)][DBLP ] Conf ] John Lach , William H. Mangione-Smith , Miodrag Potkonjak Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Sumito Nakano , Naotake Kamiura , Yutaka Hata , Nobuyuki Matsui Reconfiguration of Two-Dimensional Meshes Embedded in Faulty Hypercubes. [Citation Graph (0, 0)][DBLP ] Conf ] 