Conferences in DBLP
Rajnish K. Prasad , Israel Koren The Effect of Placement on Yield for Standard Cell Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Moran , Gerard A. Allan IC Critical Volume Calculation through Ray-Casting of CSG Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaohong Jiang , Susumu Horiguchi , Yue Hao Predicting the Yield Efficacy of a Defect-Tolerant Embedded Core. [Citation Graph (0, 0)][DBLP ] Conf ] Tianxu Zhao , Yue Hao , Yongchang Jiao VLSI Yield Optimization Based on the Sub-Processing-Element Level Redundancy. [Citation Graph (0, 0)][DBLP ] Conf ] Nohpill Park , Fred J. Meyer , Fabrizio Lombardi Quality-Effective Repair of Multichip Module Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Israel Koren , Zahava Koren , Glenn H. Chapman A Self-Correcting Active Pixel Camera. [Citation Graph (0, 0)][DBLP ] Conf ] Moritoshi Yasunaga , Ikuo Yoshihara , Jung Hwan Kim A High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI. [Citation Graph (0, 0)][DBLP ] Conf ] Markus Rudack , Michael Redeker , Dieter Treytnar , Ole Mende , Klaus Herrmann Self-Configuration of a Large Area Integrated Multiprocessor System for Video Applications. [Citation Graph (0, 0)][DBLP ] Conf ] R. M. Lea , P. T. Tetnowski , M. Covic A Reconfigurable WSI Massively Data-Parallel Processing Device for Cost-Effective 3D Sensor Data Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaohong Jiang , Susumu Horiguchi Optimization of Wafer Scale H-Tree Clock Distribution Network Based on a New Statistical Skew Model. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Herrmann , Sören Moch , Jörg Hilgenstock , Peter Pirsch Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Ole Mende , Michael Redeker , Markus Rudack , Dieter Treytnar A Multifunctional Laser Linking and Cutting Structure for Standard 0.25 mum CMOS-Technology. [Citation Graph (0, 0)][DBLP ] Conf ] W. Shi , K. Kumar , Fabrizio Lombardi On the Complexity of Switch Programming in Fault-Tolerant-Configurable Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Abderrahim Doumar , Hideo Ito Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources. [Citation Graph (0, 0)][DBLP ] Conf ] Naotake Kamiura , Takashi Kodera , Nobuyuki Matsui Design of a Fault Tolerant Multistage Interconnection Network with Parallel Duplicated Switches. [Citation Graph (0, 0)][DBLP ] Conf ] Monica Alderighi , Sergio D'Angelo , Giacomo R. Sechi , Cecilia Metra Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs. [Citation Graph (0, 0)][DBLP ] Conf ] Jae-Hyuck Kwak , Earl E. Swartzlander Jr. , Vincenzo Piuri Fault-Tolerant High-Performance Cordic Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Gian-Carlo Cardarilli , Adelio Salsano , P. Marinucci , Marco Ottavi A Fault-Tolerant 176 Gbit Solid State Mass Memory Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Masato Kitakami , Hongyuan Chen , Eiji Fujiwara Evaluations of Burst Error Recovery for VF Arithmetic Coding. [Citation Graph (0, 0)][DBLP ] Conf ] Ganesan Umanesan , Eiji Fujiwara Single Byte Error Control Codes with Double Bit within a Block Error Correcting Capability for Semiconductor Memory Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Yasunao Katayama , Yasushi Negishi , Sumio Morioka Efficient Error Correction Code Configurations for Quasi-Nonvolatile Data Retention by DRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Itsuo Takanami Built-in Self-Reconfiguring Systems for Mesh-Connected Processor Arrays with Spares on Two Rows/Columns. [Citation Graph (0, 0)][DBLP ] Conf ] Nobuo Tsuda Fault-Tolerant Ring- and Toroidal Mesh-Connected Processor Arrays Able to Enhance Emulation of Hypercubes. [Citation Graph (0, 0)][DBLP ] Conf ] Alfredo Benso , Silvia Chiusano , Paolo Prinetto , P. Simonotti , G. Ugo Self-Repairing in a Micro-Programmed Processor for Dependable Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Masaru Fukushi , Susumu Horiguchi Self-Reconfigurable Mesh Array System on FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Steininger , Christoph Scherrer How Does Resource Utilization Affect Fault Tolerance? [Citation Graph (0, 0)][DBLP ] Conf ] Maurizio Rebaudengo , Matteo Sonza Reorda , Marco Torchiano , Massimo Violante An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Serge N. Demidenko , Eugene M. Levine , Vincenzo Piuri Synthesis of On-Line Testing Control Units: Flow Graph Coding/Monitoring Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Parag K. Lala , Alvernon Walker An On-Line Reconfigurable FPGA Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Gert Jervan , Zebo Peng , Raimund Ubar Test Cost Minimization for Hybrid Bist. [Citation Graph (0, 0)][DBLP ] Conf ] G. Biasoli , Fabrizio Ferrandi , Donatella Sciuto , Alessandro Fin , Franco Fummi BIST Architectures Selection Based on Behavioral Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Chuang Cheng , Chih-Tsun Huang , Jing-Reng Huang , Cheng-Wen Wu , Chen-Jong Wey , Ming-Chang Tsai BRAINS: A BIST Compiler for Embedded Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Nohpill Park , S. J. Ruiwale , Fabrizio Lombardi Testing the Configurability of Dynamic FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Sukalyan Mukherjee Design for Testability to Achieve High Test Coverage - A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Ching-Hwa Cheng , Jinn-Shyan Wang , Shih-Chieh Chang , Wen-Ben Jone Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Sosnowski , Tomasz Wabia , Tomasz Bech Path Delay Fault Testability Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Madhuban Kishor , José Pineda de Gyvez Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families. [Citation Graph (0, 0)][DBLP ] Conf ] Shigeru Ohnishi , Michinori Nishihara A New Light-Based Logic IC Screening Method. [Citation Graph (0, 0)][DBLP ] Conf ] Masaki Hashizume , Hiroyuki Yotsuyanagi , Takeomi Tamesada , Masashi Takeda Testability Analysis of IDDQ Testing with Large Threshold Value. [Citation Graph (0, 0)][DBLP ] Conf ] Shengli Li , Kai Zhang , Jien-Chung Lo The 2nd Order Analysis of IDDQ Test Data. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Baldini , Alfredo Benso , Silvia Chiusano , Paolo Prinetto 'BOND': An Interposition Agents Based Fault Injector for Windows NT. [Citation Graph (0, 0)][DBLP ] Conf ] J. C. Baraza , J. Gracia , Daniel Gil , Pedro J. Gil A Prototype of a VHDL-Based Fault Injection Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Lörinc Antoni , Régis Leveugle , Béla Fehér Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. [Citation Graph (0, 0)][DBLP ] Conf ] Régis Leveugle Fault Injection in VHDL Descriptions and Emulation. [Citation Graph (0, 0)][DBLP ] Conf ] 