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Conferences in DBLP

Defect and Fault Tolerance in VLSI Systems (dft)
2003 (conf/dft/2003)

  1. Xiaopeng Wang, Marco Ottavi, Fabrizio Lombardi
    Yield Analysis of Compiler-Based Arrays of Embedded SRAMs. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:3-10 [Conf]
  2. Tianxu Zhao, Xuchao Duan, Yue Hao, Peijun Ma
    Reliability Estimation Model of ICs Interconnect Based on Uniform Distribution of Defects on a Chip. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:11-17 [Conf]
  3. Meng Lu, Yvon Savaria, Bing Qiu, Jacques Taillefer
    IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale Integration. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:18-25 [Conf]
  4. Dirk K. de Vries, Paul L. C. Simon
    Calibration of Open Interconnect Yield Models. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:26-33 [Conf]
  5. T. Feng, Nohpill Park, Yong-Bin Kim, Vincenzo Piuri
    Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:34-0 [Conf]
  6. Vijay K. Jain, Glenn H. Chapman
    Level-Hybrid Optoelectronic TESH Interconnection Network. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:45-52 [Conf]
  7. Sunjaya Djaja, Glenn H. Chapman, Desmond Y. H. Cheung, Yves Audet
    Implementation and Testing of Fault-Tolerant Photodiode-Based Active Pixel Sensor (APS). [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:53-0 [Conf]
  8. Cecilia Metra, T. M. Mak, Daniele Rossi
    Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:63-70 [Conf]
  9. Monica Alderighi, Fabio Casini, Sergio D'Angelo, M. Mancini, A. Marmo, S. Pastore, Giacomo R. Sechi
    A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:71-78 [Conf]
  10. Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, Weiping Shi
    CodSim -- A Combined Delay Fault Simulator. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:79-0 [Conf]
  11. Hiroshi Takahashi, Yasunori Tsugaoka, Hidekazu Ayano, Yuzo Takamatsu
    BIST Based Fault Diagnosis Using Ambiguous Test Set. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:89-96 [Conf]
  12. Luca Schiano, Fabrizio Lombardi
    On the Test and Diagnosis of the Perfect Shuffle. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:97-104 [Conf]
  13. Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri
    Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:105-0 [Conf]
  14. Y. Hariri, Claude Thibeault
    3DSDM: A 3 Data-Source Diagnostic Method. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:117-123 [Conf]
  15. Marco S. Dragic, Martin Margala
    Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:124-131 [Conf]
  16. Sagar S. Sabade, D. M. H. Walker
    CROWNE: Current Ratio Outliers with Neighbor Estimator. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:132-139 [Conf]
  17. Abhijit Prasad, D. M. H. Walker
    Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:140-0 [Conf]
  18. Hamidreza Hashempour, Fabrizio Lombardi
    ATE-Amenable Test Data Compression with No Cyclic Scan. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:151-158 [Conf]
  19. Fengming Zhang, Young-Jun Lee, T. Kane, Luca Schiano, Mariam Momenzadeh, Yong-Bin Kim, Fred J. Meyer, Fabrizio Lombardi, S. Max, Phil Perkinson
    A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:159-166 [Conf]
  20. James Wingfield, Jennifer Dworak, M. Ray Mercer
    Function-Based Dynamic Compaction and its Impact on Test Set Sizes. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:167-174 [Conf]
  21. Xiao Liu, Michael S. Hsiao
    Constrained ATPG for Broadside Transition Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:175-0 [Conf]
  22. Sandeep Bhatia
    Test Compaction by Using Linear-Matrix Driven Scan Chains. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:185-190 [Conf]
  23. Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy
    Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:191-198 [Conf]
  24. Ching-Hwa Cheng
    Design Scan Test Strategy for Single Phase Dynamic Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:199-0 [Conf]
  25. Kedarnath J. Balakrishnan, Nur A. Touba
    Scan-Based BIST Diagnosis Using an Embedded Processor. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:209-216 [Conf]
  26. C. V. Krishna, Nur A. Touba
    Hybrid BIST Using an Incrementally Guided LFSR. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:217-224 [Conf]
  27. Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
    Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:225-0 [Conf]
  28. Parag K. Lala
    A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:235-241 [Conf]
  29. Haruhiko Kaneko, Eiji Fujiwara
    Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix Symbols. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:242-249 [Conf]
  30. Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr.
    Quadruple Time Redundancy Adders. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:250-256 [Conf]
  31. Daniele Rossi, S. Cavallotti, Cecilia Metra
    Error Correcting Codes for Crosstalk Effect Minimization. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:257-0 [Conf]
  32. Charles F. Hawkins, Ali Keshavarzi, Jaume Segura
    A View from the Bottom: Nanometer Technology AC Parametric Failures -- Why, Where, and How to Detect. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:267-0 [Conf]
  33. Yukiya Miura, Daisuke Kato
    Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model: A Case Study of Application and Implementation. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:279-286 [Conf]
  34. Kranthi K. Pinjala, Bruce C. Kim
    An Approach for Selection of Test Points for Analog Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:287-294 [Conf]
  35. Jerzy Dabrowski
    BiST Model for IC RF-Transceiver Front-End. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:295-302 [Conf]
  36. John M. Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani
    A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:303-0 [Conf]
  37. Arman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi
    Thermal Management of High Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:313-319 [Conf]
  38. Ying Zhang, Krishnendu Chakrabarty
    Fault Recovery Based on Checkpointing for Hard Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:320-327 [Conf]
  39. Eiko Sugawara, Masaru Fukushi, Susumu Horiguchi
    Fault Tolerant Multi-Layer Neural Networks with GA Training. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:328-335 [Conf]
  40. Abdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante
    Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:336-343 [Conf]
  41. Konstantinos Rokas, Yiorgos Makris, Dimitris Gizopoulos
    Low Cost Convolutional Code Based Concurrent Error Detection in FSMs. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:344-351 [Conf]
  42. Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi
    Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:352-360 [Conf]
  43. John M. Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani
    An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:361-368 [Conf]
  44. Rafic A. Ayoubi, Haissam Ziade, Magdy A. Bayoumi
    Fault Tolerant Hopfield Associative Memory on Torus. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:369-376 [Conf]
  45. B. Nicolescu, P. Peronnard, Raoul Velazco, Yvon Savaria
    Efficiency of Transient Bit-Flips Detection by Software Means: A Complete Study. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:377-384 [Conf]
  46. Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
    Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:385-392 [Conf]
  47. N.-J. Park, Byoungjae Jin, K. M. George, Nohpill Park, Minsu Choi
    Regressive Testing for System-on-Chip with Unknown-Good-Yield. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:393-400 [Conf]
  48. Gian-Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
    Error Detection in Signed Digit Arithmetic Circuit with Parity Checker. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:401-408 [Conf]
  49. Mehdi Baradaran Tahoori
    Application-Dependent Testing of FPGA Interconnects. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:409-416 [Conf]
  50. Cecilia Metra, Stefano Di Francescantonio, Martin Omaña
    Automatic Modification of Sequential Circuits for Self-Checking Implementation. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:417-424 [Conf]
  51. Dan Zhao, Shambhu J. Upadhyaya, Martin Margala
    Control Constrained Resource Partitioning for Complex SoCs. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:425-432 [Conf]
  52. Kartik Mohanram, Nur A. Touba
    Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:433-0 [Conf]
  53. Cristiana Bolchini, Fabio Salice, Donatella Sciuto, R. Zavaglia
    An Integrated Design Approach for Self-Checking FPGAs. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:443-450 [Conf]
  54. Bai Hong Fang, Nicola Nicolici
    Power-Constrained Embedded Memory BIST Architecture. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:451-458 [Conf]
  55. Michael Nicolaidis, Nadir Achouri, Lorena Anghel
    A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:459-466 [Conf]
  56. Rob Aitken, Neeraj Dogra, Dhrumil Gandhi, Scott Becker
    Redundancy, Repair, and Test Features of a 90nm Embedded SRAM Generator. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:467-474 [Conf]
  57. Xiaoling Sun, Bruce F. Cockburn, Duncan G. Elliott
    An Efficient Functional Test for the Massively-Parallel C ?RAM Logic-Enhanced Memory Architecture. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:475-0 [Conf]
  58. Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali
    Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:485-492 [Conf]
  59. Lorena Anghel, Raoul Velazco, S. Saleh, S. Deswaertes, A. El Moucary
    Preliminary Validation of an Approach Dealing with Processor Obsolescence. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:493-0 [Conf]
  60. Gang Zeng, Hideo Ito
    Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:503-510 [Conf]
  61. Vikram Iyengar, Anshuman Chandra
    A Uni.ed SOC Test Approach Based on Test Data Compression and TAM Design. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:511-518 [Conf]
  62. Adam B. Kinsman, Jonathan I. Hewitt, Nicola Nicolici
    Embedded Compact Deterministic Test for IP-Protected Cores. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:519-0 [Conf]
  63. Fulvio Corno, S. Tosato, P. Gabrielli
    System-Level Analysis of Fault Effects in an Automotive Environment. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:529-536 [Conf]
  64. J. Pérez, Matteo Sonza Reorda, Massimo Violante
    Dependability Analysis of CAN Networks: An Emulation-Based Approach. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:537-0 [Conf]
  65. Toshinori Sato
    Exploiting Instruction Redundancy for Transient Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:547-554 [Conf]
  66. Yung-Yuan Chen, Shi-Jinn Horng, Hung-Chuan Lai
    An Integrated Fault-Tolerant Design Framework for VLIW Processors. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:555-562 [Conf]
  67. Sobeeh Almukhaizim, Yiorgos Makris
    Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:563-570 [Conf]
  68. Vinu Vijay Kumar, John Lach
    Heterogeneous Redundancy for Fault and Defect Tolerance with Complexity Independent Area Overhead. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:571-0 [Conf]
  69. O. Goloubeva, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Soft-Error Detection Using Control Flow Assertions. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:581-588 [Conf]
  70. B. Nicolescu, Yvon Savaria, Raoul Velazco
    SIED: Software Implemented Error Detection. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:589-596 [Conf]
  71. Atul Maheshwari, Israel Koren, Wayne Burleson
    Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:597-0 [Conf]
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