Conferences in DBLP
Roman Barsky , Israel A. Wagner Reliability and Yield: A Joint Defect-Oriented Approach. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:2-10 [Conf ] Xiaopeng Wang , Marco Ottavi , Fred J. Meyer , Fabrizio Lombardi On The Yield of Compiler-Based eSRAMs. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:11-19 [Conf ] Yu-Tsao Hsing , Chih-Wea Wang , Ching-Wei Wu , Chih-Tsun Huang , Cheng-Wen Wu Failure Factor Based Yield Enhancement for SRAM Designs. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:20-28 [Conf ] Jing Huang , Mariam Momenzadeh , Mehdi Baradaran Tahoori , Fabrizio Lombardi Defect Characterization for Scaling of QCA Devices. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:30-38 [Conf ] Alexandre Schmid , Yusuf Leblebici A Highly Fault Tolerant PLA Architecture for Failure-Prone Nanometer CMOS and Novel Quantum Device Technologies. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:39-47 [Conf ] Shanrui Zhang , Minsu Choi , Nohpill Park , Fabrizio Lombardi Probabilistic Balancing of Fault Coverage and Test Cost in Combined Built-In Self-Test/Automated Test Equipment Testing Environment. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:48-56 [Conf ] Michelle L. La Haye , Glenn H. Chapman , Cory Jung , Desmond Y. H. Cheung , Sunjaya Djaja , Benjamin Wang , Gary Liaw , Yves Audet Characteristics of Fault-Tolerant Photodiode and Photogate Active Pixel Sensor (APS). [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:58-66 [Conf ] Glenn H. Chapman , Vijay K. Jain , Shekhar Bhansali Defect Avoidance in a 3-D Heterogeneous Sensor. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:67-75 [Conf ] Ammar Aljer , Philippe Devienne Co-Design and Refinement for Safety Critical Systems. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:78-86 [Conf ] Mohamed Abbas , Makoto Ikeda , Kunihiro Asada Noise Effects on Performance of Low Power Design Schemes in Deep Submicron Regime. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:87-95 [Conf ] Jing Huang , Mehdi Baradaran Tahoori , Fabrizio Lombardi On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:96-104 [Conf ] Stefano Bertazzoni , Domenico Di Giovenale , Marcello Salmeri , Arianna Mencattini , Adelio Salsano , M. Florean , Jeffery Wyss , Ricardo Rando , Silvano Lora Monitoring Methodology for TID Damaging of SDRAM Devices based on Retention Time Analysis. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:106-110 [Conf ] Xiaopeng Wang , Marco Ottavi , Fabrizio Lombardi Testing of Inter-Word Coupling Faults in Word-Oriented SRAMs. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:111-119 [Conf ] Baosheng Wang , Yuejian Wu , André Ivanov Designs for Reducing Test Time of Distributed Small Embedded SRAMs. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:120-128 [Conf ] Guido Bertoni , Luca Breveglieri , Israel Koren , Paolo Maistri An Efficient Hardware-Based Fault Diagnosis Scheme for AES: Performances and Cost. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:130-138 [Conf ] Shi-Yu Huang A Fading Algorithm For Sequential Fault Diagnosis. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:139-147 [Conf ] Hamidreza Hashempour , Fabrizio Lombardi Compression of VLSI Test Data by Arithmetic Coding. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:150-157 [Conf ] Gian-Carlo Cardarilli , Marco Ottavi , Salvatore Pontarelli , Marco Re , Adelio Salsano Data Integrity Evaluations of Reed Solomon Codes for Storage Systems. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:158-164 [Conf ] Ping-Hsun Hsieh , Ing-Yi Chen , Yu-Ting Lin , Sy-Yen Kuo An XOR Based Reed-Solomon Algorithm for Advanced RAID Systems. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:165-172 [Conf ] Ajoy Kumar Palit , Volker Meyer , Walter Anheier , Jürgen Schlöffel Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:174-182 [Conf ] Irith Pomeranz , Sudhakar M. Reddy Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:183-190 [Conf ] Michele Favalli "Victim Gate" Crosstalk Fault Model. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:191-199 [Conf ] Martin Omaña , Daniele Rossi , Cecilia Metra Fast and Low-Cost Clock Deskew Buffer. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:202-210 [Conf ] Tejasvi Das , Anand Gopalan , Clyde Washburn , P. R. Mukund Dynamic Input Match Correction in RF Low Noise Amplifiers. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:211-219 [Conf ] Jerzy Dabrowski , Javier Gonzalez Bayon Mixed Loopback BiST for RF Digital Transceivers. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:220-228 [Conf ] Yukiya Miura Fault Diagnosis of Analog Circuits by Operation-Region Model and X-Y Zoning Method. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:230-238 [Conf ] Adão Antônio de Souza Jr. , Luigi Carro Robust Low-Cost Analog Signal Acquisition with Self-Test Capabilities. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:239-247 [Conf ] Lorena Anghel , Ernesto Sánchez , Matteo Sonza Reorda , Giovanni Squillero , Raoul Velazco Coupling Different Methodologies to Validate Obsolete Microprocessors. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:250-255 [Conf ] Ireneusz Gosciniak A New Approach to Linear Connections Building BIST Structure Based on CSTP Structure. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:256-263 [Conf ] Najwa Aaraj , Anis Nazer , Ali Chehab , Ayman I. Kayssi Transient Current Testing of Dynamic CMOS Circuits. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:264-271 [Conf ] Brian Peng , Ing-Yi Chen , Sy-Yen Kuo , Colin Bolger IC HTOL Test Stress Condition Optimization. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:272-279 [Conf ] Arvind Kumar , Sandip Tiwari Testing and Defect Tolerance: A Rent's Rule Based Analysis and Implications on Nanoelectronics. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:280-288 [Conf ] Carlos Arthur Lang Lisbôa , Luigi Carro Arithmetic Operators Robust to Multiple Simultaneous Upsets. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:289-297 [Conf ] Yinhe Han , Yu Hu , Huawei Li , Xiaowei Li , Anshuman Chandra Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:298-305 [Conf ] Hung-Yau Lin , Fu-Min Yeh , Ing-Yi Chen , Sy-Yen Kuo An Efficient Perfect Algorithm for Memory Repair Problems. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:306-313 [Conf ] Swarup Bhunia , Hamid Mahmoodi-Meimand , Arijit Raychowdhury , Kaushik Roy First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:314-315 [Conf ] Hamidreza Hashempour , Luca Schiano , Fabrizio Lombardi Error-Resilient Test Data Compression Using Tunstall Codes. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:316-323 [Conf ] D. P. Vasudevan , Parag K. Lala , James Patrick Parkerson Online Testable Reversible Logic Circuit Design using NAND Blocks. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:324-331 [Conf ] Nitin Parimi , Xiaoling Sun Toggle-Masking for Test-per-Scan VLSI Circuits. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:332-338 [Conf ] Naotake Kamiura , Teijiro Isokawa , Nobuyuki Matsui Learning Based on Fault Injection and Weight Restriction for Fault-Tolerant Hopfield Neural Networks. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:339-346 [Conf ] John Y. Fong , Randy Acklin , John Roscher , Feng Li , Cindy Laird , Cezary Pietrzyk Nonvolatile Repair Caches Repair Embedded SRAM and New Nonvolatile Memories. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:347-355 [Conf ] Shanrui Zhang , Minsu Choi , Nohpill Park Modeling Yield of Carbon-Nanotube/Silicon-Nanowire FET-Based Nanoarray Architecture with h-hot Addressing Scheme. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:356-364 [Conf ] Michele Favalli Annotated Bit Flip Fault Model. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:366-376 [Conf ] Nicola Bombieri , Franco Fummi , Graziano Pravadelli At-Speed Functional Verification of Programmable Devices. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:386-394 [Conf ] Yung-Yuan Chen , Kun-Feng Chen Incorporating Signature-Monitoring Technique in VLIW Processors. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:395-402 [Conf ] Paolo Bernardi , Maurizio Rebaudengo , Matteo Sonza Reorda Exploiting an I-IP for In-Field SOC Test. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:404-412 [Conf ] Gang Zeng , Hideo Ito Non-Intrusive Test Compression for SOC Using Embedded FPGA Core. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:413-421 [Conf ] Matteo Sonza Reorda , Massimo Violante On-Line Analysis and Perturbation of CAN Networks. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:424-432 [Conf ] Cristiana Bolchini , Antonio Miele , Fabio Salice , Donatella Sciuto , Luigi Pomante Reliable System Co-Design: The FIR Case Study. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:433-441 [Conf ] T. Feng , Nohpill Park , Yong-Bin Kim , Fabrizio Lombardi , Fred J. Meyer Reliability Modeling and Assurance of Clockless Wave Pipeline. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:442-450 [Conf ] Régis Leveugle , D. Cimonnet , Abdelaziz Ammari System-Level Dependability Analysis with RT-Level Fault Injection Accuracy. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:451-458 [Conf ] Jennifer Dworak , James Wingfield , M. Ray Mercer A Preliminary Investigation of Observation Diversity for Enhancing Fortuitous Detection of Defects. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:460-468 [Conf ] Irith Pomeranz , Sudhakar M. Reddy Concurrent On-Line Testing of Identical Circuits Through Output Comparison Using Non-Identical Input Vectors. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:469-476 [Conf ] Yen-Lin Peng , Jing-Jia Liou , Chih-Tsun Huang , Cheng-Wen Wu An Application-Independent Delay Testing Methodology for Island-Style FPGA. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:478-486 [Conf ] Andrzej Krasniewski Concurrent Error Detection in Sequential Circuits Implemented Using Embedded Memory of LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:487-495 [Conf ] Masaru Fukushi , Susumu Horiguchi Reconfiguration Algorithm for Degradable Processor Arrays Based on Row and Column Rerouting. [Citation Graph (0, 0)][DBLP ] DFT, 2004, pp:496-504 [Conf ]