Conferences in DBLP
Ulf Schlichtmann Systems Are Made from Transistors: UDSM Technology Creates New Challenges for Library and IC Development. [Citation Graph (0, 0)][DBLP ] Conf ] Daranee Hormdee , Jim D. Garside , Stephen B. Furber An Asynchronous Victim Cache. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Habibi , Sofiène Tahar , Adel Ghazel Formal Verification of a DSP Chip Using an Iterative Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth B. Kent , Micaela Serra Hardware Architecture for Java in a Hardware/Software Co-Design of the Virtual Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Jarno Vanne , Eero Aho , Kimmo Kuusilinna , Timo D. Hämäläinen Enhanced Configurable Parallel Memory Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Drechsler , Wolfgang Günther , Thomas Eschbach , Lothar Linhard , Gerhard Angst Recursive Bi-Partitioning of Netlists for Large Number of Partitions. [Citation Graph (0, 0)][DBLP ] Conf ] Ivan Milentijevic , Vladimir Ciric , Teufik Tokic , Oliver Vojinovic Folded Bit-Plane FIR Filter Architecture with Changeable Folding Factor. [Citation Graph (0, 0)][DBLP ] Conf ] Yinshui Xia , A. E. A. Almaini Best Polarity for Low Power XOR Gate Decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] José Ignacio Hidalgo , Juan Lanchares , Aitor Ibarra , Román Hermida A Hybrid Evolutionary Algorithm for Multi-FPGA Systems Design. [Citation Graph (0, 0)][DBLP ] Conf ] Matías J. Garrido , César Sanz , Marcos Jiménez , Juan M. Meneses A Flexible Architecture for H.263 Video Coding. [Citation Graph (0, 0)][DBLP ] Conf ] Omar Mansour , Egbert Molenkamp , Thijs Krol The Synthesis of a Hardware Scheduler for Non-Manifest Loops. [Citation Graph (0, 0)][DBLP ] Conf ] Juha-Pekka Soininen , Antti Pelkonen , Jussi Roivainen Configurable Memory Organisation for Communication Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Maik Boden , Jörg Schneider , Klaus Feske , Steffen Rülke Enhanced Reusability for SoC-Based HW/SW Co-Design. [Citation Graph (0, 0)][DBLP ] Conf ] Per Andersson , Krzysztof Kuchcinski , Klas Nordberg , Patrick Doherty Integrating a Computational Model and a Run Time System for Image Processing on a UAV. [Citation Graph (0, 0)][DBLP ] Conf ] Loe M. G. Feijs , Paul Gorissen , Joachim Trescher Specification and Simulation of Microprocessor Operations and Parallel Instructions. [Citation Graph (0, 0)][DBLP ] Conf ] Martyn Edwards , Benjamin Fozard Rapid Prototyping of Mixed Hardware and Software Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ilia Oussorov , Wolfgang Raab , J. A. Ulrich Hachmann , Alex Kravtsov Integration of Instruction Set Simulators into SystemC High Level Models. [Citation Graph (0, 0)][DBLP ] Conf ] Bart D. Theelen , A. C. Verschueren Architecture Design of a Scalable Single-Chip Multi-Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Ari Wahyudi , Amos Omondi Parallel Multimedia Processor Using Customised Infineon TriCores. [Citation Graph (0, 0)][DBLP ] Conf ] Manuel Lois Anido , Alexander Paar , Nader Bagherzadeh Improving the Operation Autonomy of SIMD Processing Elements by Using Guarded Instructions and Pseudo Branches. [Citation Graph (0, 0)][DBLP ] Conf ] Dmitry Cheresiz , Ben H. H. Juurlink , Stamatis Vassiliadis , Harry A. G. Wijshoff Implementation of a Streaming Execution Unit. [Citation Graph (0, 0)][DBLP ] Conf ] Josef Strnadel , Zdenek Kotásek Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. [Citation Graph (0, 0)][DBLP ] Conf ] Roman Goot , Ilya Levin , Sergei Ostanin Fault Latencies of Concurrent Checking FSMs. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Amblard , Fabienne Lagnier , Michel Lévy Using Formal Tools to Study Complex Circuits Behaviour. [Citation Graph (0, 0)][DBLP ] Conf ] André Schneider , Karl-Heinz Diener , Eero Ivask , Raimund Ubar , Elena Gramatová , Thomas Hollstein , Wieslaw Kuzmicz , Zebo Peng Integrated Design and Test Generation Under Internet Based Environment MOSCITO. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Wielage , Kees G. W. Goossens Networks on Silicon: Blessing or Nightmare? [Citation Graph (0, 0)][DBLP ] Conf ] Peter Marwedel Embedded Software: How To Make It Efficient? [Citation Graph (0, 0)][DBLP ] Conf ] Shoji Goto , Takashi Yamada , Norihisa Takayarna , Yoshifumi Matsushita , Yasoo Harada , Hiroto Yasuura A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA. [Citation Graph (0, 0)][DBLP ] Conf ] D. Piso , José-Alejandro Piñeiro , Javier D. Bruguera Analysis of the Impact of Different Methods for Division/Square Root Computation in the Performance of a Superscalar Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Nadia Nedjah , Luiza de Macedo Mourelle Reconfigurable Hardware Implementation of Montgomery Modular Multiplication and Parallel Binary Exponentiation. [Citation Graph (0, 0)][DBLP ] Conf ] Dragan Jankovic , Radomir S. Stankovic , Rolf Drechsler Decision Diagram Optimization Using Copy Properties. [Citation Graph (0, 0)][DBLP ] Conf ] Jacqueline E. Rice , Jon C. Muzio Use of the Autocorrelation Function in the Classification of Switching Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Aitor Ibarra , José M. Mendías , Juan Lanchares , José Ignacio Hidalgo , Román Hermida Optimization of Equational Specifications Using Genetic Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Pawel Kerntopf Synthesis of Multipurpose Reversible Logic Gates. [Citation Graph (0, 0)][DBLP ] Conf ] Domingo Benitez Performance of Remote FPGA-Based Coprocessors for Image-Processing Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Oswaldo Cadenas , Graham M. Megson Improving mW/MHz Ratio in FPGAs Pipelined Designs. [Citation Graph (0, 0)][DBLP ] Conf ] M. A. Hannan Bin Azhar , Keith R. Dimond Design of an FPGA Based Adaptive Neural Controller for Intelligent Robot Navigation. [Citation Graph (0, 0)][DBLP ] Conf ] Ernest Jamro , Kazimierz Wiatr Constant Coefficient Convolution Implemented in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Green , M. Vakondios , Martyn Edwards An Evaluation of an FPGA Run-Time Support System. [Citation Graph (0, 0)][DBLP ] Conf ] José M. Mendías , Román Hermida , María C. Molina , Olga Peñalba Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Azeddien M. Sllame , Vladimír Drábek An Efficient List-Based Scheduling Algorithm for High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Olga Peñalba , José M. Mendías , Román Hermida Source Code Transformation to Improve Conditional Hardware Reuse. [Citation Graph (0, 0)][DBLP ] Conf ] Zeljko Vujovic Work Out of the Algorithm Based on A-Mod for Detection Borderlines in Images Provided by the Intravascular Ultrasound System (IVUS) with 64 Transducers. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Drechsler , Daniel Große Reachability Analysis for Formal Verification of SystemC. [Citation Graph (0, 0)][DBLP ] Conf ] Toshinori Sato , Itsujiro Arita Simplifying Instruction Issue Logic in Superscalar Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Feldhofer , Thomas Trathnigg , Bernd Schnitzer A Self-Timed Arithmetic Unit for Elliptic Curve Cryptography. [Citation Graph (0, 0)][DBLP ] Conf ] Giuseppe Notarangelo , Marco Gibilaro , Francesco Pappalardo 0002 , Agatino Pennisi , Gaetano Palumbo Low Power Strategy for a TFT Controller. [Citation Graph (0, 0)][DBLP ] Conf ] Khushwinder Jasrotia , Jianwen Zhu Hardware Implementation of a Memory Allocator. [Citation Graph (0, 0)][DBLP ] Conf ] Mariusz Chyzy , Witold Kosinski Evolutionary Algorithm for State Assignment of Finite State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Ronny Frevert , Steffen Rülke , Torsten Schäfer , Frank Dresig Use of HDL Code Checkers to Support the IP Entrance Check - A Requirement Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] M. Verhappen , P. H. A. van der Putten , Jeroen Voeten On the Fundamental Design Gap in Terabit per Second Packet Switching. [Citation Graph (0, 0)][DBLP ] Conf ] Rajendra S. Katti Speeding up Elliptic Cryptosystems Using a New Signed Binary Representation for Integers. [Citation Graph (0, 0)][DBLP ] Conf ] María C. Molina , José M. Mendías , Román Hermida Bit-Level Allocation of Multiple-Precision Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] 