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Conferences in DBLP

Euromicro Symposium on Digital Systems Design (dsd)
2002 (conf/dsd/2002)

  1. Ulf Schlichtmann
    Systems Are Made from Transistors: UDSM Technology Creates New Challenges for Library and IC Development. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:2-3 [Conf]
  2. Daranee Hormdee, Jim D. Garside, Stephen B. Furber
    An Asynchronous Victim Cache. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:4-11 [Conf]
  3. Ali Habibi, Sofiène Tahar, Adel Ghazel
    Formal Verification of a DSP Chip Using an Iterative Approach. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:12-19 [Conf]
  4. Kenneth B. Kent, Micaela Serra
    Hardware Architecture for Java in a Hardware/Software Co-Design of the Virtual Machine. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:20-27 [Conf]
  5. Jarno Vanne, Eero Aho, Kimmo Kuusilinna, Timo D. Hämäläinen
    Enhanced Configurable Parallel Memory Architecture. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:28-37 [Conf]
  6. Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst
    Recursive Bi-Partitioning of Netlists for Large Number of Partitions. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:38-44 [Conf]
  7. Ivan Milentijevic, Vladimir Ciric, Teufik Tokic, Oliver Vojinovic
    Folded Bit-Plane FIR Filter Architecture with Changeable Folding Factor. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:45-52 [Conf]
  8. Yinshui Xia, A. E. A. Almaini
    Best Polarity for Low Power XOR Gate Decomposition. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:53-59 [Conf]
  9. José Ignacio Hidalgo, Juan Lanchares, Aitor Ibarra, Román Hermida
    A Hybrid Evolutionary Algorithm for Multi-FPGA Systems Design. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:60-69 [Conf]
  10. Matías J. Garrido, César Sanz, Marcos Jiménez, Juan M. Meneses
    A Flexible Architecture for H.263 Video Coding. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:70-77 [Conf]
  11. Omar Mansour, Egbert Molenkamp, Thijs Krol
    The Synthesis of a Hardware Scheduler for Non-Manifest Loops. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:78-85 [Conf]
  12. Juha-Pekka Soininen, Antti Pelkonen, Jussi Roivainen
    Configurable Memory Organisation for Communication Applications. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:86-93 [Conf]
  13. Maik Boden, Jörg Schneider, Klaus Feske, Steffen Rülke
    Enhanced Reusability for SoC-Based HW/SW Co-Design. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:94-101 [Conf]
  14. Per Andersson, Krzysztof Kuchcinski, Klas Nordberg, Patrick Doherty
    Integrating a Computational Model and a Run Time System for Image Processing on a UAV. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:102-109 [Conf]
  15. Loe M. G. Feijs, Paul Gorissen, Joachim Trescher
    Specification and Simulation of Microprocessor Operations and Parallel Instructions. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:110-117 [Conf]
  16. Martyn Edwards, Benjamin Fozard
    Rapid Prototyping of Mixed Hardware and Software Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:118-125 [Conf]
  17. Ilia Oussorov, Wolfgang Raab, J. A. Ulrich Hachmann, Alex Kravtsov
    Integration of Instruction Set Simulators into SystemC High Level Models. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:126-131 [Conf]
  18. Bart D. Theelen, A. C. Verschueren
    Architecture Design of a Scalable Single-Chip Multi-Processor. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:132-139 [Conf]
  19. Ari Wahyudi, Amos Omondi
    Parallel Multimedia Processor Using Customised Infineon TriCores. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:140-147 [Conf]
  20. Manuel Lois Anido, Alexander Paar, Nader Bagherzadeh
    Improving the Operation Autonomy of SIMD Processing Elements by Using Guarded Instructions and Pseudo Branches. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:148-155 [Conf]
  21. Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff
    Implementation of a Streaming Execution Unit. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:156-165 [Conf]
  22. Josef Strnadel, Zdenek Kotásek
    Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:166-173 [Conf]
  23. Roman Goot, Ilya Levin, Sergei Ostanin
    Fault Latencies of Concurrent Checking FSMs. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:174-179 [Conf]
  24. Paul Amblard, Fabienne Lagnier, Michel Lévy
    Using Formal Tools to Study Complex Circuits Behaviour. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:180-186 [Conf]
  25. André Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatová, Thomas Hollstein, Wieslaw Kuzmicz, Zebo Peng
    Integrated Design and Test Generation Under Internet Based Environment MOSCITO. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:187-195 [Conf]
  26. Paul Wielage, Kees G. W. Goossens
    Networks on Silicon: Blessing or Nightmare? [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:196-200 [Conf]
  27. Peter Marwedel
    Embedded Software: How To Make It Efficient? [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:201-209 [Conf]
  28. Shoji Goto, Takashi Yamada, Norihisa Takayarna, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura
    A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:210-217 [Conf]
  29. D. Piso, José-Alejandro Piñeiro, Javier D. Bruguera
    Analysis of the Impact of Different Methods for Division/Square Root Computation in the Performance of a Superscalar Microprocessor. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:218-225 [Conf]
  30. Nadia Nedjah, Luiza de Macedo Mourelle
    Reconfigurable Hardware Implementation of Montgomery Modular Multiplication and Parallel Binary Exponentiation. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:226-235 [Conf]
  31. Dragan Jankovic, Radomir S. Stankovic, Rolf Drechsler
    Decision Diagram Optimization Using Copy Properties. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:236-243 [Conf]
  32. Jacqueline E. Rice, Jon C. Muzio
    Use of the Autocorrelation Function in the Classification of Switching Functions. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:244-251 [Conf]
  33. Aitor Ibarra, José M. Mendías, Juan Lanchares, José Ignacio Hidalgo, Román Hermida
    Optimization of Equational Specifications Using Genetic Techniques. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:252-258 [Conf]
  34. Pawel Kerntopf
    Synthesis of Multipurpose Reversible Logic Gates. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:259-267 [Conf]
  35. Domingo Benitez
    Performance of Remote FPGA-Based Coprocessors for Image-Processing Applications. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:268-275 [Conf]
  36. Oswaldo Cadenas, Graham M. Megson
    Improving mW/MHz Ratio in FPGAs Pipelined Designs. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:276-282 [Conf]
  37. M. A. Hannan Bin Azhar, Keith R. Dimond
    Design of an FPGA Based Adaptive Neural Controller for Intelligent Robot Navigation. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:283-290 [Conf]
  38. Ernest Jamro, Kazimierz Wiatr
    Constant Coefficient Convolution Implemented in FPGAs. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:291-298 [Conf]
  39. Peter Green, M. Vakondios, Martyn Edwards
    An Evaluation of an FPGA Run-Time Support System. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:299-307 [Conf]
  40. José M. Mendías, Román Hermida, María C. Molina, Olga Peñalba
    Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:308-315 [Conf]
  41. Azeddien M. Sllame, Vladimír Drábek
    An Efficient List-Based Scheduling Algorithm for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:316-323 [Conf]
  42. Olga Peñalba, José M. Mendías, Román Hermida
    Source Code Transformation to Improve Conditional Hardware Reuse. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:324-331 [Conf]
  43. Zeljko Vujovic
    Work Out of the Algorithm Based on A-Mod for Detection Borderlines in Images Provided by the Intravascular Ultrasound System (IVUS) with 64 Transducers. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:332-336 [Conf]
  44. Rolf Drechsler, Daniel Große
    Reachability Analysis for Formal Verification of SystemC. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:337-340 [Conf]
  45. Toshinori Sato, Itsujiro Arita
    Simplifying Instruction Issue Logic in Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:341-346 [Conf]
  46. Martin Feldhofer, Thomas Trathnigg, Bernd Schnitzer
    A Self-Timed Arithmetic Unit for Elliptic Curve Cryptography. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:347-350 [Conf]
  47. Giuseppe Notarangelo, Marco Gibilaro, Francesco Pappalardo 0002, Agatino Pennisi, Gaetano Palumbo
    Low Power Strategy for a TFT Controller. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:351-354 [Conf]
  48. Khushwinder Jasrotia, Jianwen Zhu
    Hardware Implementation of a Memory Allocator. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:355-358 [Conf]
  49. Mariusz Chyzy, Witold Kosinski
    Evolutionary Algorithm for State Assignment of Finite State Machines. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:359-363 [Conf]
  50. Ronny Frevert, Steffen Rülke, Torsten Schäfer, Frank Dresig
    Use of HDL Code Checkers to Support the IP Entrance Check - A Requirement Analysis. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:364-370 [Conf]
  51. M. Verhappen, P. H. A. van der Putten, Jeroen Voeten
    On the Fundamental Design Gap in Terabit per Second Packet Switching. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:371-379 [Conf]
  52. Rajendra S. Katti
    Speeding up Elliptic Cryptosystems Using a New Signed Binary Representation for Integers. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:380-384 [Conf]
  53. María C. Molina, José M. Mendías, Román Hermida
    Bit-Level Allocation of Multiple-Precision Specifications. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:385-392 [Conf]
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002