Conferences in DBLP
Gordon J. Brebner Eccentric SoC Architectures as the Future Norm. [Citation Graph (0, 0)][DBLP ] Conf ] Axel Jantsch NoCs: A new Contract between Hardware and Software. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroto Yasuura Towards the Digitally Named World -Challenges for New Social Infrastructures based on Information Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Sung Woo Chung , Hyong-Shik Kim , Chu Shik Jhon Distance-aware L2 Cache Organizations for Scalable Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ben H. H. Juurlink Unified Dual Data Caches. [Citation Graph (0, 0)][DBLP ] Conf ] Lin Li , Narayanan Vijaykrishnan , Mahmut T. Kandemir , Mary Jane Irwin , Ismail Kadayif CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Hafiz Md. Hasan Babu , Md. Rafiqul Islam , Ahsan Raja Chowdhury , Syed Mostahed Ali Chowdhury Reversible Logic Synthesis for Minimization of Full-Adder Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Loïc Pontani , Denis Dupont Scheduling and Assignment for Real-time Embedded Systems with Resource Contention. [Citation Graph (0, 0)][DBLP ] Conf ] Nina Yevtushenko , Svetlana Zharikova , Maria Vetrova Multi Component Digital Circuit Optimization by Solving FSM Equations. [Citation Graph (0, 0)][DBLP ] Conf ] P. Srivatsan , P. B. Sudarshan , P. P. Bhaskaran DYNORA: A New Caching Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmet Akkas , Michael J. Schulte A Quadruple Precision and Dual Double Precision Floating-Point Multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] Rainer Schaffer , Renate Merker , Francky Catthoor Causality Constraints for Processor Architectures with Sub-Word Parallelism. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Bertola , Guy Bois A methodology for the design of AHB bus master wrappers. [Citation Graph (0, 0)][DBLP ] Conf ] Winthir Brunnbauer , Thomas Wild , Jürgen Foag , Nuria Pazos A Constructive Algorithm with Look-Ahead for Mapping and Scheduling of Task Graphs with Conditional Edges. [Citation Graph (0, 0)][DBLP ] Conf ] Mariusz Rawski , Henry Selvaraj , Tadeusz Luba An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA Devices. [Citation Graph (0, 0)][DBLP ] Conf ] James E. Stine , Oliver M. Duverne Variations on Truncated Multiplication. [Citation Graph (0, 0)][DBLP ] Conf ] Manoj Kumar Jain , M. Balakrishnan , Anshul Kumar Exploring Storage Organization in ASIP Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Ricardo Chaves , Leonel Sousa RDSP: A RISC DSP based on Residue Number System. [Citation Graph (0, 0)][DBLP ] Conf ] Gregorio Cappuccino Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Ling Wang , Henry Selvaraj A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple Voltages. [Citation Graph (0, 0)][DBLP ] Conf ] Lech Józwiak , Szymon Bieganski , Artur Chojnacki Information-driven Library-based Circuit Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Petrov , Alex Orailoglu Low-power Branch Target Buffer for Application-Specific Embedded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Philip K. F. Hölzenspies , Erik Schepers , Wouter Bach , Mischa Jonker , Bart Sikkes , Gerard J. M. Smit , Paul J. M. Havinga A Communication Model Based on an n-Dimensional Torus Architecture Using Deadlock-Free Wormhole Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Bera , Giovanni Danese , Ivo De Lotto , Francesco Leporati , Alvaro Spelgatti A Development and Simulation Environment for a Floating Point Operations FPGA Based Accelerator. [Citation Graph (0, 0)][DBLP ] Conf ] Tang Lei , Shashi Kumar A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Stephan Klaus , Sorin A. Huss A Novel Specification Model for IP-based Design. [Citation Graph (0, 0)][DBLP ] Conf ] George Kornaros , Theofanis Orphanoudakis , Nicholaos Zervos An Efficient Implementation of Fair Load Balancing over Multi-CPU SOC Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] S. Ramachandran , S. Srinivasan Design and FPGA Implementation of a Video Scalar with on-chip reduced memory utilization. [Citation Graph (0, 0)][DBLP ] Conf ] Yang Qu , Juha-Pekka Soininen Estimating the Utilization of Embedded FPGA Co-Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Valery Sklyarov , Iouliia Skliarova , Arnaldo Oliveira , António de Brito Ferrari A Dynamically Reconfigurable Accelerator for Operations over Boolean and Ternary Vectors. [Citation Graph (0, 0)][DBLP ] Conf ] Mario Hilgemeier , Nicole Drechsler , Rolf Drechsler Fast Heuristics for the Edge Coloring of Large Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Amirali Baniasadi Back-End Dynamic Resource Allocation Heuristics for Power-Aware High-Performance Clustered Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Michal Pleban , Hubert Niewiadomski , Piotr Buciak , Henry Selvaraj , Piotr Sapiecha , Tadeusz Luba NOAH, a tool for argument reduction, serial and parallel decomposition of decision tables. [Citation Graph (0, 0)][DBLP ] Conf ] Valery Sklyarov , Iouliia Skliarova , Pedro Almeida , Manuel Almeida Design Tools and Reusable Libraries for FPGA-Based Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Karthikeyan Bhasyam , Kia Bazargan HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Fatih Kocan Reconfigurable Randomized K-way Graph Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Bharath Radhakrishnan , Muthukumar Venkatesan Multiple Voltage and Frequency Scheduling for Power Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Chichyang Chen , Rui-Lin Chen , Ming-Hwa Sheu A Fast Additive Normalization Method for Exponential Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Mark G. Arnold A VLIW Architecture for Logarithmic Arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Ruzicka Testable Design Verification Using Petri Nets. [Citation Graph (0, 0)][DBLP ] Conf ] Ozgur Sinanoglu , Alex Orailoglu Hierarchical Constraint Conscious RT-level Test Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Goran Panic , Daniel Dietterle , Zoran Stamenkovic , Klaus Tittelbach-Helmrich A System-on-Chip Implementation of the IEEE 802.11a MAC Layer. [Citation Graph (0, 0)][DBLP ] Conf ] Behzad Akbarpour , Sofiène Tahar The Application of Formal Verification to SPW Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Filip Traugott , Kim Andersson , Andreas Löfgren , Lennart Lindh Successful Prototyping of a Real-Time Hardware Based Terrain Navigation Correlator Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Margarita Amor , Montserrat Bóo , Ángel del Río , Michael Wand , Wolfgang Straßer A New Algorithm for High-Speed Projection in Point Rendering Applications. [Citation Graph (0, 0)][DBLP ] Conf ] M. De Marinis , Luca Fanucci , A. Giambastiani , Alessandro Renieri , A. Rocchi , Christian Rosadini , Claudio Sicilia , Daniele Sicilia Sensor Platform Design for Automotive Applications. [Citation Graph (0, 0)][DBLP ] Conf ] R. Fernández-Ramos , J. Romero-Sánchez , F. Ríos-Gómez , J. Martín-Canales Modelling and Simulation of a Digital IC System Using SimulPet: Application to a Speech Coding Communication IC. [Citation Graph (0, 0)][DBLP ] Conf ] Sandro Neves Soares , Flávio Rech Wagner T&D-Bench+ - A Software Environment for Modeling and Simulation of State-of-the-Art Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Hahanov , Raimund Ubar , Stanley Hyduke Back-Traced Deductive-Parallel Fault Simulation for Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Adam Golda , Andrzej Kos Temperature Influence on Power Consumption and Time Delay. [Citation Graph (0, 0)][DBLP ] Conf ] O. Benderli , Yusuf Çagatay Tekmen , A. Neslin Ismailoglu A Real Time, Low Latency, FPGA Implementation of the 2-D Discrete Wavelet Transformation for Streaming Image Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Om Prakash Gangwal , Johan Janssen , Selliah Rathnam , Erwin B. Bellers , Marc Duranton Understanding Video Pixel Processing Applications for Flexible Implementations. [Citation Graph (0, 0)][DBLP ] Conf ] Nizamettin Aydin , Tughrul Arslan , David R. S. Cumming Power/Area Analysis and Optimization of a DS-SS receiver for an Integrated Sensor Microsystem. [Citation Graph (0, 0)][DBLP ] Conf ] Masanori Muroyama , Akihiko Hyodo , Takanori Okuma , Hiroto Yasuura A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits. [Citation Graph (0, 0)][DBLP ] Conf ] Armin Wellig , Julien Zory Framed Complexity Analysis in SystemC for Multi-level Design Space Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] S. T. G. S. Ramakrishna , H. S. Jamadagni Analytical Bounds on the Threads in IXP1200 Network Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Gregor Papa , Jurij Silc Concurrent Operation Scheduling and Unit Allocation with an Evolutionary Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Juan Manuel García Chamizo , Jerónimo Mora Pascual , Higinio Mora Mora Exact Numerical Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Nadia Nedjah , Luiza de Macedo Mourelle Stochastic Reconfigurable Hardware for Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Radoslaw Czarnecki , Stanislaw Deniziak , Krzysztof Sapiecha An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Jouni Riihimäki , Väinö Helminen , Kimmo Kuusilinna , Timo D. Hämäläinen Distributing SoC Simulations over a Network of Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Petr Fiser , Jan Hlavicka , Hana Kubatova FC-Min: A Fast Multi-Output Boolean Minimizer. [Citation Graph (0, 0)][DBLP ] Conf ] Václav Dvorák , Vladimír Kutálek A Methodology for Designing Communication Architectures for Multiprocessor SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Guangyu Chen , Ismail Kadayif , Wei Zhang 0002 , Mahmut T. Kandemir , Ibrahim Kolcu , Ugur Sezer Compiler-Directed Management of Instruction Accesses. [Citation Graph (0, 0)][DBLP ] Conf ] Zdenek Kotásek , Daniel Mika , Josef Strnadel Test scheduling for embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Petrov , Alex Orailoglu Customizable Embedded Processor Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] 