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Conferences in DBLP

Euromicro Symposium on Digital Systems Design (dsd)
2003 (conf/dsd/2003)

  1. Gordon J. Brebner
    Eccentric SoC Architectures as the Future Norm. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:2-9 [Conf]
  2. Axel Jantsch
    NoCs: A new Contract between Hardware and Software. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:10-16 [Conf]
  3. Hiroto Yasuura
    Towards the Digitally Named World -Challenges for New Social Infrastructures based on Information Technologies. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:17-22 [Conf]
  4. Sung Woo Chung, Hyong-Shik Kim, Chu Shik Jhon
    Distance-aware L2 Cache Organizations for Scalable Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:24-32 [Conf]
  5. Ben H. H. Juurlink
    Unified Dual Data Caches. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:33-40 [Conf]
  6. Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Ismail Kadayif
    CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:41-49 [Conf]
  7. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury, Syed Mostahed Ali Chowdhury
    Reversible Logic Synthesis for Minimization of Full-Adder Circuit. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:50-54 [Conf]
  8. Loïc Pontani, Denis Dupont
    Scheduling and Assignment for Real-time Embedded Systems with Resource Contention. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:55-61 [Conf]
  9. Nina Yevtushenko, Svetlana Zharikova, Maria Vetrova
    Multi Component Digital Circuit Optimization by Solving FSM Equations. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:62-69 [Conf]
  10. P. Srivatsan, P. B. Sudarshan, P. P. Bhaskaran
    DYNORA: A New Caching Technique. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:70-75 [Conf]
  11. Ahmet Akkas, Michael J. Schulte
    A Quadruple Precision and Dual Double Precision Floating-Point Multiplier. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:76-81 [Conf]
  12. Rainer Schaffer, Renate Merker, Francky Catthoor
    Causality Constraints for Processor Architectures with Sub-Word Parallelism. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:82-89 [Conf]
  13. Marc Bertola, Guy Bois
    A methodology for the design of AHB bus master wrappers. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:90-97 [Conf]
  14. Winthir Brunnbauer, Thomas Wild, Jürgen Foag, Nuria Pazos
    A Constructive Algorithm with Look-Ahead for Mapping and Scheduling of Task Graphs with Conditional Edges. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:98-103 [Conf]
  15. Mariusz Rawski, Henry Selvaraj, Tadeusz Luba
    An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA Devices. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:104-111 [Conf]
  16. James E. Stine, Oliver M. Duverne
    Variations on Truncated Multiplication. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:112-119 [Conf]
  17. Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
    Exploring Storage Organization in ASIP Synthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:120-127 [Conf]
  18. Ricardo Chaves, Leonel Sousa
    RDSP: A RISC DSP based on Residue Number System. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:128-137 [Conf]
  19. Gregorio Cappuccino
    Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:138-143 [Conf]
  20. Ling Wang, Henry Selvaraj
    A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple Voltages. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:144-147 [Conf]
  21. Lech Józwiak, Szymon Bieganski, Artur Chojnacki
    Information-driven Library-based Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:148-157 [Conf]
  22. Peter Petrov, Alex Orailoglu
    Low-power Branch Target Buffer for Application-Specific Embedded Processors. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:158-165 [Conf]
  23. Philip K. F. Hölzenspies, Erik Schepers, Wouter Bach, Mischa Jonker, Bart Sikkes, Gerard J. M. Smit, Paul J. M. Havinga
    A Communication Model Based on an n-Dimensional Torus Architecture Using Deadlock-Free Wormhole Routing. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:166-172 [Conf]
  24. Marco Bera, Giovanni Danese, Ivo De Lotto, Francesco Leporati, Alvaro Spelgatti
    A Development and Simulation Environment for a Floating Point Operations FPGA Based Accelerator. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:173-179 [Conf]
  25. Tang Lei, Shashi Kumar
    A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:180-189 [Conf]
  26. Stephan Klaus, Sorin A. Huss
    A Novel Specification Model for IP-based Design. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:190-196 [Conf]
  27. George Kornaros, Theofanis Orphanoudakis, Nicholaos Zervos
    An Efficient Implementation of Fair Load Balancing over Multi-CPU SOC Architectures. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:197-205 [Conf]
  28. S. Ramachandran, S. Srinivasan
    Design and FPGA Implementation of a Video Scalar with on-chip reduced memory utilization. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:206-213 [Conf]
  29. Yang Qu, Juha-Pekka Soininen
    Estimating the Utilization of Embedded FPGA Co-Processor. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:214-221 [Conf]
  30. Valery Sklyarov, Iouliia Skliarova, Arnaldo Oliveira, António de Brito Ferrari
    A Dynamically Reconfigurable Accelerator for Operations over Boolean and Ternary Vectors. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:222-229 [Conf]
  31. Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler
    Fast Heuristics for the Edge Coloring of Large Graphs. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:230-239 [Conf]
  32. Amirali Baniasadi
    Back-End Dynamic Resource Allocation Heuristics for Power-Aware High-Performance Clustered Architectures. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:240-247 [Conf]
  33. Michal Pleban, Hubert Niewiadomski, Piotr Buciak, Henry Selvaraj, Piotr Sapiecha, Tadeusz Luba
    NOAH, a tool for argument reduction, serial and parallel decomposition of decision tables. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:248-254 [Conf]
  34. Valery Sklyarov, Iouliia Skliarova, Pedro Almeida, Manuel Almeida
    Design Tools and Reusable Libraries for FPGA-Based Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:255-263 [Conf]
  35. Karthikeyan Bhasyam, Kia Bazargan
    HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:264-271 [Conf]
  36. Fatih Kocan
    Reconfigurable Randomized K-way Graph Partitioning. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:272-278 [Conf]
  37. Bharath Radhakrishnan, Muthukumar Venkatesan
    Multiple Voltage and Frequency Scheduling for Power Minimization. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:279-285 [Conf]
  38. Chichyang Chen, Rui-Lin Chen, Ming-Hwa Sheu
    A Fast Additive Normalization Method for Exponential Computation. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:286-293 [Conf]
  39. Mark G. Arnold
    A VLIW Architecture for Logarithmic Arithmetic. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:294-303 [Conf]
  40. Richard Ruzicka
    Testable Design Verification Using Petri Nets. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:304-311 [Conf]
  41. Ozgur Sinanoglu, Alex Orailoglu
    Hierarchical Constraint Conscious RT-level Test Generation. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:312-318 [Conf]
  42. Goran Panic, Daniel Dietterle, Zoran Stamenkovic, Klaus Tittelbach-Helmrich
    A System-on-Chip Implementation of the IEEE 802.11a MAC Layer. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:319-324 [Conf]
  43. Behzad Akbarpour, Sofiène Tahar
    The Application of Formal Verification to SPW Designs. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:325-333 [Conf]
  44. Filip Traugott, Kim Andersson, Andreas Löfgren, Lennart Lindh
    Successful Prototyping of a Real-Time Hardware Based Terrain Navigation Correlator Algorithm. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:334-337 [Conf]
  45. Margarita Amor, Montserrat Bóo, Ángel del Río, Michael Wand, Wolfgang Straßer
    A New Algorithm for High-Speed Projection in Point Rendering Applications. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:338-345 [Conf]
  46. M. De Marinis, Luca Fanucci, A. Giambastiani, Alessandro Renieri, A. Rocchi, Christian Rosadini, Claudio Sicilia, Daniele Sicilia
    Sensor Platform Design for Automotive Applications. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:346-355 [Conf]
  47. R. Fernández-Ramos, J. Romero-Sánchez, F. Ríos-Gómez, J. Martín-Canales
    Modelling and Simulation of a Digital IC System Using SimulPet: Application to a Speech Coding Communication IC. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:356-361 [Conf]
  48. Sandro Neves Soares, Flávio Rech Wagner
    T&D-Bench+ - A Software Environment for Modeling and Simulation of State-of-the-Art Processors. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:362-369 [Conf]
  49. Vladimir Hahanov, Raimund Ubar, Stanley Hyduke
    Back-Traced Deductive-Parallel Fault Simulation for Digital Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:370-377 [Conf]
  50. Adam Golda, Andrzej Kos
    Temperature Influence on Power Consumption and Time Delay. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:378-383 [Conf]
  51. O. Benderli, Yusuf Çagatay Tekmen, A. Neslin Ismailoglu
    A Real Time, Low Latency, FPGA Implementation of the 2-D Discrete Wavelet Transformation for Streaming Image Applications. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:384-391 [Conf]
  52. Om Prakash Gangwal, Johan Janssen, Selliah Rathnam, Erwin B. Bellers, Marc Duranton
    Understanding Video Pixel Processing Applications for Flexible Implementations. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:392-401 [Conf]
  53. Nizamettin Aydin, Tughrul Arslan, David R. S. Cumming
    Power/Area Analysis and Optimization of a DS-SS receiver for an Integrated Sensor Microsystem. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:402-407 [Conf]
  54. Masanori Muroyama, Akihiko Hyodo, Takanori Okuma, Hiroto Yasuura
    A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:408-415 [Conf]
  55. Armin Wellig, Julien Zory
    Framed Complexity Analysis in SystemC for Multi-level Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:416-425 [Conf]
  56. S. T. G. S. Ramakrishna, H. S. Jamadagni
    Analytical Bounds on the Threads in IXP1200 Network Processor. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:426-429 [Conf]
  57. Gregor Papa, Jurij Silc
    Concurrent Operation Scheduling and Unit Allocation with an Evolutionary Technique. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:430-433 [Conf]
  58. Juan Manuel García Chamizo, Jerónimo Mora Pascual, Higinio Mora Mora
    Exact Numerical Processing. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:434-437 [Conf]
  59. Nadia Nedjah, Luiza de Macedo Mourelle
    Stochastic Reconfigurable Hardware for Neural Networks. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:438-442 [Conf]
  60. Radoslaw Czarnecki, Stanislaw Deniziak, Krzysztof Sapiecha
    An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:443-446 [Conf]
  61. Jouni Riihimäki, Väinö Helminen, Kimmo Kuusilinna, Timo D. Hämäläinen
    Distributing SoC Simulations over a Network of Computers. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:447-450 [Conf]
  62. Petr Fiser, Jan Hlavicka, Hana Kubatova
    FC-Min: A Fast Multi-Output Boolean Minimizer. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:451-454 [Conf]
  63. Václav Dvorák, Vladimír Kutálek
    A Methodology for Designing Communication Architectures for Multiprocessor SoCs. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:455-458 [Conf]
  64. Guangyu Chen, Ismail Kadayif, Wei Zhang 0002, Mahmut T. Kandemir, Ibrahim Kolcu, Ugur Sezer
    Compiler-Directed Management of Instruction Accesses. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:459-462 [Conf]
  65. Zdenek Kotásek, Daniel Mika, Josef Strnadel
    Test scheduling for embedded systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:463-467 [Conf]
  66. Peter Petrov, Alex Orailoglu
    Customizable Embedded Processor Architectures. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:468-475 [Conf]
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002