Conferences in DBLP
Copyright. [Citation Graph (0, 0)][DBLP ] Conf ] Conference Committees. [Citation Graph (0, 0)][DBLP ] Conf ] Message from the Program Chair. [Citation Graph (0, 0)][DBLP ] Conf ] Title Page. [Citation Graph (0, 0)][DBLP ] Conf ] Melvin A. Breuer Multi-media Applications and Imprecise Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Timmermann Wireless Sensor Systems - Constraints and Opportunities. [Citation Graph (0, 0)][DBLP ] Conf ] Milos Krstic , Eckhard Grass BIST Technique for GALS Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Tun Li , Yang Guo , GongJie Liu , Sikun Li Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Arnaud Cuccuru , Robert de Simone , Thierry Saunier , Günther Siegel , Yves Sorel P2I: An Innovative MDA Methodology for Embedded Real-Time System. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Wu , Bashir M. Al-Hashimi , Marcus T. Schmitz , Petru Eles Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Lindahl , Lars Bengtsson A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit Representation. [Citation Graph (0, 0)][DBLP ] Conf ] Mark G. Arnold Approximating Trigonometric Functions with the Laws of Sines and Cosines using the Logarithmic Number System. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Filter , Hana Kubatova Improvement of the Fault Coverage of the Pseudo-Random Phase in Column-Matching BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Lucía Costas , Juan J. Rodríguez-Andina Characterization of Wavelet-Based Image Coding Systems for Algorithmic Fault Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Jaan Raik , Peeter Ellervee , Valentin Tihhomirov , Raimund Ubar Improved Fault Emulation for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Joachim Sudbrock , Jaan Raik , Raimund Ubar , Wieslaw Kuzmicz , Witold A. Pleskacz Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Zhiyuan He , Gert Jervan , Zebo Peng , Petru Eles Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Nabil Abdelli , Pierre Bomel , Emmanuel Casseau , A.-M. Fouilliart , Christophe Jégo , Philippe Kajfasz , Bertrand Le Gal , Nathalie Le Heno Hardware Virtual Components Compliant with Communication System Standards. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre Bomel , Nabil Abdelli , Eric Martin , A.-M. Fouilliart , Emmanuel Boutillon , Philippe Kajfasz High-Level Synthesis in Latency Insensitive System Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Tero Vallius , Juha Röning Embedded Object Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Soujanna Sarkar , Subash G. Chandar An Effective Framework for Enabling the Reuse of External Soft IP. [Citation Graph (0, 0)][DBLP ] Conf ] Dariusz Kania , Józef Kulisz , Adam Milik A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs. [Citation Graph (0, 0)][DBLP ] Conf ] Md. Sumon Shahriar , A. R. Mustafa , Chowdhury Farhan Ahmed , Abu Ahmed Ferdaus , A. N. M. Zaheduzzaman , Shahed Anwar , Hafiz Md. Hasan Babu An Advanced Minimization Technique for Multiple Valued Multiple Output Logic Expressions Using LUT and Realization Using Current Mode CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Czerwinski , Dariusz Kania State Assignment for PAL-based CPLDs. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Ciric , Ivan Milentijevic Coefficient Bit Reordering Method for Configurable FIR Filtering on Folded Bit-plane Array. [Citation Graph (0, 0)][DBLP ] Conf ] Krzysztof S. Berezowski , Sarma B. K. Vrudhula Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series. [Citation Graph (0, 0)][DBLP ] Conf ] Panu Hämäläinen , Jari Heikkinen , Marko Hännikäinen , Timo D. Hämäläinen Design of Transport Triggered Architecture Processors for Wireless Encryption. [Citation Graph (0, 0)][DBLP ] Conf ] C. Siu , Soraya Kasnavi , Kris Iniewski , F. Nabki RF CMOS Circuits for Ad-Hoc Networks and Wearable Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Petri Kukkala , Marko Hännikäinen , Timo D. Hämäläinen Co-simulation of Wireless Local Area Network Terminals with Protocol Software Implemented in SDL. [Citation Graph (0, 0)][DBLP ] Conf ] S. Jayapal , S. Ramachandran , R. Bhutada , Yiannos Manoli Optimization of Electronic Power Consumption in Wireless Sensor Nodes. [Citation Graph (0, 0)][DBLP ] Conf ] Danielly Cruz , Edna Barros Vital Signs Remote Management System for PDAs. [Citation Graph (0, 0)][DBLP ] Conf ] Tun Li , Dan Zhu , Yang Guo , GongJie Liu , Sikun Li MA2TG: A Functional Test Program Generator for Microprocessor Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco Duarte , José Machado da Silva , José Carlos Alves , G. A. Pinho , José Silva Matos A processor for testing mixed-signal cores in System-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Eduardas Bareisa , Vacius Jusas , Kestutis Motiejunas , Rimantas Seinauskas Functional Test Generation Remote Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Karlsson , Petru Eles , Zebo Peng Validation of Embedded Systems Using Formal Method Aided Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Massimo Rovini , Nicola E. L'Insalata , Francesco Rossi , Luca Fanucci VLSI Design of a High-Throughput Multi-Rate Decoder for Structured LDPC Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Luciano Volcan Agostini , Roger Endrigo Carvalho Porto , Sergio Bampi , Ivan Saraiva Silva A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG Compressor. [Citation Graph (0, 0)][DBLP ] Conf ] Jin Hwan Park Reconfigurable Parallel Approximate String Matching on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Salvatore Vitabile , Vincenzo Conti , Fulvio Gennaro , Filippo Sorbello Efficient MLP Digital Implementation on FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Freeman , Jim Austin Designing a Binary Neural Network Co-processor. [Citation Graph (0, 0)][DBLP ] Conf ] Hamid Safizadeh , Hamid Noori , Mehdi Sedighi , Ali Jahanian , Neda Zolfaghari Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Nadia Nedjah , Luiza de Macedo Mourelle Massively Parallel Hardware Architecture for Genetic Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Oswaldo Cadenas , Graham M. Megson , Daniel Jones Implementation of a block based neural branch predictor. [Citation Graph (0, 0)][DBLP ] Conf ] Stanley Hyduke , Vladimir Hahanov , Volodymyr Obrizan , Olesya Guz PRUS - Processor Network for Digital Circuit Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Seppo Virtanen , Jani Paakkulainen , Tero Nurmi Capturing Processor Architectures from Protocol Processing Applications: a Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Zhaojun Wo , Israel Koren , Maciej J. Ciesielski Yield-aware Floorplanning. [Citation Graph (0, 0)][DBLP ] Conf ] Kashif Virk , Jan Madsen , Andreas Vad Lorentzen , Martin Leopold , Philippe Bonnet Design of A Development Platform for HW/SW Codesign ofWireless Integrated Sensor Nodes. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Ghiassi , Mohammad M. M. Rad , Mohammad S. Nikjoo , Ali Hesam Mohseni , Babak Hossein Khalaj An Efficient MAC Protocol for Sensor Network Considering Energy Consumption and Information Retrieval Pattern. [Citation Graph (0, 0)][DBLP ] Conf ] Mikko Kohvakka , Marko Hännikäinen , Timo D. Hämäläinen Wireless Sensor Network Implementation for Industrial Linear Position Metering. [Citation Graph (0, 0)][DBLP ] Conf ] Mária Fischerová , Martin Simlastík MemBIST Applet for Learning Principles of Memory Testing and Generating Memory BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Miguel Pereira , Enrique Soto , Juan J. Rodríguez-Andina , F. Javier González-Castaño High-Level Modelling and Detection of the Faulty Behaviour of VOQ Switches under Balanced Traffic. [Citation Graph (0, 0)][DBLP ] Conf ] Piotr Patronik Delay Testability Properties of Circuits Implementing Threshold and Symmetric Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto R. Osorio , Javier D. Bruguera A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder. [Citation Graph (0, 0)][DBLP ] Conf ] Pedro Trancoso , Maria Charalambous Exploring Graphics Processor Performance for General Purpose Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth B. Kent , Sharon Van Schaick , Jacqueline E. Rice , Patricia A. Evans Hardware-Based Implementation of the Common Approximate Substring Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Sergio Saponara , Michele Cassiano , Stefano Marsi , Riccardo Coen , Luca Fanucci Cost-effective VLSI Design of Non Linear Image Processing Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Per Andersson , Krzysztof Kuchcinski Java to Hardware Compilation for non Data Flow Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Ka L. Man Formal Communication Semantics of SystemCFL . [Citation Graph (0, 0)][DBLP ] Conf ] Sérgio Martins , José Carlos Alves A high-level tool for the design of custom image processing systems. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolay Kavaldjiev , Gerard J. M. Smit , Pierre G. Jansen Throughput of Streaming Applications Running on a Multiprocessor Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Wolinski , Krzysztof Kuchcinski A Constraints Programming Approach for Fabric Cell Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Yang Qu , Kari Tiensyrjä , Juha-Pekka Soininen SystemC-based Design Methodology for Reconfigurable System-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Farhad Mehdipour , Morteza Saheb Zamani , Mehdi Sedighi Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ghaffari Fakhreddine , Michel Auguin , Abid Mohamed , Benjemaa Maher An Adaptive On-Line HW/SW Partitioning for Soft Real Time Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Miguel L. Silva , João Canas Ferreira Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Sander Stuijk , Twan Basten , Bart Mesman , Marc Geilen Predictable embedding of large data structures in multiprocessor networks-on-chip. [Citation Graph (0, 0)][DBLP ] Conf ] F. Rivera , Milagros Fernández , Nader Bagherzadeh An Approach to Execute Conditional Branches onto SIMD Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Anders Larsson , Erik Larsson , Petru Eles , Zebo Peng Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Artur Jutman , Jaan Raik , Raimund Ubar , V. Vislogubov An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Josef Strnadel , Zdenek Kotásek Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies. [Citation Graph (0, 0)][DBLP ] Conf ] Oystein Gjermundnes , Einar J. Aas Remote Path Delay Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] V. Nelayev , V. Stempitsky , K. Kudin Internet-Based IC Technology Design and Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Dariusz Kania , Adam Milik , Józef Kulisz Decomposition of Multi-Output Functions for CPLDs. [Citation Graph (0, 0)][DBLP ] Conf ] Lech Józwiak , Szymon Bieganski High-quality Sub-function Construction in the Information-driven Circuit Synthesis with Gates. [Citation Graph (0, 0)][DBLP ] Conf ] Mariusz Rawski , Pawel Tomaszewicz , Henry Selvaraj , Tadeusz Luba Efficient Implementation of Digital Filters with Use of Advanced Synthesis Methods Targeted FPGA Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Tsutomu Sasao , Yukihiro Iguchi , Takahiro Suzuki On LUT Cascade Realizations of FIR Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Pedro Trancoso Dynamic Split: Flexible Border Between Instruction and Data Cache. [Citation Graph (0, 0)][DBLP ] Conf ] Arnaldo Oliveira , Valery Sklyarov , António de Brito Ferrari ARPA - A Technology Independent and Synthetizable System-on-Chip Model for Real-Time Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Danilo Pani , Giuseppe Passino , Luigi Raffo Run-time Adaptive Resources Allocation and Balancing on Nanoprocessors Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] 