The SCEAS System
Navigation Menu

Conferences in DBLP

Euromicro Symposium on Digital Systems Design (dsd)
2005 (conf/dsd/2005)

  1. Copyright. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:- [Conf]

  2. Conference Committees. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:- [Conf]

  3. Message from the Program Chair. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:- [Conf]

  4. Title Page. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:- [Conf]
  5. Melvin A. Breuer
    Multi-media Applications and Imprecise Computation. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:2-7 [Conf]
  6. Dirk Timmermann
    Wireless Sensor Systems - Constraints and Opportunities. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:8- [Conf]
  7. Milos Krstic, Eckhard Grass
    BIST Technique for GALS Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:10-16 [Conf]
  8. Tun Li, Yang Guo, GongJie Liu, Sikun Li
    Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:17-25 [Conf]
  9. Arnaud Cuccuru, Robert de Simone, Thierry Saunier, Günther Siegel, Yves Sorel
    P2I: An Innovative MDA Methodology for Embedded Real-Time System. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:26-33 [Conf]
  10. Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz, Petru Eles
    Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:34-41 [Conf]
  11. Andreas Lindahl, Lars Bengtsson
    A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit Representation. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:42-47 [Conf]
  12. Mark G. Arnold
    Approximating Trigonometric Functions with the Laws of Sines and Cosines using the Logarithmic Number System. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:48-55 [Conf]
  13. Peter Filter, Hana Kubatova
    Improvement of the Fault Coverage of the Pseudo-Random Phase in Column-Matching BIST. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:56-63 [Conf]
  14. Lucía Costas, Juan J. Rodríguez-Andina
    Characterization of Wavelet-Based Image Coding Systems for Algorithmic Fault Detection. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:64-71 [Conf]
  15. Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar
    Improved Fault Emulation for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:72-78 [Conf]
  16. Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz
    Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:79-82 [Conf]
  17. Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
    Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:83-87 [Conf]
  18. Nabil Abdelli, Pierre Bomel, Emmanuel Casseau, A.-M. Fouilliart, Christophe Jégo, Philippe Kajfasz, Bertrand Le Gal, Nathalie Le Heno
    Hardware Virtual Components Compliant with Communication System Standards. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:88-95 [Conf]
  19. Pierre Bomel, Nabil Abdelli, Eric Martin, A.-M. Fouilliart, Emmanuel Boutillon, Philippe Kajfasz
    High-Level Synthesis in Latency Insensitive System Methodology. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:96-101 [Conf]
  20. Tero Vallius, Juha Röning
    Embedded Object Architecture. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:102-107 [Conf]
  21. Soujanna Sarkar, Subash G. Chandar
    An Effective Framework for Enabling the Reuse of External Soft IP. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:108-113 [Conf]
  22. Dariusz Kania, Józef Kulisz, Adam Milik
    A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:114-121 [Conf]
  23. Md. Sumon Shahriar, A. R. Mustafa, Chowdhury Farhan Ahmed, Abu Ahmed Ferdaus, A. N. M. Zaheduzzaman, Shahed Anwar, Hafiz Md. Hasan Babu
    An Advanced Minimization Technique for Multiple Valued Multiple Output Logic Expressions Using LUT and Realization Using Current Mode CMOS. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:122-126 [Conf]
  24. Robert Czerwinski, Dariusz Kania
    State Assignment for PAL-based CPLDs. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:127-134 [Conf]
  25. Vladimir Ciric, Ivan Milentijevic
    Coefficient Bit Reordering Method for Configurable FIR Filtering on Folded Bit-plane Array. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:135-138 [Conf]
  26. Krzysztof S. Berezowski, Sarma B. K. Vrudhula
    Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:139-143 [Conf]
  27. Panu Hämäläinen, Jari Heikkinen, Marko Hännikäinen, Timo D. Hämäläinen
    Design of Transport Triggered Architecture Processors for Wireless Encryption. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:144-152 [Conf]
  28. C. Siu, Soraya Kasnavi, Kris Iniewski, F. Nabki
    RF CMOS Circuits for Ad-Hoc Networks and Wearable Computing. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:153-160 [Conf]
  29. Petri Kukkala, Marko Hännikäinen, Timo D. Hämäläinen
    Co-simulation of Wireless Local Area Network Terminals with Protocol Software Implemented in SDL. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:161-164 [Conf]
  30. S. Jayapal, S. Ramachandran, R. Bhutada, Yiannos Manoli
    Optimization of Electronic Power Consumption in Wireless Sensor Nodes. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:165-169 [Conf]
  31. Danielly Cruz, Edna Barros
    Vital Signs Remote Management System for PDAs. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:170-175 [Conf]
  32. Tun Li, Dan Zhu, Yang Guo, GongJie Liu, Sikun Li
    MA2TG: A Functional Test Program Generator for Microprocessor Verification. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:176-183 [Conf]
  33. Francisco Duarte, José Machado da Silva, José Carlos Alves, G. A. Pinho, José Silva Matos
    A processor for testing mixed-signal cores in System-on-Chip. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:184-191 [Conf]
  34. Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
    Functional Test Generation Remote Tool. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:192-195 [Conf]
  35. Daniel Karlsson, Petru Eles, Zebo Peng
    Validation of Embedded Systems Using Formal Method Aided Simulation. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:196-201 [Conf]
  36. Massimo Rovini, Nicola E. L'Insalata, Francesco Rossi, Luca Fanucci
    VLSI Design of a High-Throughput Multi-Rate Decoder for Structured LDPC Codes. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:202-209 [Conf]
  37. Luciano Volcan Agostini, Roger Endrigo Carvalho Porto, Sergio Bampi, Ivan Saraiva Silva
    A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG Compressor. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:210-213 [Conf]
  38. Jin Hwan Park
    Reconfigurable Parallel Approximate String Matching on FPGAs. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:214-217 [Conf]
  39. Salvatore Vitabile, Vincenzo Conti, Fulvio Gennaro, Filippo Sorbello
    Efficient MLP Digital Implementation on FPGA. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:218-222 [Conf]
  40. Michael Freeman, Jim Austin
    Designing a Binary Neural Network Co-processor. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:223-227 [Conf]
  41. Hamid Safizadeh, Hamid Noori, Mehdi Sedighi, Ali Jahanian, Neda Zolfaghari
    Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:227-230 [Conf]
  42. Nadia Nedjah, Luiza de Macedo Mourelle
    Massively Parallel Hardware Architecture for Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:231-234 [Conf]
  43. Oswaldo Cadenas, Graham M. Megson, Daniel Jones
    Implementation of a block based neural branch predictor. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:235-238 [Conf]
  44. Stanley Hyduke, Vladimir Hahanov, Volodymyr Obrizan, Olesya Guz
    PRUS - Processor Network for Digital Circuit Implementation. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:239-242 [Conf]
  45. Seppo Virtanen, Jani Paakkulainen, Tero Nurmi
    Capturing Processor Architectures from Protocol Processing Applications: a Case Study. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:243-246 [Conf]
  46. Zhaojun Wo, Israel Koren, Maciej J. Ciesielski
    Yield-aware Floorplanning. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:247-253 [Conf]
  47. Kashif Virk, Jan Madsen, Andreas Vad Lorentzen, Martin Leopold, Philippe Bonnet
    Design of A Development Platform for HW/SW Codesign ofWireless Integrated Sensor Nodes. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:254-260 [Conf]
  48. Y. Ghiassi, Mohammad M. M. Rad, Mohammad S. Nikjoo, Ali Hesam Mohseni, Babak Hossein Khalaj
    An Efficient MAC Protocol for Sensor Network Considering Energy Consumption and Information Retrieval Pattern. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:261-266 [Conf]
  49. Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen
    Wireless Sensor Network Implementation for Industrial Linear Position Metering. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:267-275 [Conf]
  50. Mária Fischerová, Martin Simlastík
    MemBIST Applet for Learning Principles of Memory Testing and Generating Memory BIST. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:276-281 [Conf]
  51. Miguel Pereira, Enrique Soto, Juan J. Rodríguez-Andina, F. Javier González-Castaño
    High-Level Modelling and Detection of the Faulty Behaviour of VOQ Switches under Balanced Traffic. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:282-288 [Conf]
  52. Piotr Patronik
    Delay Testability Properties of Circuits Implementing Threshold and Symmetric Functions. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:289-297 [Conf]
  53. Roberto R. Osorio, Javier D. Bruguera
    A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:298-305 [Conf]
  54. Pedro Trancoso, Maria Charalambous
    Exploring Graphics Processor Performance for General Purpose Applications. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:306-313 [Conf]
  55. Kenneth B. Kent, Sharon Van Schaick, Jacqueline E. Rice, Patricia A. Evans
    Hardware-Based Implementation of the Common Approximate Substring Algorithm. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:314-321 [Conf]
  56. Sergio Saponara, Michele Cassiano, Stefano Marsi, Riccardo Coen, Luca Fanucci
    Cost-effective VLSI Design of Non Linear Image Processing Filters. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:322-329 [Conf]
  57. Per Andersson, Krzysztof Kuchcinski
    Java to Hardware Compilation for non Data Flow Applications. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:330-337 [Conf]
  58. Ka L. Man
    Formal Communication Semantics of SystemCFL. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:338-345 [Conf]
  59. Sérgio Martins, José Carlos Alves
    A high-level tool for the design of custom image processing systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:346-349 [Conf]
  60. Nikolay Kavaldjiev, Gerard J. M. Smit, Pierre G. Jansen
    Throughput of Streaming Applications Running on a Multiprocessor Architecture. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:350-355 [Conf]
  61. Christophe Wolinski, Krzysztof Kuchcinski
    A Constraints Programming Approach for Fabric Cell Synthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:356-363 [Conf]
  62. Yang Qu, Kari Tiensyrjä, Juha-Pekka Soininen
    SystemC-based Design Methodology for Reconfigurable System-on-Chip. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:364-371 [Conf]
  63. Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi
    Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:372-378 [Conf]
  64. Ghaffari Fakhreddine, Michel Auguin, Abid Mohamed, Benjemaa Maher
    An Adaptive On-Line HW/SW Partitioning for Soft Real Time Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:379-382 [Conf]
  65. Miguel L. Silva, João Canas Ferreira
    Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAs. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:383-387 [Conf]
  66. Sander Stuijk, Twan Basten, Bart Mesman, Marc Geilen
    Predictable embedding of large data structures in multiprocessor networks-on-chip. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:388-396 [Conf]
  67. F. Rivera, Milagros Fernández, Nader Bagherzadeh
    An Approach to Execute Conditional Branches onto SIMD Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:396-402 [Conf]
  68. Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
    Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:403-411 [Conf]
  69. Artur Jutman, Jaan Raik, Raimund Ubar, V. Vislogubov
    An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:412-419 [Conf]
  70. Josef Strnadel, Zdenek Kotásek
    Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:420-427 [Conf]
  71. Oystein Gjermundnes, Einar J. Aas
    Remote Path Delay Fault Simulation. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:428-434 [Conf]
  72. V. Nelayev, V. Stempitsky, K. Kudin
    Internet-Based IC Technology Design and Simulation. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:435-441 [Conf]
  73. Dariusz Kania, Adam Milik, Józef Kulisz
    Decomposition of Multi-Output Functions for CPLDs. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:442-449 [Conf]
  74. Lech Józwiak, Szymon Bieganski
    High-quality Sub-function Construction in the Information-driven Circuit Synthesis with Gates. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:450-459 [Conf]
  75. Mariusz Rawski, Pawel Tomaszewicz, Henry Selvaraj, Tadeusz Luba
    Efficient Implementation of Digital Filters with Use of Advanced Synthesis Methods Targeted FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:460-466 [Conf]
  76. Tsutomu Sasao, Yukihiro Iguchi, Takahiro Suzuki
    On LUT Cascade Realizations of FIR Filters. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:467-475 [Conf]
  77. Pedro Trancoso
    Dynamic Split: Flexible Border Between Instruction and Data Cache. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:476-483 [Conf]
  78. Arnaldo Oliveira, Valery Sklyarov, António de Brito Ferrari
    ARPA - A Technology Independent and Synthetizable System-on-Chip Model for Real-Time Applications. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:484-491 [Conf]
  79. Danilo Pani, Giuseppe Passino, Luigi Raffo
    Run-time Adaptive Resources Allocation and Balancing on Nanoprocessors Arrays. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:492-499 [Conf]
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002