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Conferences in DBLP

Euromicro Symposium on Digital Systems Design (dsd)
2006 (conf/dsd/2006)

  1. Marc Duranton
    The Challenges for High Performance Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:3-7 [Conf]
  2. Roman Staszewski
    Digital RF. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:8- [Conf]
  3. Tohru Furuyama
    Deep Sub-100 nm Design Challenges. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:9-16 [Conf]
  4. Risto Suoranta
    New Directions in Mobile Device Architectures. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:17-26 [Conf]
  5. Klaus Waldschmidt
    Robustness in SOC Design. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:27-36 [Conf]
  6. Zhonghai Lu, Ingo Sander, Axel Jantsch
    Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:37-44 [Conf]
  7. Sander Stuijk, Twan Basten, Marc Geilen, Amir Hossein Ghamarian, Bart D. Theelen
    Resource-Efficient Routing and Scheduling of Time-Constrained Network-on-Chip Communication. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:45-52 [Conf]
  8. Frédéric Pétrot, Alain Greiner, Pascal Gomez
    On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:53-60 [Conf]
  9. Sara Román, Hortensia Mecha, Daniel Mozos, Julio Septién
    Partition Based Dynamic 2D HW Multitasking Management. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:61-70 [Conf]
  10. Akash Kumar, Bart Mesman, Henk Corporaal, Jef L. van Meerbergen, Yajun Ha
    Global Analysis of Resource Arbitration for MPSoC. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:71-78 [Conf]
  11. Alokika Dash, Peter Petrov
    Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:79-82 [Conf]
  12. Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen
    Comparison of GALS and Synchronous Architectures with MPEG-4 Video Encoder on Multiprocessor System-on-Chip FPGA. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:83-88 [Conf]
  13. Hanene Ben Fradj, Cécile Belleudy, Michel Auguin
    Multi-Bank Main Memory Architecture with Dynamic Voltage Frequency Scaling for System Energy Optimization. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:89-96 [Conf]
  14. Calin Ciordas, Andreas Hansson, Kees Goossens, Twan Basten
    A Monitoring-Aware Network-on-Chip Design Flow. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:97-106 [Conf]
  15. Reid B. Porter, Jan R. Frigo, Maya Gokhale, Christophe Wolinski, François Charot, Charles Wagner
    A Run-Time Re-configurable Parametric Architecture for Local Neighborhood Image Processing. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:107-115 [Conf]
  16. Michael Freeman, Thimal Jayasooriya
    A Hardware IP-Core for Information Retrieval. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:115-122 [Conf]
  17. Kyriakos Stavrou, Pedro Trancoso
    Thermal-Aware Scheduling: A Solution for Future Chip Multiprocessors Thermal Problems. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:123-126 [Conf]
  18. Michael Freeman
    Evaluating Dataflow and Pipelined Vector Processing Architectures for FPGA Co-processors. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:127-130 [Conf]
  19. Martin Delvai, Andreas Steininger
    Solving the Fundamental Problem of Digital Design - A Systematic Review of Design Methods. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:131-138 [Conf]
  20. Pavel Kubalík, Radek Dobias, Hana Kubatova
    Dependable Design for FPGA Based on Duplex System and Reconfiguration. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:139-145 [Conf]
  21. Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, Andrea Scorzoni
    A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA Blocks. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:146-154 [Conf]
  22. Ramachandruni Venkata Kamala, M. Sudhakar, M. B. Srinivas
    An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n). [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:155-159 [Conf]
  23. S. Momcilovic, Tiago Dias, Nuno Roma, Leonel Sousa
    Application Specific Instruction Set Processor for Adaptive Video Motion Estimation. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:160-167 [Conf]
  24. Haridimos T. Vergos, Costas Efstathiou
    Novel Modulo 2n + 1 Multipliers. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:168-175 [Conf]
  25. Eryk Laskowski, Marek Tudruj
    Embedded Parallel Systems Based on Dynamic Look-Ahead Reconfiguration in Redundant Communication Resources. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:176-179 [Conf]
  26. George Kornaros
    BCB: A Buffered CrossBar Switch Fabric Utilizing Shared Memory. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:180-188 [Conf]
  27. Fritz Mayer-Lindenberg
    Design and Application of a Scalable Embedded Systems' Architecture with an FPGA Based Operating Infrastucture. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:189-196 [Conf]
  28. Sylvain Collange, Jérémie Detrey, Florent de Dinechin
    Floating Point or LNS: Choosing the Right Arithmetic on an Aapplication Basis. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:197-203 [Conf]
  29. Jamel Tayeb, Smaïl Niar
    Adapting EPIC Architecture's Register Stack for Virtual Stack Machines. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:204-210 [Conf]
  30. Ahmet Akkas
    Dual-Mode Quadruple Precision Floating-Point Adder. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:211-220 [Conf]
  31. Pedro Trancoso
    Adaptive High-End Microprocessor for Power-Performance Efficiency. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:221-228 [Conf]
  32. Filipa Duarte, Stephan Wong
    Profiling Bluetooth and Linux on the Xilinx Virtex II Pro. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:229-235 [Conf]
  33. Viay Holimath, Javier D. Bruguera
    A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:236-239 [Conf]
  34. Sylvain Huet, Emmanuel Casseau, Olivier Pasquier
    A Computation Core for Communication Refinement of Digital Signal Processing Algorithms. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:240-250 [Conf]
  35. Martin Stáva, Ondrej Novák
    Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:251-256 [Conf]
  36. Petros Oikonomakos, Simon W. Moore
    An Asynchronous PLA with Improved Security Characteristics. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:257-264 [Conf]
  37. Giovanni Busonera, Salvatore Carta, Andrea Marongiu, Luigi Raffo
    Automatic Application Partitioning on FPGA/CPU Systems Based on Detailed Low-Level Information. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:265-268 [Conf]
  38. Roberto R. Osorio, Javier D. Bruguera
    A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:269-274 [Conf]
  39. Silvio Misera, Heinrich Theodor Vierhaus, Lars Breitenfeld, André Sieber
    A Mixed Language Fault Simulation of VHDL and SystemC. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:275-279 [Conf]
  40. Sébastien Le Beux, Philippe Marquet, Ouassila Labbani, Jean-Luc Dekeyser
    FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:280-287 [Conf]
  41. Ines Viskic, Rainer Dömer
    A Flexible, Syntax Independent Representation (SIR) for System Level Design Models. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:288-294 [Conf]
  42. Adam Smyk, Marek Tudruj
    Prototyping Parallel FDTD Programs by Macro Data Flow Graph Analysis. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:295-304 [Conf]
  43. Armando Sánchez-Peña, Pedro P. Carballo, Luz García, Antonio Núñez
    VIPACES, Verification Interface Primitives for the Development of AXI Compliant Elements and Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:305-312 [Conf]
  44. Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Peng
    Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems*. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:313-322 [Conf]
  45. Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas
    Transition Fault Test Reuse. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:323-330 [Conf]
  46. Muhammad Waseem, Ludovic Apvrille, Rabea Ameur-Boulifa, Sophie Coudert, Renaud Pacalet
    Abstract Application Modeling for System Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:331-337 [Conf]
  47. Gianluca Casarosa, Michele Apuzzo, Luca Fanucci, Bruno Sarti
    Characterization of the EMC Performances of the CAN Bus in a Typical System Bus Architecture for Small Satellites. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:338-345 [Conf]
  48. Liam Noonan, Colin Flanagan
    Utilising Evolutionary Approaches and Object Oriented Techniques for Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:346-352 [Conf]
  49. Jaan Raik, Raimund Ubar, Taavi Viilukas
    High-Level Decision Diagram based Fault Models for Targeting FSMs. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:353-358 [Conf]
  50. Ilya Levin, Vladimir Ostrovsky, Osnat Keren, Vladimir Sinelnikov
    Cascade Scheme for Concurrent Errors Detection. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:359-368 [Conf]
  51. Petr Fiser, Hana Kubatova
    Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:369-376 [Conf]
  52. Anna Bernasconi, Valentina Ciriani
    DRedSOP: Synthesis of a New Class of Regular Functions. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:377-384 [Conf]
  53. Lech Józwiak, Aleksander Slusarczyk, Dominik Gawlowski
    Multi-objective Optimal FSM State Assignment. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:385-396 [Conf]
  54. Lech Józwiak, Sien-An Ong
    Quality-Driven Template-Based Architecture Synthesis for Real-time Embedded SoCs. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:397-406 [Conf]
  55. Javier D. Bruguera, Roberto R. Osorio
    A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:407-414 [Conf]
  56. Michael Cowell, Adam Postula
    Rachael SPARC: An Open Source 32-bit Microprocessor Core for SoCs. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:415-422 [Conf]
  57. José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López
    Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:423-432 [Conf]
  58. Christian Galke, U. Gätzschmann, Heinrich Theodor Vierhaus
    Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:433-438 [Conf]
  59. Jacques J. A. Fournier, Simon W. Moore
    Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:439-446 [Conf]
  60. Arjan C. Dam, Michel G. J. Lammertink, Kenneth C. Rovers, Johan Slagman, Arno M. Wellink
    Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:447-455 [Conf]
  61. Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar
    A Power-Aware Technique for Functional Units in High-Performance Processors. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:456-459 [Conf]
  62. Vít Fábera, Vlastimil Jánes, Mária Jánesová
    Automata Construct with Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:460-463 [Conf]
  63. Tero Vallius, Juha Röning
    ATOMI II - Framework for Easy Building of Object-oriented Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:464-474 [Conf]
  64. Mark G. Arnold
    A RISC Processor with Redundant LNS Instructions. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:475-482 [Conf]
  65. Markus Damm
    State Assignment for Detecting Erroneous Transitions in Finite State Machines. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:483-490 [Conf]
  66. Qing K. Zhu
    Memory Generation and Power Distribution In SOC. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:491-495 [Conf]
  67. Jelena Trajkovic, Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski
    A Graph Based Algorithm for Data Path Optimization in Custom Processors. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:496-503 [Conf]
  68. Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina
    Testability Estimation Based on Controllability and Observability Parameters. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:504-514 [Conf]
  69. Ali R. Iranpour, Krzysztof Kuchcinski
    Performance Improvement for H.264 Video Encoding using ILP Embedded Processor. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:515-521 [Conf]
  70. Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
    Function Call Optimization in Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:522-529 [Conf]
  71. José M. Quintana, Maria J. Avedillo, Juan Núñez
    Design Guides for a Correct DC Operation in RTD-based Threshold Gates. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:530-536 [Conf]
  72. Massimo Rovini, Francesco Rossi, Pasquale Ciao, Nicola L'Insalat, Luca Fanucci
    Layered Decoding of Non-Layered LDPC Codes. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:537-544 [Conf]
  73. Francesco Rossi, Massimo Rovini, Luca Fanucci
    Design and Validation of Digital Channels for a Galileo Receiver Prototype. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:545-549 [Conf]
  74. Martin Novotný, Jan Schmidt
    Two Architectures of a General Digit-Serial Normal Basis Multiplier. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:550-553 [Conf]
  75. E. Pastor, J. Lopez, P. Royo
    An Embedded Architecture for Mission Control of Unmanned Aerial Vehicles. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:554-560 [Conf]
  76. Andrea Ricci, Matteo Grisanti, Ilaria De Munari, Paolo Ciampolini
    Design of a Low-Power Digital Core for Passive UHF RFID Transponder. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:561-568 [Conf]
  77. G. M. Bertolotti, A. Cristiani, R. Gandolfi, R. Lombardi
    A Portable System for Measuring Human Body Movement. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:569-576 [Conf]
  78. Panu Hämäläinen, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen
    Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:577-583 [Conf]
  79. Yan Zhang, Jussi Roivainen, Aarne Mämmelä
    Clock-Gating in FPGAs: A Novel and Comparative Evaluation. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:584-590 [Conf]
  80. Juan A. Sánchez, Pedro M. Ruiz
    Improving Delivery Ratio and Power Efficiency in Unicast Geographic Routing with a Realistic Physical Layer for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:591-597 [Conf]
  81. Jaroslaw Domaszewicz, Michal Rój, A. Pruszkowski
    Opportunistic Pervasive Computing with Domain-Oriented Virtual Machines. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:598-605 [Conf]
  82. Falko Dressler, Isabel Dietrich
    Lifetime Analysis in Heterogeneous Sensor Networks. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:606-616 [Conf]
  83. Matthew D'Souza, Montserrat Ros, Adam Postula
    Wireless Medical Information System Network for Patient ECG Monitoring. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:617-624 [Conf]
  84. R. Morales-Ramos, Juan A. Montiel-Nelson, R. Berenguer, A. Garcia-Alonso
    Voltage Sensors for Supply Capacitor in Passive UHF RFID Transponders. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:625-629 [Conf]
  85. Frank Reichenbach, Jan Blumenthal, Dirk Timmermann
    Improved Precision of Coarse Grained Localization in Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:630-640 [Conf]
  86. Mikkel Bystrup Stensgaard, Tobias Bjerregaard, Jens Sparsø, Johnny Halkjær Pedersen
    A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:641-648 [Conf]
  87. Guang Liang, Axel Jantsch
    Adaptive Power Management for the On-Chip Communication Network. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:649-656 [Conf]
  88. Tobias Bjerregaard, Jens Sparsø
    Packetizing OCP Transactions in the MANGO Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:657-664 [Conf]
  89. Christian Neeb, Norbert Wehn
    Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:665-672 [Conf]
  90. Sandro Penolazzi, Axel Jantsch
    A High Level Power Model for the Nostrum NoC. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:673-676 [Conf]
  91. Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng
    Off-Line Testing of Delay Faults in NoC Interconnects. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:677-680 [Conf]
  92. Rikard Thid, Ingo Sander, Axel Jantsch
    Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:681-688 [Conf]
  93. Partha Pratim Pande, Haibo Zhu, Amlan Ganguly, Cristian Grecu
    Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:689-695 [Conf]
  94. Rickard Holsmark, Maurizio Palesi, Shashi Kumar
    Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:696-703 [Conf]
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