Conferences in DBLP
Marc Duranton The Challenges for High Performance Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Roman Staszewski Digital RF. [Citation Graph (0, 0)][DBLP ] Conf ] Tohru Furuyama Deep Sub-100 nm Design Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Risto Suoranta New Directions in Mobile Device Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Waldschmidt Robustness in SOC Design. [Citation Graph (0, 0)][DBLP ] Conf ] Zhonghai Lu , Ingo Sander , Axel Jantsch Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Sander Stuijk , Twan Basten , Marc Geilen , Amir Hossein Ghamarian , Bart D. Theelen Resource-Efficient Routing and Scheduling of Time-Constrained Network-on-Chip Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Frédéric Pétrot , Alain Greiner , Pascal Gomez On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Sara Román , Hortensia Mecha , Daniel Mozos , Julio Septién Partition Based Dynamic 2D HW Multitasking Management. [Citation Graph (0, 0)][DBLP ] Conf ] Akash Kumar , Bart Mesman , Henk Corporaal , Jef L. van Meerbergen , Yajun Ha Global Analysis of Resource Arbitration for MPSoC. [Citation Graph (0, 0)][DBLP ] Conf ] Alokika Dash , Peter Petrov Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering. [Citation Graph (0, 0)][DBLP ] Conf ] Ari Kulmala , Timo D. Hämäläinen , Marko Hännikäinen Comparison of GALS and Synchronous Architectures with MPEG-4 Video Encoder on Multiprocessor System-on-Chip FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Hanene Ben Fradj , Cécile Belleudy , Michel Auguin Multi-Bank Main Memory Architecture with Dynamic Voltage Frequency Scaling for System Energy Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Calin Ciordas , Andreas Hansson , Kees Goossens , Twan Basten A Monitoring-Aware Network-on-Chip Design Flow. [Citation Graph (0, 0)][DBLP ] Conf ] Reid B. Porter , Jan R. Frigo , Maya Gokhale , Christophe Wolinski , François Charot , Charles Wagner A Run-Time Re-configurable Parametric Architecture for Local Neighborhood Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Freeman , Thimal Jayasooriya A Hardware IP-Core for Information Retrieval. [Citation Graph (0, 0)][DBLP ] Conf ] Kyriakos Stavrou , Pedro Trancoso Thermal-Aware Scheduling: A Solution for Future Chip Multiprocessors Thermal Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Freeman Evaluating Dataflow and Pipelined Vector Processing Architectures for FPGA Co-processors. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Delvai , Andreas Steininger Solving the Fundamental Problem of Digital Design - A Systematic Review of Design Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Pavel Kubalík , Radek Dobias , Hana Kubatova Dependable Design for FPGA Based on Duplex System and Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] Lucia Bissi , Pisana Placidi , Giuseppe Baruffa , Andrea Scorzoni A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Ramachandruni Venkata Kamala , M. Sudhakar , M. B. Srinivas An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n). [Citation Graph (0, 0)][DBLP ] Conf ] S. Momcilovic , Tiago Dias , Nuno Roma , Leonel Sousa Application Specific Instruction Set Processor for Adaptive Video Motion Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Haridimos T. Vergos , Costas Efstathiou Novel Modulo 2n + 1 Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Eryk Laskowski , Marek Tudruj Embedded Parallel Systems Based on Dynamic Look-Ahead Reconfiguration in Redundant Communication Resources. [Citation Graph (0, 0)][DBLP ] Conf ] George Kornaros BCB: A Buffered CrossBar Switch Fabric Utilizing Shared Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Fritz Mayer-Lindenberg Design and Application of a Scalable Embedded Systems' Architecture with an FPGA Based Operating Infrastucture. [Citation Graph (0, 0)][DBLP ] Conf ] Sylvain Collange , Jérémie Detrey , Florent de Dinechin Floating Point or LNS: Choosing the Right Arithmetic on an Aapplication Basis. [Citation Graph (0, 0)][DBLP ] Conf ] Jamel Tayeb , Smaïl Niar Adapting EPIC Architecture's Register Stack for Virtual Stack Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmet Akkas Dual-Mode Quadruple Precision Floating-Point Adder. [Citation Graph (0, 0)][DBLP ] Conf ] Pedro Trancoso Adaptive High-End Microprocessor for Power-Performance Efficiency. [Citation Graph (0, 0)][DBLP ] Conf ] Filipa Duarte , Stephan Wong Profiling Bluetooth and Linux on the Xilinx Virtex II Pro. [Citation Graph (0, 0)][DBLP ] Conf ] Viay Holimath , Javier D. Bruguera A Linear Convergent Functional Iterative DivisionWithout a Look-Up Table. [Citation Graph (0, 0)][DBLP ] Conf ] Sylvain Huet , Emmanuel Casseau , Olivier Pasquier A Computation Core for Communication Refinement of Digital Signal Processing Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Stáva , Ondrej Novák Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW. [Citation Graph (0, 0)][DBLP ] Conf ] Petros Oikonomakos , Simon W. Moore An Asynchronous PLA with Improved Security Characteristics. [Citation Graph (0, 0)][DBLP ] Conf ] Giovanni Busonera , Salvatore Carta , Andrea Marongiu , Luigi Raffo Automatic Application Partitioning on FPGA/CPU Systems Based on Detailed Low-Level Information. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto R. Osorio , Javier D. Bruguera A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Silvio Misera , Heinrich Theodor Vierhaus , Lars Breitenfeld , André Sieber A Mixed Language Fault Simulation of VHDL and SystemC. [Citation Graph (0, 0)][DBLP ] Conf ] Sébastien Le Beux , Philippe Marquet , Ouassila Labbani , Jean-Luc Dekeyser FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar. [Citation Graph (0, 0)][DBLP ] Conf ] Ines Viskic , Rainer Dömer A Flexible, Syntax Independent Representation (SIR) for System Level Design Models. [Citation Graph (0, 0)][DBLP ] Conf ] Adam Smyk , Marek Tudruj Prototyping Parallel FDTD Programs by Macro Data Flow Graph Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Armando Sánchez-Peña , Pedro P. Carballo , Luz García , Antonio Núñez VIPACES, Verification Interface Primitives for the Development of AXI Compliant Elements and Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Viacheslav Izosimov , Paul Pop , Petru Eles , Zebo Peng Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems*. [Citation Graph (0, 0)][DBLP ] Conf ] Eduardas Bareisa , Vacius Jusas , Kestutis Motiejunas , Rimantas Seinauskas Transition Fault Test Reuse. [Citation Graph (0, 0)][DBLP ] Conf ] Muhammad Waseem , Ludovic Apvrille , Rabea Ameur-Boulifa , Sophie Coudert , Renaud Pacalet Abstract Application Modeling for System Design Space Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Gianluca Casarosa , Michele Apuzzo , Luca Fanucci , Bruno Sarti Characterization of the EMC Performances of the CAN Bus in a Typical System Bus Architecture for Small Satellites. [Citation Graph (0, 0)][DBLP ] Conf ] Liam Noonan , Colin Flanagan Utilising Evolutionary Approaches and Object Oriented Techniques for Design Space Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Jaan Raik , Raimund Ubar , Taavi Viilukas High-Level Decision Diagram based Fault Models for Targeting FSMs. [Citation Graph (0, 0)][DBLP ] Conf ] Ilya Levin , Vladimir Ostrovsky , Osnat Keren , Vladimir Sinelnikov Cascade Scheme for Concurrent Errors Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Petr Fiser , Hana Kubatova Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Anna Bernasconi , Valentina Ciriani DRedSOP: Synthesis of a New Class of Regular Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Lech Józwiak , Aleksander Slusarczyk , Dominik Gawlowski Multi-objective Optimal FSM State Assignment. [Citation Graph (0, 0)][DBLP ] Conf ] Lech Józwiak , Sien-An Ong Quality-Driven Template-Based Architecture Synthesis for Real-time Embedded SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Javier D. Bruguera , Roberto R. Osorio A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Cowell , Adam Postula Rachael SPARC: An Open Source 32-bit Microprocessor Core for SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] José Manuel Colmenar , Oscar Garnica , Juan Lanchares , José Ignacio Hidalgo , Guadalupe Miñana , Sonia López Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Galke , U. Gätzschmann , Heinrich Theodor Vierhaus Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Jacques J. A. Fournier , Simon W. Moore Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography. [Citation Graph (0, 0)][DBLP ] Conf ] Arjan C. Dam , Michel G. J. Lammertink , Kenneth C. Rovers , Johan Slagman , Arno M. Wellink Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard. [Citation Graph (0, 0)][DBLP ] Conf ] Guadalupe Miñana , Oscar Garnica , José Ignacio Hidalgo , Juan Lanchares , José Manuel Colmenar A Power-Aware Technique for Functional Units in High-Performance Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Vít Fábera , Vlastimil Jánes , Mária Jánesová Automata Construct with Genetic Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Tero Vallius , Juha Röning ATOMI II - Framework for Easy Building of Object-oriented Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Mark G. Arnold A RISC Processor with Redundant LNS Instructions. [Citation Graph (0, 0)][DBLP ] Conf ] Markus Damm State Assignment for Detecting Erroneous Transitions in Finite State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Qing K. Zhu Memory Generation and Power Distribution In SOC. [Citation Graph (0, 0)][DBLP ] Conf ] Jelena Trajkovic , Mehrdad Reshadi , Bita Gorjiara , Daniel Gajski A Graph Based Algorithm for Data Path Optimization in Custom Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Tomas Pecenka , Josef Strnadel , Zdenek Kotásek , Lukás Sekanina Testability Estimation Based on Controllability and Observability Parameters. [Citation Graph (0, 0)][DBLP ] Conf ] Ali R. Iranpour , Krzysztof Kuchcinski Performance Improvement for H.264 Video Encoding using ILP Embedded Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Yuko Hara , Hiroyuki Tomiyama , Shinya Honda , Hiroaki Takada Function Call Optimization in Behavioral Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] José M. Quintana , Maria J. Avedillo , Juan Núñez Design Guides for a Correct DC Operation in RTD-based Threshold Gates. [Citation Graph (0, 0)][DBLP ] Conf ] Massimo Rovini , Francesco Rossi , Pasquale Ciao , Nicola L'Insalat , Luca Fanucci Layered Decoding of Non-Layered LDPC Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Francesco Rossi , Massimo Rovini , Luca Fanucci Design and Validation of Digital Channels for a Galileo Receiver Prototype. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Novotný , Jan Schmidt Two Architectures of a General Digit-Serial Normal Basis Multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] E. Pastor , J. Lopez , P. Royo An Embedded Architecture for Mission Control of Unmanned Aerial Vehicles. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Ricci , Matteo Grisanti , Ilaria De Munari , Paolo Ciampolini Design of a Low-Power Digital Core for Passive UHF RFID Transponder. [Citation Graph (0, 0)][DBLP ] Conf ] G. M. Bertolotti , A. Cristiani , R. Gandolfi , R. Lombardi A Portable System for Measuring Human Body Movement. [Citation Graph (0, 0)][DBLP ] Conf ] Panu Hämäläinen , Timo Alho , Marko Hännikäinen , Timo D. Hämäläinen Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core. [Citation Graph (0, 0)][DBLP ] Conf ] Yan Zhang , Jussi Roivainen , Aarne Mämmelä Clock-Gating in FPGAs: A Novel and Comparative Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Juan A. Sánchez , Pedro M. Ruiz Improving Delivery Ratio and Power Efficiency in Unicast Geographic Routing with a Realistic Physical Layer for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jaroslaw Domaszewicz , Michal Rój , A. Pruszkowski Opportunistic Pervasive Computing with Domain-Oriented Virtual Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Falko Dressler , Isabel Dietrich Lifetime Analysis in Heterogeneous Sensor Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew D'Souza , Montserrat Ros , Adam Postula Wireless Medical Information System Network for Patient ECG Monitoring. [Citation Graph (0, 0)][DBLP ] Conf ] R. Morales-Ramos , Juan A. Montiel-Nelson , R. Berenguer , A. Garcia-Alonso Voltage Sensors for Supply Capacitor in Passive UHF RFID Transponders. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Reichenbach , Jan Blumenthal , Dirk Timmermann Improved Precision of Coarse Grained Localization in Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Mikkel Bystrup Stensgaard , Tobias Bjerregaard , Jens Sparsø , Johnny Halkjær Pedersen A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Guang Liang , Axel Jantsch Adaptive Power Management for the On-Chip Communication Network. [Citation Graph (0, 0)][DBLP ] Conf ] Tobias Bjerregaard , Jens Sparsø Packetizing OCP Transactions in the MANGO Network-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Neeb , Norbert Wehn Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Sandro Penolazzi , Axel Jantsch A High Level Power Model for the Nostrum NoC. [Citation Graph (0, 0)][DBLP ] Conf ] Tomas Bengtsson , Artur Jutman , Shashi Kumar , Raimund Ubar , Zebo Peng Off-Line Testing of Delay Faults in NoC Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Rikard Thid , Ingo Sander , Axel Jantsch Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads. [Citation Graph (0, 0)][DBLP ] Conf ] Partha Pratim Pande , Haibo Zhu , Amlan Ganguly , Cristian Grecu Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm. [Citation Graph (0, 0)][DBLP ] Conf ] Rickard Holsmark , Maurizio Palesi , Shashi Kumar Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions. [Citation Graph (0, 0)][DBLP ] Conf ] 