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Conferences in DBLP

European Dependable Computing Conference (EDCC) (edcc)
1994 (conf/edcc/1994)

  1. Matti A. Hiltunen, Richard D. Schlichting
    A Model for Adaptive Fault-Tolerant Systems. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:3-20 [Conf]
  2. Jean-Charles Fabre, Yves Deswarte, Brian Randell
    Designing Secure and Reliable Applications using Fragmentation-Redundancy-Scattering: An Object-Oriented Approach. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:21-38 [Conf]
  3. João Gabriel Silva, Luís Moura Silva, Henrique Madeira, Jorge Bernardino
    A Fault-Tolerant Mechanism for Simple Controllers. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:39-55 [Conf]
  4. Carsta Petersohn, Willem P. de Roever, Cornelis Huizing, Jan Peleska
    Formal Semantics for Ward & Mellor's Transformation Schemas and the Specification of Faul Tolerant Systems. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:59-76 [Conf]
  5. Cinzia Bernardeschi, Alessandro Fantechi, Luca Simoncini
    Formal Reasoning on Fault Coverage of Fault Tolerant Techniques: A Case Study. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:77-94 [Conf]
  6. Silvano Chiaradonna, Andrea Bondavalli, Lorenzo Strigini
    On Performability Modeling and Evaluation of Software Fault Tolerant Structures. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:97-114 [Conf]
  7. Cesare Antonelli, Vincenzo Grassi
    Optimal Design of Fault-Tolerant Soft-Real-Time Systems with Imprecise Computations. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:115-130 [Conf]
  8. Andrea Bobbio, Miklós Telek
    Computational Restrictions for SPN with Generally Distributed Transition Times. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:131-148 [Conf]
  9. Raimund Ubar
    Test Generation for Digital Systems Based on Alternative Graphs. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:151-164 [Conf]
  10. Michel Renovell, P. Huc, Yves Bertrand
    The Configuration Ratio: A Model for Simulating CMOS Intra-Gate Bridge with Variable Logic Thresholds. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:165-177 [Conf]
  11. Andrzej Krasniewski, Leszek B. Wronski
    Coverage of Delay Faults: When 13% and 99% Mean the Same. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:178-195 [Conf]
  12. Henrique Madeira, Mário Zenha Rela, Francisco Moreira, João Gabriel Silva
    RIFLE: A General Purpose Pin-level Fault Injector. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:199-216 [Conf]
  13. Rolf Johansson
    On Single Event Upset Error Manifestation. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:217-231 [Conf]
  14. Hong Zhu, Patrick A. V. Hall, John H. R. May, T. Cockram
    Injecting Faults into Environment Simulators for Testing Safety Critical Software. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:235-249 [Conf]
  15. Pascale Thévenod-Fosse, Christine Mazuet, Yves Crouzet
    On Statistical Structural Testing of Synchronous Data Flow Programs. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:250-267 [Conf]
  16. G. Masseboeuf, J. Pulou, J. L. Rainard
    Hierarchical Test Analysis of VLSI Circuits for Random BIST. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:271-288 [Conf]
  17. Peter Böhlau
    Zero Aliasing Compression Based on Groups of Weakly Independent Outputs in Circuits with High Complexity for Two Fault Models. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:289-306 [Conf]
  18. Tomislav Lovric
    Systematic and Design Diversity - Software Techniques for Hardware Fault Detection. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:309-326 [Conf]
  19. Stefan Gerber, Michael Gössel
    Detection of Permanent Hardware Faults of a Floating Point Adder by Pseudoduplication. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:327-335 [Conf]
  20. Aki Watanabe, Ken Sakamura
    MLDD (Multi Layered Design Diversity) Architecture for Achieving High Design Fault Tolerance Capabilities. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:336-349 [Conf]
  21. Bernd Bieker, Erik Maehle, Geert Deconinck, Johan Vounckx
    Reconfiguration and Checkpointing in Massively Parallel Systems. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:353-370 [Conf]
  22. Jörn Altmann, Frank Balbach, Axel Hein
    An Approach for Hierarchical System Level Diagnosis of Massively Parallel Computers Combined with a Simulation-Based Method for Dependability Analysis. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:371-385 [Conf]
  23. István Majzik, András Pataricza, Mario Dal Cin, Wolfgang Hohl, J. Hönig, Volkmar Sieh
    Hierarchical Checking of Multiprocessors Using Watchdog Processors. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:386-403 [Conf]
  24. Jean-Claude Laprie
    Dependability: The Challenge for the Future of Computing and Communication Technologies. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:407-408 [Conf]
  25. Algirdas Avizienis
    Position Paper. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:409-410 [Conf]
  26. Jan Hlavicka
    Position Paper. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:411- [Conf]
  27. Michele Morganti
    Position Paper. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:412-413 [Conf]
  28. Brian Randell
    Some Lessons from the SW2000 Workshop. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:414-416 [Conf]
  29. Ernst Schmitter
    Dependable Computing and its Industrial Use. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:417-418 [Conf]
  30. Yung-Yuan Chen, Ching-Hwa Cheng, Yung-Ci Chou
    An Effective Reconfiguration Process for Fault-Tolerant VLSI/WSI Array Processors. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:421-438 [Conf]
  31. Jamel M. Tahir, Satnam Singh Dlay, Raouf N. Gorgui-Naguib, Oliver R. Hinton
    Concurrent Error Detection in Fast FNT Networks. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:439-452 [Conf]
  32. Laurence E. LaForge
    Feasible Regions Quantify the Configuration Power of Arrays with Multiple Fault Types. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:453-469 [Conf]
  33. Mohamed Kaâniche, Karama Kanoun, Michel Cukier, Marta Rettelbusch de Bastos Martini
    Software Reliability Analysis of Three Successive Generations of a Switching System. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:473-490 [Conf]
  34. Gilles Muller, Mireille Hue, Nadine Peyrouze
    Performance of Consistent Checkpointing in a Modular Operating System: Results of the FTM Experiment. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:491-508 [Conf]
  35. Jae-Hyun Park, Heung-Kyu Lee, Ju-Hyun Cho
    Ring-Banyan Network: A Faul Tolerant Multistage Interconnection Network and its Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:511-528 [Conf]
  36. Dimiter R. Avresky, Khalid M. Al-Tawil
    Reconfiguration of Faulty Hypercubes. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:529-545 [Conf]
  37. Chu-Sing Yang, Shun-Yue Wu
    Fault-Tolerance on Boolean n-Cube Architectures. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:546-559 [Conf]
  38. Martin Leu
    Relative Signatures for Fault Tolerance and their Implementation. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:563-580 [Conf]
  39. Bertil Folliot, Pierre Sens
    GATOSTAR: A Fault Tolerant Load Sharing Facility for Parallel Applications. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:581-598 [Conf]
  40. P. D. V. van der Stok, M. M. M. P. J. Claessen, D. Alstein
    A Hierarchical Membership Protocol for Synchronous Distributed Systems. [Citation Graph (0, 0)][DBLP]
    EDCC, 1994, pp:599-616 [Conf]
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