|
Conferences in DBLP
- Michael J. Flynn, Patrick Hung
Computer Architecture and Technology: Some Thoughts on the Road Ahead. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:3-16 [Conf]
- Walid A. Najjar
From Here to Main-stream: The Present and Future of Reconfigurable Computing. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:17- [Conf]
- Tim Todman, José Gabriel F. Coutinho, Wayne Luk
Customisable Hardware Compilation. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:18-28 [Conf]
- Seth Copen Goldstein
Computing Without Processors. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:29-32 [Conf]
- Jawad Khan, Balasubramanian Sethuraman, Ranga Vemuri
A Power-Performance Trade-off Methodology for Portable Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:33-37 [Conf]
- Paul M. Heysters, Gerard J. M. Smit, Egbert Molenkamp
Energy-Efficiency of the MONTIUM Reconfigurable Tile Processor. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:38-44 [Conf]
- Gerard J. M. Smit, Michèl A. J. Rosien, Yuanqing Guo, Paul M. Heysters
Overview of the Tool-flow for the Montium Processor Tile. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:45-51 [Conf]
- Stephan Gatzka, Christian Hochberger
Distinguished Paper: A New General Model for Adaptive Processors. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:52-62 [Conf]
- Christian Plessl, Marco Platzner
Virtualization of Hardware - Introduction and Survey. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:63-69 [Conf]
- Heiko Kalte, Markus Koester, Boris Kettelhoit, Mario Porrmann, Ulrich Rückert
A Comparative Study on System Approaches for Partially Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:70-76 [Conf]
- Manish Handa, Ranga Vemuri
Area Fragmentation in Reconfigurable Operating Systems. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:77-83 [Conf]
- Nam Pham Ngoc, Gauthier Lafruit, Jean-Yves Mignolet, Geert Deconinck, Rudy Lauwereins
QOS Aware HW/SW Partitioning on Run-time Reconfigurable Multimedia Platforms. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:84-92 [Conf]
- T. Bretschneider, B. Ramesh, V. Gupta, I. McLoughlin
Low-Cost Space-Borne Processing on a Reconfigurable Parallel Architecture. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:93-99 [Conf]
- Duncan A. Buell, James P. Davis, Gang Quan, Sreesa Akella, Siddhaveerasharan Devarkal, P. Kancharla, Allen Michalski, Heather A. Wake
Experiences with a Reconfigurable Computer. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:100-108 [Conf]
- Fred Ma, John P. Knight, Calvin Plett
Physical Resource Binding for a Coarse Grain Reconfigurable Array. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:109-115 [Conf]
- Razali Jidin, David L. Andrews, Douglas Niehaus
Implementing Multi Threaded System Support for Hybrid FPGA/CPU Computational Components. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:116-122 [Conf]
- Madhura Purnaprajna, Marek Reformat, Witold Pedrycz
Genetic Algorithms in Hardware-Software Partitioning. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:123-129 [Conf]
- Spencer Isaacson, Doran Wilde
The Task-Resource Matrix: Control for a Distributed Reconfigurable Multi-Processor Hardware RTOS. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:130-136 [Conf]
- Per Andersson, Krzysztof Kuchcinski
Distinguished Paper: Automatic Local Memory Architecture Generation for Data Reuse in Custom Data Paths. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:137-144 [Conf]
- Laurie A. Smith King, Miriam Leeser, Heather Quinn
Dynamo: A Runtime Partitioning System. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:145-154 [Conf]
- Sacki Agelis, Magnus Jonsson
System-Level Runtime Reconfigurablity - Optical Interconnection Networks for Switching Applications. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:155-162 [Conf]
- John W. Williams, Neil Bergmann
Embedded Linux as a Platform for Dynamically Self-Reconfiguring Systems-on-Chip. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:163-169 [Conf]
- Mitchell J. Myjak, Fredrick L. Anderson, José G. Delgado-Frias
H-Tree Interconnection Structure for Reconfigurable DSP Hardware. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:170-176 [Conf]
- Dennis Johnsson, Jerker Bengtsson, Bertil Svensson
Two-level Reconfigurable Architecture for High-Performance Signal Processing. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:177-183 [Conf]
- Tero Rissa, Wayne Luk, Peter Y. K. Cheung
Distinguished Paper: Automated Combination of Simulation and Hardware Prototyping. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:184-193 [Conf]
- Zoran A. Salcic, Partha S. Roop
Customizing Processor Cores to Support Reactivity. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:194-202 [Conf]
- X. Zhang, Gabriel Dragffy, Anthony G. Pipe, Quan M. Zhu
Partial-DNA Supported Artificial-Life in an Embryonic Array. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:203-208 [Conf]
- Xin-Ming Huang, Jing Ma
An FPGA-Based Accelerator for Multiphysics Modeling. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:209-212 [Conf]
- Jawad Khan, Jayanthi Rajagopalan, Renqiu Huang, Ranga Vemuri
A Portable Face Recognition System Using Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:213-217 [Conf]
- Wenrui Gong, Gang Wang, Ryan Kastner
A High Performance Application Representation for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:218-224 [Conf]
- Arvind Sudarsanam, Aravind Dasu, Sethuraman Panchanathan
Task Scheduling of Control-Data Flow Graphs for Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:225-231 [Conf]
- Zafer Gürdal, Tom Hartka, Mark Jones, Sun Wook Kim
A Reconfigurable Approach to Structural Engineering Design Computations. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:232-239 [Conf]
- Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
Incremental Timing Budget Management in Programmable Systems. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:240-246 [Conf]
- Peter Bellows
Distinguished Paper: High-Visibility Debug-by-Design for FPGA Platforms. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:247-258 [Conf]
- Chris Dick, Fred Harris
On the Use of FPGAs for OFDM Signal Processing. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:259-263 [Conf]
- Viktor K. Prasanna
Invited Paper: Energy-Efficient Computations on FPGAs. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:264-275 [Conf]
- Gokul Govindu, Viktor K. Prasanna, Vikash Daga, Sridhar Gangadharpalli, V. Sridhar
Efficient Floating-point Based Block LU Decomposition on FPGAs. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:276-279 [Conf]
- Jingzhao Ou, Viktor K. Prasanna
A Methodology for Energy Efficient Application Synthesis Using Platform FPGAs. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:280-283 [Conf]
- Ronald Scrofano, Viktor K. Prasanna
Computing Lennard-Jones Potentials and Forces with Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:284-292 [Conf]
- J. Yardley, K. Gilson
A Reconfigurable Computing Model for Biological Research. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:293-295 [Conf]
- Ali Akoglu, Aravind Dasu, Sethuraman Panchanathan
Cluster Extraction for Hybrid FPGA Architecture in Computation Intensive Applications. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:296- [Conf]
- Jesse Hunter, Peter Athanas, Cameron Patterson
VTSim: A Virtex-II Device Simulator. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:297-298 [Conf]
- Minoru Watanabe, Fuminori Kobayashi
Testing Method for Optical Connections Using Gate Array Structure in ORGAs. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:299-302 [Conf]
- Otsebele E. Nare, Lisa P. Mickens, Charles T. Johnson-Bey
A Multi-Objective System Level Synthesis Approach to Reconfigurable Analog Technology. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:303-304 [Conf]
- Xinzhong Guo, Jack S. N. Jean
Design Enumeration of Mapping 2D FFT onto FPGA Based Reconfigurable Computers. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:305-306 [Conf]
- Herbert Walder, Samuel Nobs, Marco Platzner
XF-Board: A Prototyping Platform for Reconfigurable Hardware Operating Systems. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:306- [Conf]
- Aju M. Jacob, Ian A. Troxel, Alan D. George
Distributed Configuration Management for Reconfigurable Cluster Computing. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:307- [Conf]
- Vasanth Asokan, S. Mohan, Raj K. Nagarajan
Hardware Software Codesign of the Xilinx Microkernel. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:308- [Conf]
- Shinichi Koyama, Tomonori Izumi, Yukihiro Nakamura
An Adaptive Load Distribution Model and Design on Self-Reconfigurable Logic Device. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:309- [Conf]
- Pius Ng, David Zhao
FFT Mapping on MathStar's FPOATM FilterBuilderTM Platform. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:310- [Conf]
- Minoru Watanabe, Fuminori Kobayashi
Timing Analysis of an Optically Differential Reconfigurable Gate Array for Dynamically Reconfigurable Processors. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:311- [Conf]
- Austin Hung, William D. Bishop, Andrew A. Kennings
Enabling Cache Coherency for N-Way SMP Systems on Programmable Chips. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:312- [Conf]
- Lodewijk T. Smit, Gerard J. M. Smit, Johann Hurink
Run-Time Adaptation of a Reconfigurable Mobile UMTS Receiver. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:313- [Conf]
- David Grant, William D. Bishop, Wayne M. Loucks
A Flexible Processor for Research Prototyping. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:314- [Conf]
- Mayur Srinivasan, Sethuraman Panchanathan
Target Arhcitecture Automation for Reconfigurable Logic Blocks. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:315- [Conf]
- Ling Zhuo, Viktor K. Prasanna
Energy Performance of Floating-Point Matrix Multiplication on FPGAs. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:316- [Conf]
- M. David Yeager, Wei Wang
HARC: A Homogeneous Architecture reconfigurable Computer. [Citation Graph (0, 0)][DBLP] ERSA, 2004, pp:317- [Conf]
|