Conferences in DBLP
Nick Tredennick , Brion Shimamoto The Rise of Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:3-12 [Conf ] Soheil Ghiasi , Hyun J. Moon , Majid Sarrafzadeh Collaborative and Reconfigurable Object Tracking. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:13-20 [Conf ] Jürgen Becker , Martin Vorbach PACT XPP Architecture in Adaptive System-on-Chip Integration. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:21-30 [Conf ] Cameron Patterson A Dynamic Module Server for Embedded Platform FPGAs. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:31-40 [Conf ] Razak Mohammedali Altera FPGA Technology Provides Innovative Solutions for Evolving Market Needs. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:41-47 [Conf ] Steve Guccione Latest Developments at Quicksilver Tech. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:48-50 [Conf ] Jack S. N. Jean , Xinzhong Guo , Fei Wang , Lei Song , Ying Zhang A Study of Mapping Generalized Sliding Window Operations on Reconfigurable Computers. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:51-57 [Conf ] Kendra Cooper , Jia Zhou , Hui Ma , I-Ling Yen , Farokh B. Bastani Code Parameterization for Satisfaction of QoS Requirements in Embedded Software. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:58-64 [Conf ] Lilian Bossuet , Guy Gogniat , Jean Luc Philippe Fast Design Space Exploration Method for Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:65-71 [Conf ] Jacir Luiz Bordim , Yasuaki Ito , Koji Nakano Instance-Specific Solutions to Accelerate the CKY Parsing. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:72-80 [Conf ] Vincent Nollet , Jean-Yves Mignolet , Andrei Bartic , Diederik Verkest , Serge Vernalde , Rudy Lauwereins Hierarchical Run-Time Reconfiguration Managed by an Operating System for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:81-87 [Conf ] Nico Kasprzyk , Andreas Koch , Ulrich Golze , Michael Rock An Improved Intermediate Representation for Datapath Generation. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:88-94 [Conf ] Pramote Kuacharoen , Mohamed Shalan , Vincent John Mooney A Configurable Hardware Scheduler for Real-Time Systems. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:95-101 [Conf ] Stephen Charlwood , Steven F. Quigley The Impact of Routing Architecture on Reconfiguration Overheads. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:102-110 [Conf ] A. P. Shanthi , Balaji Vijayan , Manivel Rajendran , Senthilkumar Veluswami , Ranjani Parthasarathi JBits Based Fault Tolerant Framework for Evolvable Hardware. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:111-117 [Conf ] Jing Ma , Peter Athanas A JBits-Based Incremental Design Environment with Non-Preemptive Refinement for Multi-Million Gate FPGAs. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:118-126 [Conf ] Valery Sklyarov , Iouliia Skliarova Architecture of a Reconfigurable Processor for Implementing Search Algorithm over Discrete Matrices. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:127-133 [Conf ] X. Zhang , Gabriel Dragffy , Anthony G. Pipe , Nigel Gunton , Quan M. Zhu A Reconfigurable Self-Healing Embryonic Cell Architecture. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:134-140 [Conf ] Timothy F. Oliver , Douglas L. Maskell Towards Run-Time Re-Configurable Techniques for Real-Time Embedded Applications. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:141-146 [Conf ] Klaus Danne , Christophe Bobda , Heiko Kalte Increasing Efficiency by Partial Hardware Reconfiguration: Case Study of a Multi-Controller System. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:147-153 [Conf ] Dominique Lavenier , Stéphane Guyetant , Steven Derrien , Stéphane Rubini A Reconfigurable Parallel Disk System for Filtering Genomic Banks. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:154-166 [Conf ] Tien-Lung Lee , Neil W. Bergmann An Interface Methodology for Retargettable FPGA Peripherals. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:167-173 [Conf ] Rolf Enzler , Christian Plessl , Marco Platzner Co-Simulation of a Hybrid Multi-Context Architecture. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:174-180 [Conf ] Jong-Ru Guo , Chao You , Michael Chu , Kuan Zhou , Young Uk Yim , Robert W. Heikaus , Russell P. Kraft , John F. McDonald A Novel Multi-Speed, Power Saving Architecture for SiGe HBT FPGA. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:181-187 [Conf ] Linda Kaouane , Mohamed Akil , Thierry Grandpierre , Yves Sorel A Methodology to Implement Real-Time Applications on Reconfigurable Circuits. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:188-200 [Conf ] Oswaldo Cadenas , Graham M. Megson , Toomas P. Plaks FPGA Circuits for a Monte-Carlo Based Matrix Inversion Architecture. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:201-207 [Conf ] Zhihong Zhao , Miriam Lesser Precision Modeling of Floating-Point Applications for Variable Bitwidth Computing. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:208-214 [Conf ] Ronald Scrofano , Ju-wook Jang , Viktor K. Prasanna Energy-Efficient Discrete Cosine Transform on FPGAs. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:215-221 [Conf ] William D. Smith , Austars R. Schnore Towards an RCC-Based Accelerator for Computational Fluid Dynamics Applications. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:222-234 [Conf ] Paul M. Heysters , Gerard J. M. Smit , Egbert Molenkamp Montium - Balancing between Energy-Efficiency, Flexibility and Performance. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:235-241 [Conf ] Gerard K. Rauwerda , Gerard J. M. Smit , L. F. W. van Hoesel , Paul M. Heysters Mapping Wireless Communication Algorithms to a Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:242-251 [Conf ] Chris Dick FPGAs: Re-Inventing the Signal Processor. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:252-258 [Conf ] S. Murat Bicer , Frank Pilhofer , Graham Bardouleau , Jeffrey Smith Next Generation Architecture for Heterogeneous Embedded Systems. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:259-268 [Conf ] John P. Morrison , Padraig J. O'Dowd , Philip D. Healy Searching RC5 Keyspaces with Distributed Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:269-272 [Conf ] Darrin M. Hanna , Richard E. Haskell Using Flowpaths for the High-Level Synthesis of Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:273-279 [Conf ] Nikolaos G. Bartzoudis , Alexandros G. Fragkiadakis , David J. Parish , Jose Luis Nunez , Mark Sandford Reconfigurable Computing and Active Networks. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:280-283 [Conf ] Herbert Walder , Marco Platzner Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:284-287 [Conf ] Per Haglund , Oskar Mencer , Wayne Luk , Benjamin Tai PyHDL: Hardware Scripting with Python. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:288-291 [Conf ] Aravind Dasu , Ali Akoglu , Sethuraman Panchanathan An Analysis Tool Set for Reconfigurable Media Processing. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:292-295 [Conf ] Janusz A. Starzyk , Yongtao Guo Dynamically Self-Reconfigurable Machine Learning Structure for FPGA Implementation. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:296-299 [Conf ] Neil W. Bergmann , John A. Williams , Peter Waldeck Egret: A Flexible Platform for Real-Time Reconfigurable Systems on Chip. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:300-303 [Conf ] Christophe Wolinski , Frans Trouw , Maya Gokhale A Preliminary Study of Molecular Dynamics on Reconfigurable Computers. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:304-307 [Conf ] James M. McCollum , Joseph M. Lancaster , Gregory D. Peterson Using Reconfigurable Computing to Accelerate Simulation Applications. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:308-311 [Conf ] Maryam S. Mirian , Majid Nili Ahmadabadi , Babak Nadjar Araabi A Fault Tolerant Multi-Agent System with Non-Deterministic Decision-Making for Task Allocation. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:312-315 [Conf ] Jonathan M. Gentle , Iyad A. Ajwa Draak: A Mulitlanguage Macro Compiler. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:316-320 [Conf ] Seong Yong Ohm , Ki-Yeol Ryu , Kang Yi Lower Bound Estimation on the Numbers of LUT Blocks and Micro-Registers for Time-Mulitplexed FPGA Synthesis. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:321-324 [Conf ] Seong-Yong Ahn , Yo-Seop Hwang , Jae-Hong Shim , Jeong-A. Lee Producer and Consumer: Roles of a Microprocessor and a Configurable Logic in a Configurable SoC. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:325-0 [Conf ]