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Conferences in DBLP
- Robert P. Colwell
Where Intel's Microprocessor Architecture is Going. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:3-6 [Conf]
- Donald W. Bouldin
Enabling Killer Applications of Reconfigurable Systems: ERSA Keynote and Introduction. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:7-16 [Conf]
- Gerard J. M. Smit, Gerard K. Rauwerda
Reconfigurable Architectures for Adaptable Mobile Systems. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:17-25 [Conf]
- Steven A. Guccione
Microprocessors: The New LUT. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:26-25 [Conf]
- Charlé R. Rupp
Reconfigurable Instruction Set Computing for Embedded Processing. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:36- [Conf]
- Dror E. Maydan
Configurable Processors and the Evolution of System-on-Chip Design. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:37- [Conf]
- Chris Sullivan
What's the Future of C-Based Programmable SoC design? [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:38-40 [Conf]
- Jing Ma, Xin-Ming Huang
A SoPC Architecture of MIMO Sphere Decoder for Mobile Communications. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:41-47 [Conf]
- Kimmo U. Järvinen, Matti Tommiska, Jorma Skyttä
A Compact MD5 and SHA-1 Co-Implementation Utilizing Algorithm Similarities. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:48-54 [Conf]
- Jingzhao Ou, Viktor K. Prasanna
Rapid Arithmetic Level Simulation Based Energy Estimation for Hardware/Software Co-Design Using FPGAs. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:55-61 [Conf]
- Gerard K. Rauwerda, Gerard J. M. Smit, Werner Brugger
Implementing an Adaptive Viterbi Algorithm in Coarse-Grained Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:62-70 [Conf]
- Fei Wang, Jack S. N. Jean, Shuxia Sun
Aspect Ratio Effects on Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:71-77 [Conf]
- Frank Hannig, Jürgen Teich
Output Serialization for FPGA-based and Coarse-grained Processor Arrays. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:78-84 [Conf]
- Stefan Ihmor, Florian Dittmann
Optimizing Interface Implementation Costs Using Runtime Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:85-91 [Conf]
- Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich
Defragmenting the Module Layout of a Partially Reconfigurable Device. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:92-104 [Conf]
- Brandon Thurmon, James M. McCollum, Gregory D. Peterson, Chris D. Cox, Nagiza F. Samatova, Gary Sayler, Michael L. Simpson
Accelerating Exact Stochastic Simulation Using Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:105-111 [Conf]
- Sanjay V. Rajopadhye, Kolin Paul
A 1.5-D Architecture for Back-Propagation Training. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:112-118 [Conf]
- Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna
Area-Efficient Evaluation of a Class of Arithmetic Expressions Using Deeply Pipelined Floating-Point Cores. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:119-128 [Conf]
- Chen Chang, John Wawrzynek, Pierre-Yves Droz, Robert W. Brodersen
The Design And Application Of A High-End Reconfigurable Computing System. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:129-136 [Conf]
- Ronald Scrofano, Gokul Govindu, Viktor Pasanna
A Library of Parameterizable Floating-Point Cores for FPGAs and Their Application to Scientific Computing. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:137-148 [Conf]
- Wayne Luk, Sherif Yusuf, Morris Sloman, Geoffrey Brown, Emil C. Lupu, Naranker Dulay
A Combined Hardware-Software Architecture for Network Flow. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:149-155 [Conf]
- Xuejun Liang, Jeffrey S. Vetter, Melissa C. Smith, Arthur S. Bland
Balancing FPGA Resource Utilities. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:156-162 [Conf]
- Sungjoon Jung, Tag Gon Kim
An Operation and Interconnection Sharing Algorithm for Partially Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:163-174 [Conf]
- Ryan A. DeVille, Ian A. Troxel, Alan D. George
Performance Monitoring for Run-time Management of Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:175-181 [Conf]
- Zexin Pan, Juanjo Noguera, B. Earl Wells
Improved Microarchitecture Support for Dynamic Task Scheduling on Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:182-188 [Conf]
- Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo
Flexible Core Reallocation for Virtex II Structures. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:189-195 [Conf]
- Abdel Ejnioui, Ronald F. DeMara
Area Reclamation Strategies and Metrics for SRAM-Based Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:196-202 [Conf]
- Shaoyu Liu, Gregory D. Peterson, Seong Kong
A Hardware Implementation of a Dynamically Adjustable Block-based Neural Network. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:203-210 [Conf]
- Antonio Gentile, Salvatore Segreto, Filippo Sorbello, Giorgio Vassallo, Salvatore Vitabile, Vincenzo Vullo
CliffoSor, an Innovative FPGA-based Architecture for Geometric Algebra. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:211-217 [Conf]
- Wim J. C. Melis, Kieron Turkington, Alexander Whitton, Wayne Luk, Peter Y. K. Cheung, Paul Metzgen
Cell Based Motion Estimators for Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:218-224 [Conf]
- Nobuo Nakai, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe
Reconfigurable 1-Bit Processor Array with Reduced Wirng Area. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:225-234 [Conf]
- Otsebele E. Nare, Charles T. Johnson-Bey
A Reconfigurable Antialiasing Filter Design Using Multi-Abstraction Design Exploration Approach. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:235-238 [Conf]
- Wenrui Gong, Yan Meng, Gang Wang, Ryan Kastner, Timothy Sherwood
Data Partitioning and Optimizations for Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:239-242 [Conf]
- Kenneth B. Kent, Zhao Yong, Jacqueline E. Rice, Troy Ronda
Instance-Specific Versus Parameter-Specific Circuit Generation. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:243-246 [Conf]
- Ali Akoglu, Sethuraman Panchanathan
Application Specific Reconfigurable Architecture Design. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:247-250 [Conf]
- Heng Tan, Ronald F. DeMara
A Device-Controlled Dynamic Configuration Framework Supporting Heterogeneous Resource Management. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:251-254 [Conf]
- Janak Porwal, Sachin Patkar
Algorithms For Scheduling Of Data Transfer Across FPGAs In A Grid. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:255-260 [Conf]
- Youngsoo Kim, Dongsoo Kim, Daesun Park, Sungjo Kim
A Non-LIinear Function Generator Using BRM. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:261-262 [Conf]
- Caaliph Andriamisaina, Catherine Dezan, Christophe Jégo, Bernard Pottier
Abstract Synthesis of Turbo Decoder Elements onto Reconfigurable Circuit. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:263-266 [Conf]
- Chuan He, Wei Zhao, Mi Lu
FPGA-Based High-Order Finite Difference Algorithm for 2D Acoustic Wave Propagation Problems. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:267-273 [Conf]
- Zain-ul-Abdin, Bertil Svensson
Compiling Stream-Language Applications to a Reconfigurable Array Processor. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:274-275 [Conf]
- Yuanqing Guo, Cornelis Hoede, Gerard J. M. Smit
A Multi-Pattern Scheduling Algorithm. [Citation Graph (0, 0)][DBLP]
ERSA, 2005, pp:276-0 [Conf]
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