The SCEAS System
Navigation Menu

Conferences in DBLP

European Design and Test Conference (EDAC) (eurodac)
1994 (conf/eurodac/1994)

  1. Fast OFDD based minimization of fixed polarity Reed-Muller expressions. [Citation Graph (, )][DBLP]

  2. Free Kronecker decision diagrams and their application to Atmel 6000 series FPGA mapping. [Citation Graph (, )][DBLP]

  3. Multilevel logic optimization of very high complexity circuits. [Citation Graph (, )][DBLP]

  4. Symbolic exploration of large circuits with enhanced forward/backward traversals. [Citation Graph (, )][DBLP]

  5. Extended timing diagrams as a specification language. [Citation Graph (, )][DBLP]

  6. Efficient algorithms for interface timing verification. [Citation Graph (, )][DBLP]

  7. A unified discrete gate sizing/cell library optimization method for design and analysis of delay minimized CMOS and BiCMOS circuits. [Citation Graph (, )][DBLP]

  8. Layout optimization of planar CMOS cells regarding width-to-height trade-off. [Citation Graph (, )][DBLP]

  9. Automatic layout generation for CMOS analog transistors. [Citation Graph (, )][DBLP]

  10. A prototyping environment for control-oriented HW/SW systems using state-charts, activity-charts and FPGA's. [Citation Graph (, )][DBLP]

  11. A performance evaluator for parameterized ASIC architectures. [Citation Graph (, )][DBLP]

  12. Hardware-software-codesign of application specific microcontrollers with the ASM environment. [Citation Graph (, )][DBLP]

  13. A hardware environment for prototyping and partitioning based on multiple FPGAs. [Citation Graph (, )][DBLP]

  14. GSA: scheduling and allocation using genetic algorithm. [Citation Graph (, )][DBLP]

  15. OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming. [Citation Graph (, )][DBLP]

  16. Parallel controller synthesis from a Petri net specification. [Citation Graph (, )][DBLP]

  17. Parallel algorithms for the simulation of lossy transmission lines. [Citation Graph (, )][DBLP]

  18. Mixed electrical-thermal and electrical-mechanical simulation of electromechatronic systems using PSpice. [Citation Graph (, )][DBLP]

  19. TRICAP—a three dimensional capacitance solver for arbitrarily shaped conductors on printed circuit boards and VLSI interconnections. [Citation Graph (, )][DBLP]

  20. Advanced simulation and modeling techniques for hardware quality verification of digital systems. [Citation Graph (, )][DBLP]

  21. OPERAS in a DSP CAD environment. [Citation Graph (, )][DBLP]

  22. Logic synthesis for reliability—an early start to controlling electromigration and hot carrier effects. [Citation Graph (, )][DBLP]

  23. 100-hour design cycle: a test case. [Citation Graph (, )][DBLP]

  24. A tool for processor instruction set design. [Citation Graph (, )][DBLP]

  25. Instruction set extraction from programmable structures. [Citation Graph (, )][DBLP]

  26. Optimal equivalent circuits for interconnect delay calculations using moments. [Citation Graph (, )][DBLP]

  27. Efficient linear circuit analysis by Pade´ approximation via the Lanczos process. [Citation Graph (, )][DBLP]

  28. Multilevel generalization of relaxation algorithms for circuit simulation. [Citation Graph (, )][DBLP]

  29. MOS VLSI circuit simulation by hardware accelerator using semi-natural models. [Citation Graph (, )][DBLP]

  30. A flexible access control mechanism for CAD frameworks. [Citation Graph (, )][DBLP]

  31. A tightly coupled approach to design and data management. [Citation Graph (, )][DBLP]

  32. Integrating CAD tools into a framework environment using a flexible and adaptable procedural interface. [Citation Graph (, )][DBLP]

  33. Design tool encapsulation—all problems solved? [Citation Graph (, )][DBLP]

  34. A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning. [Citation Graph (, )][DBLP]

  35. A method for partitioning UNITY language in hardware and software. [Citation Graph (, )][DBLP]

  36. Hardware/software partitioning and minimizing memory interface traffic. [Citation Graph (, )][DBLP]

  37. Reliability study of combinatorial circuits. [Citation Graph (, )][DBLP]

  38. Test pattern generation hardware motivated by pseudo-exhaustive test techniques. [Citation Graph (, )][DBLP]

  39. An experimental analysis of the effectiveness of the circular self-test path technique. [Citation Graph (, )][DBLP]

  40. Design automation of self checking circuits. [Citation Graph (, )][DBLP]

  41. An architecture-independent approach to FPGA routing based on multi-weighted graphs. [Citation Graph (, )][DBLP]

  42. Algorithms for a switch module routing problem. [Citation Graph (, )][DBLP]

  43. A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions. [Citation Graph (, )][DBLP]

  44. A delay driven FPGA placement algorithm. [Citation Graph (, )][DBLP]

  45. Formal verification of pipeline conflicts in RISC processors. [Citation Graph (, )][DBLP]

  46. An automatically verified generalized multifunction arithmetic pipeline. [Citation Graph (, )][DBLP]

  47. Formal specification and simulation of instruction-level parallelism. [Citation Graph (, )][DBLP]

  48. An efficient verification algorithm for parallel controllers. [Citation Graph (, )][DBLP]

  49. Tests for path delay faults vs. tests for gate delay faults: how different they are. [Citation Graph (, )][DBLP]

  50. RESIST: a recursive test pattern generation algorithm for path delay faults. [Citation Graph (, )][DBLP]

  51. BiTeS: a BDD based test pattern generator for strong robust path delay faults. [Citation Graph (, )][DBLP]

  52. Testing redundant asynchronous circuits by variable phase splitting. [Citation Graph (, )][DBLP]

  53. Re-engineering hardware specifications by exploiting design semantics. [Citation Graph (, )][DBLP]

  54. The use of semantic information for control of a complex routing tool. [Citation Graph (, )][DBLP]

  55. A new knowledge-based design manager assistant for CAD frameworks. [Citation Graph (, )][DBLP]

  56. The use of single and multiple seed architectures with a natural based micro-architecture exploration algorithm. [Citation Graph (, )][DBLP]

  57. Compiled-code-based simulation with timing verification. [Citation Graph (, )][DBLP]

  58. A portable and extendible testbed for distributed logic simulation. [Citation Graph (, )][DBLP]

  59. Gate-level timing verification using waveform narrowing. [Citation Graph (, )][DBLP]

  60. Exact path sensitization in timing analysis. [Citation Graph (, )][DBLP]

  61. A new power estimation technique with application to decomposition of Boolean functions for low power. [Citation Graph (, )][DBLP]

  62. A new technique for exploiting regularity in data path synthesis. [Citation Graph (, )][DBLP]

  63. A component selection algorithm for high-performance pipelines. [Citation Graph (, )][DBLP]

  64. Fast simulation method for the detection of reflection—and crosstalk effects during the design of complex printed circuit boards. [Citation Graph (, )][DBLP]

  65. Design support of printed circuit boards concerning radiation and irradiation effects (EMI): using an extended EMC-Workbench. [Citation Graph (, )][DBLP]

  66. Overall thermal simulation of electronic equipment. [Citation Graph (, )][DBLP]

  67. A macro-cell global router based on two genetic algorithms. [Citation Graph (, )][DBLP]

  68. An appreciation of simulated annealing to maze routing. [Citation Graph (, )][DBLP]

  69. Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay. [Citation Graph (, )][DBLP]

  70. A general state graph transformation framework for asynchronous synthesis. [Citation Graph (, )][DBLP]

  71. Evaluation of function blocks for asynchronous design. [Citation Graph (, )][DBLP]

  72. Application-independent hierarchical synthesis methodology for analogue circuits. [Citation Graph (, )][DBLP]

  73. Generating VHDL models from natural language descriptions. [Citation Graph (, )][DBLP]

  74. Non-reversible VHDL source-source encryption. [Citation Graph (, )][DBLP]

  75. Modeling shared variables in VHDL. [Citation Graph (, )][DBLP]

  76. A VHDL-based bus model for multi-PCB system design. [Citation Graph (, )][DBLP]

  77. The semantics of behavioral VHDL '93 descriptions. [Citation Graph (, )][DBLP]

  78. A process algebra interpretation of a verification oriented overlanguage of VHDL. [Citation Graph (, )][DBLP]

  79. Proof theory and a validation condition generator for VHDL. [Citation Graph (, )][DBLP]

  80. Implementation of a SDH STM-N IC for B-ISDN using VHDL based synthesis tools. [Citation Graph (, )][DBLP]

  81. VHDL and cyclic corrector codes. [Citation Graph (, )][DBLP]

  82. Generating compilers for generated datapaths. [Citation Graph (, )][DBLP]

  83. Synthesis of VHDL concurrent processes. [Citation Graph (, )][DBLP]

  84. Scheduling of behavioral VHDL by retiming techniques. [Citation Graph (, )][DBLP]

  85. A transformation for integrating VHDL behavioral specification with synthesis and software generation. [Citation Graph (, )][DBLP]

  86. Formal verification of behavioral VHDL specifications: a case study. [Citation Graph (, )][DBLP]

  87. (V)HDL-based verification of heterogeneous synchronous/asynchronous systems. [Citation Graph (, )][DBLP]

  88. Petri nets as intermediate representation between VHDL and symbolic transition systems. [Citation Graph (, )][DBLP]

  89. Computing binary decision diagrams for VHDL data types. [Citation Graph (, )][DBLP]

  90. Static analysis for VHDL model evaluation. [Citation Graph (, )][DBLP]

  91. Automotive databus simulation using VHDL. [Citation Graph (, )][DBLP]

  92. Distributed simulation for structural VHDL netlists. [Citation Graph (, )][DBLP]

  93. A new flexible VHDL simulator. [Citation Graph (, )][DBLP]

  94. The role of VHDL within the TOSCA hardware/software codesign framework. [Citation Graph (, )][DBLP]

  95. Timing preserving interface transformations for the synthesis of behavioral VHDL. [Citation Graph (, )][DBLP]

  96. Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations. [Citation Graph (, )][DBLP]

  97. Speeding up test pattern generation from behavioral VHDL descriptions containing several processes. [Citation Graph (, )][DBLP]

  98. Algorithms for behavioral test pattern generation from VHDL circuit descriptions containing loop language constructs. [Citation Graph (, )][DBLP]

  99. Testability analysis and improvement from VHDL behavioral specifications. [Citation Graph (, )][DBLP]

  100. VHDL switch level fault simulation. [Citation Graph (, )][DBLP]

  101. ASIC synthesis of a flexible 80 Mbit/s Reed-Solomon Codec. [Citation Graph (, )][DBLP]

  102. A VHDL-based design methodology: the design experience of a high performance ASIC chip. [Citation Graph (, )][DBLP]

  103. SYNOPA: an automated synthesizer for CMOS operational amplifiers. [Citation Graph (, )][DBLP]

  104. Using C to write portable CMOS VLSI module generators. [Citation Graph (, )][DBLP]

  105. Rapid prototyping for DSP circuits using high level design tools. [Citation Graph (, )][DBLP]

  106. CAD education and science in Ukraine after Perestroika. [Citation Graph (, )][DBLP]

System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002