Fast OFDD based minimization of fixed polarity Reed-Muller expressions. [Citation Graph (, )][DBLP]

Free Kronecker decision diagrams and their application to Atmel 6000 series FPGA mapping. [Citation Graph (, )][DBLP]

Multilevel logic optimization of very high complexity circuits. [Citation Graph (, )][DBLP]

Symbolic exploration of large circuits with enhanced forward/backward traversals. [Citation Graph (, )][DBLP]

Extended timing diagrams as a specification language. [Citation Graph (, )][DBLP]

Efficient algorithms for interface timing verification. [Citation Graph (, )][DBLP]

A unified discrete gate sizing/cell library optimization method for design and analysis of delay minimized CMOS and BiCMOS circuits. [Citation Graph (, )][DBLP]

Automatic layout generation for CMOS analog transistors. [Citation Graph (, )][DBLP]

A prototyping environment for control-oriented HW/SW systems using state-charts, activity-charts and FPGA's. [Citation Graph (, )][DBLP]

A performance evaluator for parameterized ASIC architectures. [Citation Graph (, )][DBLP]

Hardware-software-codesign of application specific microcontrollers with the ASM environment. [Citation Graph (, )][DBLP]

A hardware environment for prototyping and partitioning based on multiple FPGAs. [Citation Graph (, )][DBLP]

GSA: scheduling and allocation using genetic algorithm. [Citation Graph (, )][DBLP]

OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming. [Citation Graph (, )][DBLP]

Parallel controller synthesis from a Petri net specification. [Citation Graph (, )][DBLP]

Parallel algorithms for the simulation of lossy transmission lines. [Citation Graph (, )][DBLP]

Mixed electrical-thermal and electrical-mechanical simulation of electromechatronic systems using PSpice. [Citation Graph (, )][DBLP]

TRICAP—a three dimensional capacitance solver for arbitrarily shaped conductors on printed circuit boards and VLSI interconnections. [Citation Graph (, )][DBLP]

Advanced simulation and modeling techniques for hardware quality verification of digital systems. [Citation Graph (, )][DBLP]

Reliability study of combinatorial circuits. [Citation Graph (, )][DBLP]

Test pattern generation hardware motivated by pseudo-exhaustive test techniques. [Citation Graph (, )][DBLP]

An experimental analysis of the effectiveness of the circular self-test path technique. [Citation Graph (, )][DBLP]

Design automation of self checking circuits. [Citation Graph (, )][DBLP]

An architecture-independent approach to FPGA routing based on multi-weighted graphs. [Citation Graph (, )][DBLP]

Algorithms for a switch module routing problem. [Citation Graph (, )][DBLP]

A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions. [Citation Graph (, )][DBLP]

The use of semantic information for control of a complex routing tool. [Citation Graph (, )][DBLP]

A new knowledge-based design manager assistant for CAD frameworks. [Citation Graph (, )][DBLP]

The use of single and multiple seed architectures with a natural based micro-architecture exploration algorithm. [Citation Graph (, )][DBLP]

Compiled-code-based simulation with timing verification. [Citation Graph (, )][DBLP]

A portable and extendible testbed for distributed logic simulation. [Citation Graph (, )][DBLP]

Gate-level timing verification using waveform narrowing. [Citation Graph (, )][DBLP]

Exact path sensitization in timing analysis. [Citation Graph (, )][DBLP]

A new power estimation technique with application to decomposition of Boolean functions for low power. [Citation Graph (, )][DBLP]

A new technique for exploiting regularity in data path synthesis. [Citation Graph (, )][DBLP]

A component selection algorithm for high-performance pipelines. [Citation Graph (, )][DBLP]

Fast simulation method for the detection of reflection—and crosstalk effects during the design of complex printed circuit boards. [Citation Graph (, )][DBLP]

Design support of printed circuit boards concerning radiation and irradiation effects (EMI): using an extended EMC-Workbench. [Citation Graph (, )][DBLP]

Overall thermal simulation of electronic equipment. [Citation Graph (, )][DBLP]

A macro-cell global router based on two genetic algorithms. [Citation Graph (, )][DBLP]

An appreciation of simulated annealing to maze routing. [Citation Graph (, )][DBLP]