Conferences in DBLP
Lech Józwiak , Sien-An Ong Quality-Driven Decision Making Methodology for System-Level Design. [Citation Graph (0, 0)][DBLP ] Conf ] Jeroen Voeten , P. H. A. van der Putten , M. P. J. Stevens Behaviour-Preserving Transformations in SHE: A Formal Approach to Architecture Design. [Citation Graph (0, 0)][DBLP ] Conf ] Ghassan Al Hayek , Yves Le Traon , Chantal Robach Considering Test Economics in the Process of Hardware/Software Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] A. M. del Corral , José M. Llabería Increasing the Effective Memory Bandwidth in Multivector Processors. [Citation Graph (0, 0)][DBLP ] Conf ] István Vassányi , István Erényi Implementation of Processor Cells for Array Algorithms on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Aziz Can Yuceturk , Bernd Klauer , Stefan Zickenheiner , Ronald Moore , Klaus Waldschmidt Mapping of Neural Networks onto Data Flow Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto García-Martínez , Jesús Fernández-Conde , Ángel Viña A Comprehensive Approach in Performance Evaluation for Modern Real-Time Operating Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Joshua Etkin , José Fridman An Algorithm for Scheduling Prioritized Tasks in a Hard Real-Time Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Steven Bradley , William Henderson , David Kendall , Adrian Robson , Stephen Hawkes A Formal Design and Implementation Method for Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Reinhard Rauscher A Design Assistant for Scheduling of Design Decisions. [Citation Graph (0, 0)][DBLP ] Conf ] João M. S. Alcântara , C. E. T. Oliveira , Manuel L. Anido A Novel Circuit Extraction Tool Based on X-Spans and Y-Spans. [Citation Graph (0, 0)][DBLP ] Conf ] Karlheinz Agsteiner , Dieter Monjau , Sören Schulze Automating System-Level Design: From Specification to Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Dominique De Vito , Olivier Michel Effective SIMD Code Generation for the High-Level Declarative Data-Parallel Language 8 1/2. [Citation Graph (0, 0)][DBLP ] Conf ] Genésio Gomes da Cruz Neto , Ricardo Massa Ferreira Lima , Rafael Dueire Lins , André L. M. Santos Optimising Pseudoknotin FCMC. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander S. Antonov , Vladimir V. Voevodin Application of the V-Ray Technology for Optimization of the TRFD and FL052 Perfect Club Benchmarks to CRAY Y-MP and CRAY T3D Supercomputers. [Citation Graph (0, 0)][DBLP ] Conf ] Eero Lassila A Macro Expansion Approach to Embedded Processor Code Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Hlavicka , Stanislav Racek , Pavel Smrha Functional Validation of Fault-Tolerant Asynchronous Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Miroslav Svéda A Prototyping Technique with an Asychronous Specification Language. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver Hammerschmidt , Thomas Doersam Software Engineering in Control Using Objects and Services. [Citation Graph (0, 0)][DBLP ] Conf ] Sheetanshu L. Pandey , Kothanda R. Subramanian , Philip A. Wilsey A Semantic Model of VHDL for Validating Rewriting Algebras. [Citation Graph (0, 0)][DBLP ] Conf ] Corrie Huijs A Graph Rewriting Approach for Transformational Design of Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Grün , Petru Eles , Krzysztof Kuchcinski , Zebo Peng Automatic Parallelization of a Petri Net-Based Design Representation for High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] B. Antal , György Csertán , István Majzik , Andrea Bondavalli , Luca Simoncini Reachability and Timing Analysis in Data Flow Networks: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Siegelin , Ciaran O'Donnell , Ulrich Finger Efficient Simulation of Multiprocessors through Finite State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto Giorgi , Cosimo Antonio Prete , Luigi M. Ricciardi , Gianpaolo Prina A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] José M. García , A. Flores A Novel Approach to Improve the Performance of Interconnection Networks with Hot - Spots. [Citation Graph (0, 0)][DBLP ] Conf ] Leszek Borzemski , Arkadiusz Kieda A Load Balancing System for Windows NT Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Vanthienen , Stephan Poelmans A General Framework for Positioning, Evaluating and Selecting the New Generation of Development Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Cecilia Inés Sosa Arias , Beatriz Mascia Daltrini A Multi-Agent Environment for User Interface Design. [Citation Graph (0, 0)][DBLP ] Conf ] Nomusa Dlodlo , Carl Bamford Separating Application Functionality from the User Interface in a Distributed Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Reinhard Rauscher , Dieter Klawan , Hans-Jürgen Bandelt Results Given by a New Evaluation System for Placement and Routing Heuristics. [Citation Graph (0, 0)][DBLP ] Conf ] Reinhard Rauscher , Andreas Krause A System for Heuristic Modifications on PLA - Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Hans-Georg Martin Retiming for Circuits with Enable Registers. [Citation Graph (0, 0)][DBLP ] Conf ] Charles Changli Chin , Shang-Rong Tsai Transparency in a Replicated Network File System. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew M. Tyrrell Recovery Blocks and Algorithm-Based Fault Tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Yong Sun , Hongji Yang Communication Mechanism Independent Protocol Specification Based on CSP: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] István Majzik Software Monitoring and Debugging Using Compressed Signature Sequences. [Citation Graph (0, 0)][DBLP ] Conf ] Souâd Taouil-Traverson , Sylvie Vignes Preliminary Analysis Cycle for B-Method Software Development. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Sosnowski , A. Kusmierczyk Pseudorandom versus Deterministic Testing of Intel 80x86 Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Ghassan Al Hayek , Chantal Robach On the Adequacy of Deriving Hardware Test Data from the Behavioral Specification. [Citation Graph (0, 0)][DBLP ] Conf ] João Carlos Cunha , João Gabriel Silva DELFIM: Error Detection by Thin Memory Protection. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto Bevacqua , Luca Guerrazzi , Franco Fummi SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Katerina Goseva-Popstojanova , Aksenti Grnarov N-Version Programming: A Unified Modeling Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Oum-El-Kheir Benkahla , F. Chevassu , B. Remy , Chantal Robach Performance Evaluation of Testing Strategies in Parallel Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Tamás Bartha Effective Approximate Fault Diagnosis of Systems with Inhomogeneous Test Invalidation. [Citation Graph (0, 0)][DBLP ] Conf ] Aristotel Tentov , Aksenti L. Grnarov Performance Analysis of Packet Switching Interconnection Networks with Finite Buffers. [Citation Graph (0, 0)][DBLP ] Conf ] Hoyoung Hwang , Hyoungjun Kim , Yanghee Choi , Chongsang Kim Multicast Routing Algorithms for Manhattan Street Network. [Citation Graph (0, 0)][DBLP ] Conf ] Pertti Raatikainen , Teleste Oy , Juha Zidbeck Performance Comparison of Experimented Switching Architectures for ATM. [Citation Graph (0, 0)][DBLP ] Conf ] Minho Song , Yanghee Choi , Chongsang Kim Connection Rerouting Method for General Application to Connection-Oriented Mobile Communication Net works. [Citation Graph (0, 0)][DBLP ] Conf ] Morten Kjelsø , Mark Gooch , Simon Jones Design and Performance of a Main Memory Hardware Data Compressor. [Citation Graph (0, 0)][DBLP ] Conf ] Pablo Ibáñez , Víctor Viñals Performance Assessment of Contents Management in Multilevel On-Chip Caches. [Citation Graph (0, 0)][DBLP ] Conf ] Kanad Ghose , Kiran Raghavendra Desai , Peter M. Kogge Using Method Lookup Caches and Register Windowing to Speed Up Dynamically-Bound Object-Oriented Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Elena Pagani , Gian Paolo Rossi Comparing Performances and Quality of Service of Group Communication Protocols. [Citation Graph (0, 0)][DBLP ] Conf ] Giacomo Cabri , Antonio Corradi , Franco Zambonelli Experience of Adaptive Replication in Distributed File Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Han-Suk Choi , Jae Soo Yoo , Ok-Bae Chang A New Control Service Model Based on CORBA for Distributed Multimedia Objects. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Fischer , Jacek Wytrebowicz , Stanislaw Budkowski Hardware/Software Co-Design of Communication Protocols. [Citation Graph (0, 0)][DBLP ] Conf ] Chie Dou Formal Specification of Communication Protocols Based on a Timed-SDL: Validation and Performance Prospects. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed Bettaz , Mourad Maouche , Kamel Barkaoui Formal Specification of Communication Protocols with Object-Based ECATNets. [Citation Graph (0, 0)][DBLP ] Conf ] Adam Postula , David Abramson , Paul Logothetis The Design of a Specialised Processor for the Simulation of Sintering A. Postula. [Citation Graph (0, 0)][DBLP ] Conf ] Johan Stärner , Joakirn Adomat , John Furunäs , Lennart Lindh Real-Time Scheduling Co-Processor in Hardware for Single and Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandre R. S. Romariz , P. U. A. Ferreira , J. V. Campelo Jr. , M. L. Graciano Jr. , J. C. da Costa Design of a Hybrid Digital-Analog Neural Co-Processor for Signal Processing. [Citation Graph (0, 0)][DBLP ] Conf ] V. Tchoumatchenko , T. Vassileva , P. Gurov An FPGA-Based Square-Root Co-Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Petr Zemánek Parallel Set Operations with Visual Data. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Canham , Stephen L. Smith , Andrew M. Tyrrell Parallel Approaches to the Segmentation of Free-Hand Drawings. [Citation Graph (0, 0)][DBLP ] Conf ] John Yiannis Cotronis Efficient Program Composition on Parix by the Ensemble Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Casiano Rodríguez , José L. Roda , F. García , Francisco Almeida , Daniel González Paradigms for Parallel Dynamic Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Anastasio Molano , Alberto García-Martínez , Ángel Viña The Design and Implementation of a Multimedia Storage Server to Support Video-on-Demand Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Hess , Tino Hutschenreuther , Ralf Lehmann , Alexander Schill Architecture and Implementation for Scalable Transfer of Live Videos in Multimedia Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jocelyne Farhat-Gissler , Isabelle M. Demeure Automatic Scheduling of Applications with Temporal QoS Constraints: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Winfried Grünewald , Theo Ungerer Towards Extremely Fast Context Switching in a Block-Multithreaded Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Piguet , T. Schneider , Jean-Marc Masgonty , Claude Arm , Serge Durand , M. Stegers Low-Power Embedded Microprocessor Design. [Citation Graph (0, 0)][DBLP ] Conf ] Kanad Ghose , Pavel Vasek A Fast Capability Extension to a RISC Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto Baldoni , Michel Raynal , Ravi Prakash , Mukesh Singhal Broadcast with Time and Causality Constraints for Multimedia Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Tino Pyssysalo , Leo Ojala Causal Modeling of a Video-on-Demand System Using Predicate/Transition Net Formalism. [Citation Graph (0, 0)][DBLP ] Conf ] Ernst Biersack , Frédéric Thiesse Statistical Admission Control in Video Servers with Variable Bit-Rate Streams and Constant Time Length Retrieva. [Citation Graph (0, 0)][DBLP ] Conf ] Roger Collins , Gordon Steven Instruction Scheduling for a Superscalar Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Eliseu M. Chaves Filho , Edil S. Tavares Fernandes , Andrew Wolfe Load Balancing in Superscalar Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] 