Conferences in DBLP
Conference Organizers. [Citation Graph (0, 0)][DBLP ] Conf ] Zachary K. Baker , Viktor K. Prasanna Efficient Hardware Data Mining with the Apriori Algorithm on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Christos-Savvas Bouganis , George A. Constantinides , Peter Y. K. Cheung A Novel 2D Filter Design Methodology for Heterogeneous Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Radu Teodorescu , Josep Torrellas Prototyping Architectural Support for Program Rollback Using FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Zion Kwok , Steven J. E. Wilton Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Francesco Lertora , Michele Borgatti Handling Different Computational Granularity by a Reconfigurable IC Featuring Embedded FPGAs and a Network-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Roman L. Lysecky , Frank Vahid , Sheldon X.-D. Tan A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation. [Citation Graph (0, 0)][DBLP ] Conf ] Lesley Shannon , Paul Chow Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable Controller. [Citation Graph (0, 0)][DBLP ] Conf ] Pedro C. Diniz Evaluation of Code Generation Strategies for Scalar Replaced Codes in Fine-Grain Configurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] John Sachs Beeckler , Warren J. Gross FPGA Particle Graphics Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Baker , Tim Todman , Henry Styles , Wayne Luk Reconfigurable Designs for Radiosity. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Simka , Jan Pelzl , Thorsten Kleinjung , Jens Franke , Christine Priplata , Colin Stahlke , Milos Drutarovský , Viktor Fischer Hardware Factorization Based on Elliptic Curve Method. [Citation Graph (0, 0)][DBLP ] Conf ] Justin L. Tripp , Henning S. Mortveit , Anders A. Hansson , Maya Gokhale Metropolitan Road Traffic Simulation on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] He Chuan , Wei Zhao , Mi Lu Time Domain Numerical Simulation for Transient Waves on Reconfigurable Coprocessor Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Jingzhao Ou , Viktor K. Prasanna COMA: A COoperative MAnagement Scheme for Energy Efficient Implementation of Real-Time Operating Systems on FPGA Based Soft Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Wenyin Fu , Katherine Compton An Execution Environment for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Bryan C. Catanzaro , Brent E. Nelson Higher Radix Floating-Point Representations for FPGA-Based Arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] K. Scott Hemmert , Keith D. Underwood An Analysis of the Double-Precision Floating-Point FFT on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Haselman , Michael J. Beauchamp , Aaron Wood , Scott Hauck , Keith D. Underwood , K. Scott Hemmert A Comparison of Floating Point and Logarithmic Number Systems for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Heather Quinn , Paul Graham Terrestrial-Based Radiation Upsets: A Cautionary Tale. [Citation Graph (0, 0)][DBLP ] Conf ] Shawn Phillips , Scott Hauck Automating the Layout of Reconfigurable Subsystems Using Circuit Generators. [Citation Graph (0, 0)][DBLP ] Conf ] Young H. Cho , William H. Mangione-Smith Fast Reconfiguring Deep Packet Filter for 1+ Gigabit Network. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Attig , John W. Lockwood A Framework for Rule Processing in Reconfigurable Network Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Janardhan Singaraju , Long Bu , John A. Chandy A Signature Match Processor Architecture for Network Intrusion Detection. [Citation Graph (0, 0)][DBLP ] Conf ] José Gabriel F. Coutinho , Jun Jiang , Wayne Luk Interleaving Behavioral and Cycle-Accurate Descriptions for Reconfigurable Hardware Compilation. [Citation Graph (0, 0)][DBLP ] Conf ] Hristo Nikolov , Todor Stefanov , Ed F. Deprettere Modeling and FPGA Implementation of Applications Using Parameterized Process Networks with Non-Static Parameters. [Citation Graph (0, 0)][DBLP ] Conf ] M. Y. Niamat , Surya S. Hejeebu , M. Alam A BIST Approach for Testing FPGAs Using JBITS. [Citation Graph (0, 0)][DBLP ] Conf ] Yongfeng Gu , Tom Van Court , Douglas DiSabello , Martin C. Herbordt Preliminary Report: FPGA Acceleration of Molecular Dynamics Computations. [Citation Graph (0, 0)][DBLP ] Conf ] David Fang , John Teifel , Rajit Manohar A High-Performance Asynchronous FPGA: Test Results. [Citation Graph (0, 0)][DBLP ] Conf ] Sudarshan Banerjee , Elaheh Bozorgzadeh , Nikil D. Dutt Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Robert McIlhenny , Milos D. Ercegovac RAVIOLI - Reconfigurable Arithmetic Variable-Precision Implementations of On-Line Instructions. [Citation Graph (0, 0)][DBLP ] Conf ] John A. Williams , Neil W. Bergmann , X. Xie FIFO Communication Models in Operating Systems for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Naohito Nakasato , Tsuyoshi Hamada Astrophysical Hydrodynamics Simulations on a Reconfigurable System. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew French , Li Wang , Tyler Anderson , Michael J. Wirthlin Post Synthesis Level Power Modeling of FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Daewook Kim , Manho Kim , Gerald E. Sobelman FPGA-Based CDMA Switch for Networks-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Shakith Fernando , Ha Yajun Design of Networked Reconfigurable Encryption Engine. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Greskamp , Ron Sass A Virtual Machine for Merit-Based Runtime Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Holland , Scott Hauck Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC. [Citation Graph (0, 0)][DBLP ] Conf ] Xin Jia , Ranga Vemuri The GAPLA: A Globally Asynchronous Locally Synchronous FPGA Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Joshua M. Lucas , Raymond Hoare , Alex K. Jones Optimizing Technology Mapping for FPGAs Using CAMs. [Citation Graph (0, 0)][DBLP ] Conf ] H. Sofikitis , K. Roumpou , Apostolos Dollas , Nikolaos G. Bourbakis An Architecture for Video Compression Based on the SCAN Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Apostolos Dollas , Ioannis Ermis , Iosif Koidis , Ioannis Zisis , Christopher Kachris An Open TCP/IP Core for Reconfigurable Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Todd S. Sproull , Gordon J. Brebner , Christopher E. Neely Mutable Codesign for Embedded Protocol Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Michalis D. Galanis , Grigoris Dimitroulakos , Costas E. Goutis Accelerating Applications by Mapping Critical Kernels on Coarse-Grain Reconfigurable Hardware in Hybrid Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Lodi , Luca Ciccarelli , Claudio Mucci , Roberto Giansante , Andrea Cappelli , Mario Toma An Embedded Reconfigurable Datapath for SoC. [Citation Graph (0, 0)][DBLP ] Conf ] J. Greg Nash Systolic Architecture for Computing the Discrete Fourier Transform on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Mayumi Kato , Chia-Tien Dan Lo Hardware Solution to Java Compressed Heap. [Citation Graph (0, 0)][DBLP ] Conf ] Petersen F. Curt , James P. Durbano , Fernando E. Ortiz , John R. Humphrey , Dennis W. Prather A General Purpose, Highly Efficient Communication Controller Architecture for Hardware Acceleration Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Arash Hariri , Reza Rastegar , Morteza Saheb Zamani , Mohammad Reza Meybodi Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Hideharu Amano , Shohei Abe , Yohei Hasegawa , Katsuaki Deguchi , Masayasu Suzuki Performance and Cost Analysis of Time-Multiplexed Execution on the Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Jing Ma , Xin-Ming Huang A System-on-Programmable Chip Approach for MIMO Sphere Decoder. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Bobda , Mateusz Majer , Ali Ahmadinia , Thomas Haller , André Linarth , Jürgen Teich , Sándor P. Fekete , Jan van der Veen The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto Donato , Fabrizio Ferrandi , Massimo Redaelli , Marco D. Santambrogio , Donatella Sciuto Caronte: A Complete Methodology for the Implementation of Partially Dynamically Self-Reconfiguring Systems on FPGA Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Gerald R. Morris , Ling Zhuo , Viktor K. Prasanna High-Performance FPGA-Based General Reduction Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Jasmine Lam , John McAllister , Jennifer Dudley Core-Based Methodology: An Automated Approach for Implementing a Complete System from Algorithms to a Heterogeneous Network including FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Luis E. Cordova , Duncan A. Buell , Sreesa Akella The DARPA Dynamic Programming Benchmark on a Reconfigurable Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Tsuyoshi Hamada , Naohito Nakasato Massively Parallel Processors Generator for Reconfigurable System. [Citation Graph (0, 0)][DBLP ] Conf ] Muhammad Z. Hasan , Sotirios G. Ziavras FPGA-Based Vector Processing for Solving Sparse Sets of Equations. [Citation Graph (0, 0)][DBLP ] Conf ] Joseph Zambreno , Dan Honbo , Alok N. Choudhary Exploiting Multi-Grained Parallelism in Reconfigurable SBC Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Apostolos Dollas , Dionissios Efstathiou , Georgios Vernardos , Elias Polytarchos , Konstantinos Kazakos On Distributed Reconfigurable Systems: Open Problems and Some Initial Solutions. [Citation Graph (0, 0)][DBLP ] Conf ] 