Conferences in DBLP
Wim J. C. Melis , Peter Y. K. Cheung , Wayne Luk Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Kuen Hung Tsoi , Kin-Hong Lee , Philip Heng Wai Leong A Massively Parallel RC4 Key Search Engine. [Citation Graph (0, 0)][DBLP ] Conf ] Tulika Mitra , Tzi-cker Chiueh An FPGA Implementation of Triangle Mesh Decompression. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon J. Brebner Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro. [Citation Graph (0, 0)][DBLP ] Conf ] Todd S. Sproull , John W. Lockwood , David E. Taylor Control and Configuration Software for a Reconfigurable Networking Hardware Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Mihai Budiu , Mahim Mishra , Ashwin R. Bharambe , Seth Copen Goldstein Peer-to-Peer Hardware-Software Interfaces for Reconfigurable Fabrics. [Citation Graph (0, 0)][DBLP ] Conf ] Oskar Mencer PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Heidi E. Ziegler , Byoungro So , Mary W. Hall , Pedro C. Diniz Coarse-Grain Pipelining on Multiple FPGA Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Hezel , Andreas Kugel , Reinhard Männer , Dariu Gavrila FPGA-Based Template Matching Using Distance Transforms. [Citation Graph (0, 0)][DBLP ] Conf ] Jörn Gause , Peter Y. K. Cheung , Wayne Luk Reconfigurable Shape-Adaptive Template Matching Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Brad L. Hutchings , R. Franklin , D. Carver Assisting Network Intrusion Detection with Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Bellows , Jaroslav Flidr , Tom Lehman , Brian Schott , Keith D. Underwood GRIP: A Reconfigurable Architecture for Host-Based Gigabit-Rate Packet Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Gokhan Memik , Seda Ogrenci Memik , William H. Mangione-Smith Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Greg Stitt , Brian Grattan , Jason R. Villarreal , Frank Vahid Using On-Chip Configurable Logic to Reduce Embedded System Software Energy. [Citation Graph (0, 0)][DBLP ] Conf ] Herman Schmit , Benjamin A. Levine , Benjamin Ylvisaker Queue Machines: Hardware Compilation in Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Plessl , Marco Platzner Custom Computing Machines for the Set Covering Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Benjamin Carrión Schäfer , Steven F. Quigley , Andrew H. C. Chan Analysis and Implementation of the Discrete Element Method Using a Dedicated Highly Parallel Architecture in Reconfigurable Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Gerhard Lienhart , Andreas Kugel , Reinhard Männer Using Floating-Point Arithmetic on FPGAs to Accelerate Scientific N-Body Simulations. [Citation Graph (0, 0)][DBLP ] Conf ] Rong Yan , Seth Copen Goldstein Mobile Memory: Improving Memory Locality in Very Large Reconfigurable Fabrics. [Citation Graph (0, 0)][DBLP ] Conf ] André DeHon , Randy Huang , John Wawrzynek Hardware-Assisted Fast Routing. [Citation Graph (0, 0)][DBLP ] Conf ] George A. Constantinides , Peter Y. K. Cheung , Wayne Luk Optimum Wordlength Allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Mark L. Chang , Scott Hauck Précis: A Design-Time Precision Analysis Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Dhananjay Kulkarni , Walid A. Najjar , Robert Rinker , Fadi J. Kurdahi Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas W. Fry , Scott Hauck Hyperspectral Image Compression on Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Mihai Sima , Sorin Cotofana , Stamatis Vassiliadis , Jos T. J. van Eijndhoven , Kees A. Vissers MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64. [Citation Graph (0, 0)][DBLP ] Conf ] Hossam A. ElGindy , Yen-Liang Shue On Sparse Matrix-Vector Multiplication with FPGA-Based System. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen J. Melnikoff , Steven F. Quigley , Martin J. Russell Implementing a Simple Continuous Speech Recognition System on an FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Cyprian Grassmann , Joachim K. Anlauf RACER - A Rapid Prototyping Accelerator for Pulsed Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Henry Styles , Wayne Luk Accelerating Radiosity Calculations Using Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] N. A. Reis , José T. de Sousa On Implementing a Configware/Software SAT Solver. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan E. Scalera , Creed F. Jones III , Maneesh Soni , Mark B. Bucciero , Peter M. Athanas , A. Lynn Abbott , Amitabh Mishra Reconfigurable Object Detection in FLIR Image Sequences. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Necker , Didier Contis , David E. Schimmel TCP-Stream Reassembly and State Tracking in Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] João M. P. Cardoso , Markus Weinhardt Fast and Guaranteed C Compilation onto the PACT-XPP? Reconfigurable Computing Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Koch , Nico Kasprzyk Module Generators Driving the Compilation for Adaptive Computing Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Tero Rissa , Milan Vasilko , Jarkko Niittylahti System-Level Modelling and Implementation Technique for Run-Time Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Theerayod Wiangtong , Peter Y. K. Cheung , Wayne Luk Tabu Search with Intensification Strategy for Functional Partitioning in Hardware-Software Codesign. [Citation Graph (0, 0)][DBLP ] Conf ] J. Greg Nash Automatic Latency-Optimal Design of FPGA-Based Systolic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] A. P. Wim Böhm , J. Ross Beveridge , Bruce A. Draper , Charlie Ross , Monica Chawathe , Walid A. Najjar Compiling ATR Probing Codes for Execution on FPGA Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Nicholas Weaver , John Wawrzynek The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Yokota , Masamichi Nagafuchi , Yoshito Mekada , Tsutomu Yoshinaga , Kanemitsu Ootsu , Takanobu Baba A Scalable FPGA-Based Custom Computing Machine for a Medical Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Joshua D. Walstrom , Jeffrey J. Cook , Derek B. Gottlieb , Steve Ferrera , Chi-Wei Wang , Nicholas P. Carter The Design of the Amalgam Reconfigurable Cluster. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey J. Cook , Derek B. Gottlieb , Joshua D. Walstrom , Steve Ferrera , Chi-Wei Wang , Nicholas P. Carter Mapping Algorithms to the Amalgam Programmable-Reconfigurable Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Altaf Abdul Gaffar , Wayne Luk , Peter Y. K. Cheung , Nabeel Shirazi Customising Floating-Point Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Courtney , Richard H. Turner , Roger Woods Mapping Multi-Mode Circuits to LUT-Based FPGA Using Embedded MUXes. [Citation Graph (0, 0)][DBLP ] Conf ] 