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Conferences in DBLP

Field-Programmable Custom Computing Machines (FCCM) (fccm)
1997 (conf/fccm/1997)

  1. Norman Margolus
    An FPGA architecture for DRAM-based systolic computations. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:2-11 [Conf]
  2. John R. Hauser, John Wawrzynek
    Garp: a MIPS processor with a reconfigurable coprocessor. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:12-21 [Conf]
  3. Steven Trimberger, Dean Carberry, Anders Johnson, Jennifer Wong
    A time-multiplexed FPGA. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:22-29 [Conf]
  4. John T. McHenry, Patrick W. Dowd, Frank A. Pellegrino, Todd M. Carrozzi, W. B. Cocks
    An FPGA-based coprocessor for ATM firewalls. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:30-39 [Conf]
  5. Tom McDermott, Philip J. Ryan, Mark Shand, David J. Skellern, Terry Percival, Neil Weste
    A wireless LAN demodulator in a Pamette: design and experience. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:40-46 [Conf]
  6. Herman Schmit
    Incremental reconfiguration for pipelined applications. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:47-55 [Conf]
  7. Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung
    Compilation tools for run-time reconfigurable designs. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:56-65 [Conf]
  8. Jim Burns, Adam Donlin, Jonathan Hogg, Satnam Singh, Mark De Wit
    A dynamic reconfiguration run-time system. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:66-76 [Conf]
  9. Gordon J. Brebner
    The swappable logic unit: a paradigm for virtual hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:77-86 [Conf]
  10. Scott Hauck, Thomas W. Fry, Matthew M. Hosler, Jeffrey P. Kao
    The Chimaera reconfigurable functional unit. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:87-97 [Conf]
  11. Ray A. Bittner, Peter M. Athanas
    Computing kernels implemented with a wormhole RTR CCM. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:98-105 [Conf]
  12. Carl Ebeling, Darren C. Cronquist, Paul Franklin, Jason Secosky, Stefan G. Berg
    Mapping applications to the RaPiD configurable architecture. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:106-115 [Conf]
  13. W. Bruce Culbertson, Rick Amerson, Richard J. Carter, Philip Kuekes, Greg Snider
    Defect tolerance on the Teramac custom computer. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:116-124 [Conf]
  14. Laurent Moll, Mark Shand
    Systems performance measurement on PCI Pamette. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:125-133 [Conf]
  15. Jonathan Babb, Matthew Frank, Victor Lee, Elliot Waingold, Rajeev Barua, Michael Taylor, Jang Kim, Devabhaktuni Srikrishna, Anant Agarwal
    The RAW benchmark suite: computation structures for general purpose computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:134-144 [Conf]
  16. Qiang Wang, David M. Lewis
    Automated field-programmable compute accelerator design using partial evaluation. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:145-154 [Conf]
  17. Roger Woods, Stefan H.-M. Ludwig, Jean-Paul Heron, David W. Trainor, Stephan W. Gehring
    FPGA synthesis on the XC6200 using IRIS and Trianus/Hades (or from heaven to hell and back again). [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:155-164 [Conf]
  18. Maya Gokhale, D. Gomersall
    High level compilation for fine grained FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:165-174 [Conf]
  19. Pak K. Chan, Martine D. F. Schlag
    Acceleration of an FPGA router. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:175-181 [Conf]
  20. Miron Abramovici, Premachandran R. Menon
    Fault simulation on reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:182-191 [Conf]
  21. Michael Rencher, Brad L. Hutchings
    Automated target recognition on SPLASH 2. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:192-200 [Conf]
  22. John Woodfill, Brian Von Herzen
    Real-time stereo vision on the PARTS reconfigurable computer. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:201-210 [Conf]
  23. Jack Greenbaum, Michael Baxter
    Increased FPGA capacity enables scalable, flexible CCMs: an example from image processing. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:211-218 [Conf]
  24. Christof Paar, Martin Rosner
    Comparison of arithmetic architectures for Reed-Solomon decoders in reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:219-225 [Conf]
  25. Yamin Li, Wanming Chu
    Implementation of single precision floating point square root on FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:226-233 [Conf]
  26. Timothy J. Callahan, John Wawrzynek
    Datapath-oriented FPGA mapping and placement for configurable computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:234-235 [Conf]
  27. Steven H. Kelem
    Mapping a real-time video algorithm to a context-switched FPGA. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:236-237 [Conf]
  28. Uwe Tangen, Ludger Schulte, John S. McCaskill
    A parallel hardware evolvable computer POLYP. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:238-239 [Conf]
  29. Glenn H. Chapman, Benoit Dufort
    Laser defect correction applications to FPGA based custom computers. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:240-241 [Conf]
  30. Hyun-Kyu Yun, Aaron Smith, Harvey F. Silverman
    Speech recognition HMM training on reconfigurable parallel processor. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:242-243 [Conf]
  31. Neil W. Bergmann, Yuk Ying Chung, Bernard K. Gunther
    Efficient implementation of the DCT on custom computers. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:244-245 [Conf]
  32. Jason Cong, John Peck
    On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:246-248 [Conf]
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