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Conferences in DBLP

Field-Programmable Custom Computing Machines (FCCM) (fccm)
2004 (conf/fccm/2004)

  1. Philip James-Roxby, Gordon J. Brebner, Dennis Bemmann
    Time-Critical Software Deceleration in an FCCM. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:3-12 [Conf]
  2. André DeHon, Joshua Adams, Michael DeLorimier, Nachiket Kapre, Yuki Matsuda, Helia Naeimi, Michael C. Vanier, Michael G. Wrighton
    Design Patterns for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:13-23 [Conf]
  3. Miljan Vuletic, Laura Pozzi, Paolo Ienne
    Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:24-33 [Conf]
  4. David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee
    Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:37-46 [Conf]
  5. Jingzhao Ou, Viktor K. Prasanna
    PyGen: A MATLAB/Simulink Based Tool for Synthesizing Parameterized and Energy Efficient Designs Using FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:47-56 [Conf]
  6. Mark L. Chang, Scott Hauck
    Automated Least-Significant Bit Datapath Optimization for FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:59-67 [Conf]
  7. Kuen Hung Tsoi, Chun Hok Ho, H. C. Yeung, Philip Heng Wai Leong
    An Arithmetic Library and Its Application to the N-body Problem. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:68-78 [Conf]
  8. Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung
    Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:79-88 [Conf]
  9. Jian Liang, Russell Tessier, Dennis Goeckel
    A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:91-100 [Conf]
  10. Dong-U Lee, Wayne Luk, Connie Wang, Christopher Jones, Michael Smith, John D. Villasenor
    A Flexible Hardware Encoder for Low-Density Parity-Check Codes. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:101-111 [Conf]
  11. Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West
    ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:115-124 [Conf]
  12. Young H. Cho, William H. Mangione-Smith
    Deep Packet Filter with Dedicated Logic and Read Only Memories. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:125-134 [Conf]
  13. Zachary K. Baker, Viktor K. Prasanna
    A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:135-144 [Conf]
  14. Miriam Leeser, Shawn Miller, Haiqian Yu
    Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:147-155 [Conf]
  15. James P. Durbano, Fernando E. Ortiz, John R. Humphrey, Petersen F. Curt, Dennis W. Prather
    FPGA-Based Acceleration of the 3D Finite-Difference Time-Domain Method. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:156-163 [Conf]
  16. Hassan Al Atat, Iyad Ouaiss
    Register Binding for FPGAs with Embedded Memory. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:167-175 [Conf]
  17. Mehdi Baradaran Tahoori, Subhasish Mitra
    Defect and Fault Tolerance of Reconfigurable Molecular Computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:176-185 [Conf]
  18. Maya Gokhale, Christine Ahrens, Janette Frigo, Christophe Wolinski
    Communications Scheduling for Concurrent Processes on Reconfigurable Computers. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:186-193 [Conf]
  19. Navid Azizi, Ian Kuon, Aaron Egier, Ahmad Darabiha, Paul Chow
    Reconfigurable Molecular Dynamics Simulator. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:197-206 [Conf]
  20. He Chuan, Mi Lu, Chuanwen Sun
    Accelerating Seismic Migration Using FPGA-Based Coprocessor Platform. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:207-216 [Conf]
  21. Keith D. Underwood, K. Scott Hemmert
    Closing the Gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS Performance. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:219-228 [Conf]
  22. Christopher C. Doss, Robert L. Riley Jr.
    FPGA-Based Implementation of a Robust IEEE-754 Exponential Unit. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:229-238 [Conf]
  23. Steven D. Krueger, Peter-Michael Seidel
    Design of an On-Line IEEE Floating-Point Addition Unit for FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:239-246 [Conf]
  24. Christopher R. Clark, David E. Schimmel
    Scalable Pattern Matching for High Speed Networks. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:249-257 [Conf]
  25. Ioannis Sourdis, Dionisios N. Pnevmatikatos
    Pre-Decoded CAMs for Efficient and High-Speed NIDS Pattern Matching. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:258-267 [Conf]
  26. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
    A Structured System Methodology for FPGA Based System-on-A-Chip Design. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:271-272 [Conf]
  27. Emre Özer, Andy Nisbet, David Gregg
    Fine-Tuning Loop-Level Parallelism for Increasing Performance of DSP Applications on FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:273-274 [Conf]
  28. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
    Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:275-276 [Conf]
  29. Gregory V. Larchev, Jason D. Lohn
    Hardware-in-the-Loop Evolution of a 3-bit Multiplier. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:277-278 [Conf]
  30. Ciaran McIvor, Máire McLoone, John V. McCanny
    FPGA Montgomery Multiplier Architectures - A Comparison. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:279-282 [Conf]
  31. Sebastian Wallner
    Design Methodology of a Configurable System-on-Chip Architecture. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:283-284 [Conf]
  32. George A. Constantinides, Abunaser Miah, Nalin Sidahao
    Word-Length Optimization of Folded Polynomial Evaluation. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:285-286 [Conf]
  33. Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung
    Migrating Functionality from ROMS to Embedded Multipliers. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:287-288 [Conf]
  34. David Wentzlaff, Anant Agarwal
    A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level Computation. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:289-290 [Conf]
  35. Valeri F. Tomashau, Tom Kean
    Validation of an Advanced Encryption Standard (AES) IP Core. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:291-292 [Conf]
  36. Sami Khawam, Tughrul Arslan, Fred Westall
    Unidirectional Switch-Boxes for Synthesizable Reconfigurable Arrays. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:293-295 [Conf]
  37. Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis
    The MOLEN Processor Prototype. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:296-299 [Conf]
  38. Tom Van Court, Yongfeng Gu, Martin C. Herbordt
    FPGA Acceleration of Rigid Molecule Interactions. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:300-301 [Conf]
  39. Phil James-Roxby, Paul R. Schumacher, Charlie Ross
    A Single Program Multiple Data Parallel Processing Platform for FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:302-303 [Conf]
  40. Sebastian Lange, Martin Middendorf
    Hyperreconfigurable Architectures for Fast Run Time Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:304-305 [Conf]
  41. Gerardo Leyva, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz
    A Generator of High-Speed Floating-Point Modules. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:306-307 [Conf]
  42. Alireza Hodjat, Ingrid Verbauwhede
    A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:308-309 [Conf]
  43. Warren J. Gross, Frank R. Kschischang, P. Glenn Gulak
    An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:310-311 [Conf]
  44. Dirk Eilers, Helmut Steckenbiller, Andreas Herkersdorf
    Buffer Schemes for Runtime Reconfiguration of Function Variants in Communication Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:312-315 [Conf]
  45. Long Bu, John A. Chandy
    FPGA Based Network Intrusion Detection using Content Addressable Memories. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:316-317 [Conf]
  46. Charlie Ross, A. P. Wim Böhm
    Using FIFOs in Hardware-Software Co-Design for FPGA Based Embedded Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:318-319 [Conf]
  47. Jianchun Li, Christos A. Papachristou, Raj Shekhar
    A Reconfigurable SoC Architecture and Caching Scheme for 3D Medical Image Processing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:320-321 [Conf]
  48. Michael Attig, Sarang Dharmapurikar, John W. Lockwood
    Implementation Results of Bloom Filters for String Matching. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:322-323 [Conf]
  49. Daniel J. Allred, Walter Huang, Venkatesh Krishnan, Heejong Yoo, David V. Anderson
    An FPGA Implementation for a High Throughput Adaptive Filter Using Distributed Arithmetic. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:324-325 [Conf]
  50. Rajarshi Mukherjee, Seda Ogrenci Memik
    Power Management for FPGAs: Power-Driven Design Partitioning. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:326-327 [Conf]
  51. Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima
    Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:328-329 [Conf]
  52. Deepak Boppana, Kully Dhanoa, Jesse Kempa
    FPGA based Embedded Processing Architecture for the QRD-RLS Algorithm. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:330-331 [Conf]
  53. Andrea Cappelli, Andrea Lodi, Claudio Mucci, Mario Toma, Fabio Campi
    A Dataflow Control Unit for C-to-Configurable Pipelines Compilation Flow. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:332-333 [Conf]
  54. Haoyu Song, Jing Lu, John W. Lockwood, James Moscola
    Secure Remote Control of Field-programmable Network Devices. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:334-335 [Conf]
  55. Neil Steiner, Peter M. Athanas
    An Alternate Wire Database for Xilinx FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:336-337 [Conf]
  56. Sumit Mohanty, Viktor K. Prasanna
    Duty Cycle Aware Application Design using FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:338-339 [Conf]
  57. Shawn Phillips, Akshay Sharma, Scott Hauck
    Automating the Layout of Reconfigurable Subsystems Via Template Reduction. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:340-341 [Conf]
  58. Matthias Dyer, Marco Platzner, Lothar Thiele
    Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:342-344 [Conf]
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