Conferences in DBLP
Takashi Miyamori , Kunle Olukotun A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Csaba Andras Moritz , Donald Yeung , Anant Agarwal Exploring Optimal Cost-Performance Designs for Raw Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Charlé R. Rupp , Mark Landguth , Tim Garverick , Edson Gomersall , Harry Holt , Jeffrey M. Arnold , Maya Gokhale The NAPA Adaptive Processing Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Steven Swanchara , Scott J. Harper , Peter M. Athanas A Stream-Based Configurable Computing Radio Testbed. [Citation Graph (0, 0)][DBLP ] Conf ] Apostolos Dollas , Euripides Sotiriades , Apostolos Emmanouelides Architecture and Design of GE1, a FCCM for Golomb Ruler Derivation. [Citation Graph (0, 0)][DBLP ] Conf ] Akihisa Ohta , Tsuyoshi Isshiki , Hiroaki Kunieda New FPGA Architecture for Bit-Serial Pipeline Datapath. [Citation Graph (0, 0)][DBLP ] Conf ] Kouichi Nagami , Kiyoshi Oguri , Tsunemichi Shiozawa , Hideyuki Ito , Ryusuke Konishi Plastic Cell Architecture: Towards Reconfigurable Computing for General-Purpose. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen M. Scalera , Jóse R. Vázquez The Design and Implementation of a Context Switching FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Rhett D. Hudson , David I. Lehn , Peter M. Athanas A Run-Time Reconfigurable Engine for Image Interpolation. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Shand , Laurent Moll Hardware/Software Integration in Solar Polarimetry. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew A. Duncan , David C. Hendry , Peter Gray An Overview of the COBRA-ABS High Level Synthesis System for Multi-FPGA Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Darren C. Cronquist , Paul Franklin , Stefan G. Berg , Carl Ebeling Specifying and Compiling Applications for RaPiD. [Citation Graph (0, 0)][DBLP ] Conf ] Maya Gokhale , Janice M. Stone NAPA C: Compiling for a Hybrid RISC/FPGA Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Hauck , Zhiyuan Li , Eric J. Schwabe Configuration Compression for the Xilinx XC6200 FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Nabeel Shirazi , Wayne Luk , Peter Y. K. Cheung Automating Production of Run-Time Reconfigurable Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Chu , Nicholas Weaver , Kolja Sulimma , André DeHon , John Wawrzynek Object Oriented Circuit-Generators in Java. [Citation Graph (0, 0)][DBLP ] Conf ] Oskar Mencer , Martin Morf , Michael J. Flynn PAM-Blox: High Performance FPGA Design for Adaptive Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Bellows , Brad L. Hutchings JHDL - An HDL for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Peixin Zhong , Margaret Martonosi , Pranav Ashar , Sharad Malik Accelerating Boolean Satisfiability with Configurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Azra Rashid , Jason Leonard , William H. Mangione-Smith Dynamic Circuit Generation for Solving Specific Problem Instances of Boolean Satisfiability. [Citation Graph (0, 0)][DBLP ] Conf ] Walter B. Ligon III , Scott McMillan , Greg Monn , Kevin Schoonover , Fred Stivers , Keith D. Underwood A Re-evaluation of the Practicality of Floating-Point Operations on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandre F. Tenca , Milos D. Ercegovac A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Simon D. Haynes , Peter Y. K. Cheung A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure. [Citation Graph (0, 0)][DBLP ] Conf ] Satnam Singh , Robert Slous Accelerating Adobe Photoshop with the Reconfigurable Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Karlheinz Weiß , Ronny Kistner , Arno Kunzmann , Wolfgang Rosenstiel Analysis of the XC6000 Architecture for Embedded System Design. [Citation Graph (0, 0)][DBLP ] Conf ] Philip Heng Wai Leong , P. K. Tsang , T. K. Lee A FPGA Based Forth Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Tsuyoshi Hamada , Toshiyuki Fukushige , Atsushi Kawai , Joshiyuki Makino PROGRAPE-1: A Programmable Special-Purpose Computer for Many-Body Simulations. [Citation Graph (0, 0)][DBLP ] Conf ] José Carlos Alves , José Silva Matos RVC - A Reconfigurable Coprocessor for Vector Processing Applications. [Citation Graph (0, 0)][DBLP ] Conf ] I. M. Bland , Graham M. Megson The Systolic Array Genetic Algorithm, An Example of Systolic Arrays as a Reconfigurable Design Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Kugel , Klaus Kornmesser , R. Lay , J. Ludvig , Reinhard Männer , K. H. Noffz , Stephan Rühl , M. Sessler , Harald Simmler , Holger Singpiel 50 kHz Pattern Recognition on the Large FPGA Processor Enable++. [Citation Graph (0, 0)][DBLP ] Conf ] Masato Motomura , Yoshiharu Aimoto , Atsufkni Shibayama , Yoshikazu Yabe , Masakazu Yamashina An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey M. Arnold Mapping the MD5 Hash Algorithm onto the NAPA Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Apostolos Dollas , Euripides Sotiriades , Apostolos Emmanouelides , Lee House General Purpose vs. Custom FCCM's: a Comparison of Splash2, Quickturn RPM, and GE1 for Golomb Ruler Derivation. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey M. Arnold An Architecture Simulator for National Semiconductor's Adaptive Processing Architecture (NAPA). [Citation Graph (0, 0)][DBLP ] Conf ] S. Kumar , Luiz Pires , D. Pandalai , M. Vojta , J. Golusky , S. Wadi , Henk A. E. Spaanenburg Benchmarking Technology for Configurable Computing System. [Citation Graph (0, 0)][DBLP ] Conf ] M. F. Sakr , Steven P. Levitan , C. Lee Giles , Donald M. Chiarulli Reconfigurable Processor Architectures Exploiting High Bandwidth Optical Channels. [Citation Graph (0, 0)][DBLP ] Conf ] André Stauffer , Moshe Sipper , Andrés Pérez-Uribe Some Applications of FPGAs in Bio-Inspired Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] João Canas Ferreira , José Silva Matos A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Ruth Sivilotti , Young Cho , Wen-King Su , Danny Cohen , Brian Bray Scalable Network Based FPGA Accelerators for an Automatic Target Recognition Application. [Citation Graph (0, 0)][DBLP ] Conf ] T. K. Lee , Philip Heng Wai Leong , K. H. Lee , K. T. Chan , S. K. Hui , H. K. Yeung , M. F. Lo , J. H. M. Lee An FPGA Implementation of GENET for Solving Graph Coloring Problems . [Citation Graph (0, 0)][DBLP ] Conf ] Stephen P. Crago , Brian Schott , Robert Parker SLAAC: A Distributed Architecture for Adaptive Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Jacques-Olivier Haenni , Jean-Luc Beuchat , Eduardo Sanchez RENCO: A Reconfigurable Network Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Emeka Mosanya , Jean-Michel Puiatti , Eduardo Sanchez Hardware Implementation of Generalized Profile Search on the GENSTORM Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Hagen Ploog , Dirk Timmermann FPGA-Based Architecture Evaluation of Cryptographic Coprocessors for Smartcards. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew Moe , Herman Schmit , Seth Copen Goldstein Characterization and Parameterization of a Pipeline Reconfigurable FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Donald L. Hung , Jun Wang A FPGA-Based Custom Computing System for Solving the Assignment Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon J. Brebner Circlets: Circuits as Applets. [Citation Graph (0, 0)][DBLP ] Conf ] Jack S. N. Jean , Karen A. Tomko , Vikram Yavagal , Robert Cook , Jignesh Shah Dynamic Reconfiguration to Support Concurrent Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Pascal Poiré , Marc-André Cantin , Hervé Daniel , Yves Blaquière , Yvon Savaria A Comparative Analysis of Fuzzy ART Neural Network Implementations: The Advantages of Reconfigurable Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Graham , Brent E. Nelson Frequency-Domain Sonar Processing in FPGAs and DSPs. [Citation Graph (0, 0)][DBLP ] Conf ] Nicholas McKay , Thomas F. Melham , Kong Woei Susanto , Satnam Singh Dynamic Specialization of XC6200 FPGAs by Partial Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Kean , Ann Duncan DES Key Breaking, Encryption and Decryption on the XC6216. [Citation Graph (0, 0)][DBLP ] Conf ] Sriram Govindarajan , Iyad Ouaiss , Meenakshi Kaul , Vinoo Srinivasan , Ranga Vemuri An Effective Design System for Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Dandalis , Viktor K. Prasanna Mapping Homogeneous Computations onto Dynamically Configurable Coarse-Grained Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Sakir Sezer , Roger Woods , Jean-Paul Heron , Alan Marshall Fast Partial Reconfiguration for FCCMs. [Citation Graph (0, 0)][DBLP ] Conf ] Gunter Haug , Wolfgang Rosenstiel Reconfigurable Hardware as Shared Resource for Parallel Threads. [Citation Graph (0, 0)][DBLP ] Conf ] Hanho Lee , Gerald E. Sobelman Digit-Serial DSP Library for Optimized FPGA Configuration. [Citation Graph (0, 0)][DBLP ] Conf ] Pedro Merino , Margarida F. Jacome , Juan Carlos López A Methodology for Task Based Partitioning and Scheduling of Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Goran Doncev , Miriam Leeser , Shantanu Tarafdar High Level Synthesis for Designing Custom Computing Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Karthikeya M. Gajjala Purna , Dinesh Bhatia Temporal Partitioning and Scheduling for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Luiz Maltar , Felipe M. G. França , Vladimir Castro Alves , Cláudio L. Amorim Implementation of RNS Addition and RNS Multiplication into FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Al Walters , Peter Athanas A Scalable FIR Filter Using 32-bit Floating-Point Complex Arithmetic on a Configurable Computing Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Nikhil D. Gupta , John K. Antonio , Jack M. West Reconfigurable Computing for Space-Time Adaptive Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Manoucher Shaditalab , Guy Bois , Mohamad Sawan Self Sorting Radix_2 FFT on FPGA using Parallel Pipelined Distributed Arithmetic Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Donald Soderman , Yuri Panchul Implementing C Algorithms in Reconfigurable Hardware Using C2Verilog. [Citation Graph (0, 0)][DBLP ] Conf ] 