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Conferences in DBLP

Field-Programmable Custom Computing Machines (FCCM) (fccm)
1999 (conf/fccm/1999)

  1. João M. P. Cardoso, Horácio C. Neto
    Macro-Based Hardware Compilation of Java(tm) Bytecodes into a Dynamic Reconfigurable Computing System. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:2-11 [Conf]
  2. Brad L. Hutchings, Peter Bellows, Joseph Hawkins, K. Scott Hemmert, Brent E. Nelson, Mike Rytting
    A CAD Suite for High-Performance FPGA Design. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:12-24 [Conf]
  3. Satnam Singh, Carl Johan Lillieroth
    Formal Verification of Reconfigurable Cores. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:25-0 [Conf]
  4. Toshiaki Miyazaki, Takahiro Murooka, Masaru Katayama, Atsushi Takahara
    Transmutable Telecom System and Its Application. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:34-43 [Conf]
  5. Jason R. Hess, David C. Lee, Scott J. Harper, Mark T. Jones, Peter M. Athanas
    Implementation and Evaluation of a Prototype Reconfigurable Router. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:44-0 [Conf]
  6. Markus Weinhardt, Wayne Luk
    Pipeline Vectorization for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:52-62 [Conf]
  7. Maya Gokhale, Janice M. Stone
    Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory Banks. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:63-69 [Conf]
  8. Jonathan Babb, Martin C. Rinard, Csaba Andras Moritz, Walter Lee, Matthew Frank, Rajeev Barua, Saman P. Amarasinghe
    Parallelizing Applications into Silicon. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:70-0 [Conf]
  9. Michael R. Piacentino, Gooitzen S. van der Wal, Michael W. Hansen
    Reconfigurable Elements for a Video Pipeline Processor. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:82-91 [Conf]
  10. Bernardo Kastrup, Arjan Bink, Jan Hoogerbrugge
    ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:92-0 [Conf]
  11. Srihari Cadambi, Seth Copen Goldstein
    CPR: A Configuration Profiling Tool. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:104-113 [Conf]
  12. Nicholas McKay, Satnam Singh
    Debugging Techniques for Dynamically Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:114-122 [Conf]
  13. Milan Vasilko, David Cabanis
    Improving Simulation Accuracy in Design Methodologies for Dynamically Reconfigurable Logic Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:123-0 [Conf]
  14. Wayne Luk, T. K. Lee, J. Rice, Nabeel Shirazi, Peter Y. K. Cheung
    Reconfigurable Computing for Augmented Reality. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:136-145 [Conf]
  15. Laurent Moll, Mark Shand, Alan Heirich
    Sepia: Scalable 3D Compositing Using PCI Pamette. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:146-0 [Conf]
  16. Zhen Luo, Margaret Martonosi, Pranav Ashar
    An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:158-167 [Conf]
  17. José Carlos Alves, João Canas Ferreira, C. Albuquerque, José F. Oliveira, J. Soeiro Ferreira, José Silva Matos
    FAFNER-Accelerating Nesting Problems with FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:168-0 [Conf]
  18. Tyler J. Moeller, David R. Martinez
    Field Programmable Gate Array Based Radar Front-End Digital Signal Processing. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:178-187 [Conf]
  19. Dan Benyamin, John D. Villasenor, Wayne Luk
    Optimizing FPGA-Based Vector Product Designs. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:188-0 [Conf]
  20. Ronald Laufer, R. Reed Taylor, Herman Schmit
    PCI-PipeRench and the SWORDAPI: A System for Stream-Based Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:200-208 [Conf]
  21. Andrew A. Chien, Jay H. Byun
    Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:209-221 [Conf]
  22. Mark Jones, Luke Scharf, Jonathan Scott, Chris Twaddle, Matthew Yaconis, Kuan Yao, Peter Athanas, Brian Schott
    Implementing an API for Distributed Adaptive Computing Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:222-0 [Conf]
  23. Gerardo Orlando, Christof Paar
    A Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:232-239 [Conf]
  24. M. P. Leong, M. Y. Yeung, C. K. Yeung, C. W. Fu, P. A. Heng, Philip Heng Wai Leong
    Automatic Floating to Fixed Point Translation and its Application to Post-Rendering 3D Warping. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:240-248 [Conf]
  25. Kiran Bondalapati, Viktor K. Prasanna
    Dynamic Precision Management for Loop Computations on Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:249-0 [Conf]
  26. Jean-Paul Heron, Roger Woods
    Accelerating Run-Time Reconfiguration on FCCMs. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:260-261 [Conf]
  27. Richard H. Turner, Roger Woods, Sakir Sezer, Jean-Paul Heron
    A Virtual Hardware Handler for RTR Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:262-263 [Conf]
  28. Eric K. Pauer, Paul D. Fiore, John M. Smith
    Algorithm Analysis and Mapping Environment for Adaptive Computing Systems: Further Results. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:264-265 [Conf]
  29. Valery Sklyarov, J. Fonseca, Ricardo Sal Monteiro, Arnaldo Oliveira, Andreia Melo, Nuno Lau, Iouliia Skliarova, P. Neves, António de Brito Ferrari
    Development System for FPGA-Based Digital Circuits. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:266-267 [Conf]
  30. Cynthia Cousineau, François Laperle, Yvon Savaria
    Design of a JTAG Based Run Time Reconfigurable System. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:268-269 [Conf]
  31. Brian Schott, Chen Chen, Steve Crago, Joseph Czarnaski, Matt French, Ivan Hom, Tam Tho, Terri Valenti
    Architectures for System-Level Applications of Adaptive Computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:270-27 [Conf]
  32. Vinoo Srinivasan, Ranga Vemuri
    Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:272-0 [Conf]
  33. Andreas Koch
    Enabling Automatic Module Generation for FCCM Compilers. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:274-0 [Conf]
  34. Michael Baxter
    ICARUS: A Dynamically Reconfigurable Computer Architecture. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:278-0 [Conf]
  35. Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone
    SONIC - A Plug-In Architecture for Video Processing. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:280-281 [Conf]
  36. Christof Teuscher, Jacques-Olivier Haenni, Héctor Fabio Restrepo, Eduardo Sanchez, Francisco J. Gómez
    A Reconfigurable Platform for Academic Purposes. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:282-283 [Conf]
  37. James Hwang, Cameron Patterson, Sujoy Mitra
    VHDL Placement Directives for Parametric IP Blocks. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:284-285 [Conf]
  38. Scott Hauck, William D. Wilson
    Runlength Compression Techniques for FPGA Configurations. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:286-0 [Conf]
  39. Jack S. N. Jean, Xuejun Liang, Brian Drozd, Karen A. Tomko
    Accelerating an IR Automatic Target Recognition Application with FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:290-291 [Conf]
  40. Benjamin A. Levine, Senthil Natarajan, Chandra Tan, Danny Newport, Donald W. Bouldin
    Mapping of an Automated Target Recognition Application from a Graphical Software Environment to FPGA-Based Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:292-293 [Conf]
  41. Deepali Deshpande, Arun K. Somani, Akhilesh Tyagi
    Hybrid Data/Configuration Caching for Striped FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:294-295 [Conf]
  42. Hue-Sung Kim, Arun K. Somani, Akhilesh Tyagi
    On Reconfiguring Cache for Computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:296-297 [Conf]
  43. Ronald D. Williams, Brian D. Kuebert
    Reconfigurable Pipelines in VLIW Execution Units. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:298-299 [Conf]
  44. Kiarash Barzagan, Majid Sarrafzadeh
    Fast Online Placement for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:300-0 [Conf]
  45. Lijun Gao, Sarvesh Shrivastava, Hanho Lee, Gerald E. Sobelman
    A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:304-305 [Conf]
  46. Miron Abramovici, José T. de Sousa
    A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:306-307 [Conf]
  47. Pak K. Chan, Mark J. Boyd, S. Goren, K. Klenk, V. Kodavati, R. Kundu, M. Margolese, J. Sun, K. Suzuki, E. Thorne, X. Wang, J. Xu, M. Zhu
    Reducing Compilation Time of Zhong's FPGA-Based SAT Solver. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:308-309 [Conf]
  48. Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor
    FPGA-Based Structures for On-Line FFT and DCT. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:310-311 [Conf]
  49. Luiz Maltar, Felipe M. G. França, Vladimir Castro Alves, Cláudio L. Amorim
    An FPGA-Based Fan Beam Image Reconstruction Module. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:312-313 [Conf]
  50. Donald MacVicar, Satnam Singh, Robert Slous
    Be'zier Curve Rendering on Virtex(tm). [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:314-0 [Conf]
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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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