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Conferences in DBLP

Field-Programmable Custom Computing Machines (FCCM) (fccm)
2000 (conf/fccm/2000)

  1. L. Louis Zhang, Qiang Wang, David M. Lewis
    Design of a VLIW Compute Accelerator on the Transmogrifier-2. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:3-12 [Conf]
  2. Mark J. Boyd, Tracy Larrabee
    A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:13-21 [Conf]
  3. Zhiyuan Li, Katherine Compton, Scott Hauck
    Configuration Caching Management Techniques for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:22-38 [Conf]
  4. Prithviraj Banerjee, Nagaraj Shenoy, Alok N. Choudhary, Scott Hauck, C. Bachmann, Malay Haldar, Pramod G. Joisha, Alex K. Jones, Abhay Kanhere, Anshuman Nayak, S. Periyacheri, M. Walkden, David Zaretsky
    A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:39-48 [Conf]
  5. Maya Gokhale, Janice M. Stone, Jeffrey M. Arnold, Mirek Kalinowski
    Stream-Oriented FPGA Computing in the Streams-C High Level Language. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:49-58 [Conf]
  6. Stephen M. Scalera, Mark Falco, Brent E. Nelson
    A Reconfigurable Computing Architecture for Microsensors. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:59-67 [Conf]
  7. K. H. Leung, K. W. Ma, W. K. Wong, Philip Heng Wai Leong
    FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:68-76 [Conf]
  8. Henry Styles, Wayne Luk
    Customizing Graphics Applications: Techniques and Programming Interface. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:77-90 [Conf]
  9. Pedro C. Diniz, Joonseok Park
    Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:91-100 [Conf]
  10. Tsutomu Maruyama, Tsutomu Hoshino
    A C to HDL Compiler for Pipeline Processing on FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:101-112 [Conf]
  11. Cameron Patterson
    High Performance DES Encryption in Virtex(tm) FPGAs Using Jbits(tm). [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:113-121 [Conf]
  12. M. P. Leong, Ocean Y. H. Cheung, Kuen Hung Tsoi, Philip Heng Wai Leong
    A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:122-131 [Conf]
  13. Andreas Dandalis, Viktor K. Prasanna, José D. P. Rolim
    An Adaptive Cryptographic Engine for IPSec Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:132-144 [Conf]
  14. Satnam Singh
    Death of the RLOC? [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:145-152 [Conf]
  15. Philip James-Roxby, Steven A. Guccione
    Automated Extraction of Run-Time Parameterizable Cores from Programmable Device Configurations. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:153-164 [Conf]
  16. John M. Emmert, Charles E. Stroud, Brandon Skaggs, Miron Abramovici
    Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:165-174 [Conf]
  17. Shu-Yi Yu, Nirmal R. Saxena, Edward J. McCluskey
    An ACS Robotic Control Algorithm with Fault Tolerant Capabilities. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:175-184 [Conf]
  18. Steven K. Sinha, Peter Kamarchik, Seth Copen Goldstein
    Tunable Fault Tolerance for Runtime Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:185-194 [Conf]
  19. Chris Dick, Fred Harris, Michael Rice
    Synchronization in Software Radios-Carrier and Timing Recovery Using FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:195-204 [Conf]
  20. Ahmad Alsolaim, Janusz A. Starzyk, Jürgen Becker, Manfred Glesner
    Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:205-216 [Conf]
  21. Benjamin A. Levine, R. Reed Taylor, Herman Schmit
    Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:217-226 [Conf]
  22. Euripides Sotiriades, Apostolos Dollas, Peter Athanas
    Hardware-Software Codesign and Parallel Implementation of a Golomb Ruler Derivation Engine. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:227-235 [Conf]
  23. Cristian Ciressan, Eduardo Sanchez, Martin Rajman, Jean-Cédric Chappelier
    An FPGA-Based Coprocessor for the Parsing of Context-Free Grammars. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:236-248 [Conf]
  24. Wei-Je Huang, Nirmal R. Saxena, Edward J. McCluskey
    A Reliable LZ Data Compressor on Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:249-258 [Conf]
  25. Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi
    EVIDENCE: An FPGA-Based System for Photon EVent IDENtification and CEntroiding. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:259-266 [Conf]
  26. Michael J. Wirthlin, Steve Morrison, Paul Graham, Brian Bray
    Improving the Performance and Efficiency of an Adaptive Amplification Operation Using Configurable Hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:267-278 [Conf]
  27. Katherine Compton, James Cooley, Stephen Knol, Scott Hauck
    Configuration Relocation and Defragmentation for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:279-280 [Conf]
  28. Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara
    Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:281-282 [Conf]
  29. Shuichi Ichikawa, Lerdtanaseangtham Udorn, Kouji Konishi
    Hardware Accelerator for Subgraph Isomorphism Problems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:283-284 [Conf]
  30. K. Henriss, Peter Rüffer, Rolf Ernst, S. Hasenzahl
    A Reconfigurable Hardware Platform for Digital Real-Time Signal Processing in Television Studios. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:285-286 [Conf]
  31. Kamlesh Rath, Sirisha Tangirala, Patrick Friel, Poras T. Balsara, Jose Flores, John P. Wadley
    Reconfigurable Array Media Processor (RAMP). [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:287-288 [Conf]
  32. Hamish Fallside, Michael John Sebastian Smith
    Internet Connected FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:289-290 [Conf]
  33. Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano
    A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:291-294 [Conf]
  34. Yuichiro Shibata, Masaki Uno, Hideharu Amano, K. Furuta, Taro Fujii, Masato Motomura
    A Virtual Hardware System on a Dynamically Reconfigurable Logic Device. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:295-296 [Conf]
  35. Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh
    Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:297-298 [Conf]
  36. Jinwoo Suh, Dong-In Kang, Stephen P. Crago
    A Communication Scheduling Algorithm for Multi-FPGA Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:299-300 [Conf]
  37. L. Levinson, Reinhard Männer, M. Sessler, Harald Simmler
    Preemptive Multitasking on FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:301-302 [Conf]
  38. Aaron Schneider, Robert McIlhenny, Milos D. Ercegovac
    BigSky-An On-Line Arithmetic Design Tool for FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:303-304 [Conf]
  39. Paul Graham, Brad L. Hutchings, Brent E. Nelson
    Improving the FPGA Design Process through Determining and Applying Logical-to-Physical Design Mappings. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:305-306 [Conf]
  40. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
    Multiple Precision for Resource Minimization. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:307-308 [Conf]
  41. Oskar Mencer, Heiko Hübert, Martin Morf, Michael J. Flynn
    StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:309-312 [Conf]
  42. Tim Tuan, Miguel Figueroa, Frank Lind, Chucai Zhou, Chris Diorio, John Sahr
    An FPGA-Based Array Processor for an Ionospheric-Imaging Radar. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:313-314 [Conf]
  43. Nathaniel D. Daw, Seth Copen Goldstein, Dennis Strelow
    Embedded Compilation for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:315-316 [Conf]
  44. Kip Walker, Mihai Budiu, Seth Copen Goldstein
    Interfacing Reconfigurable Logic with a CPU. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:317-318 [Conf]
  45. Jonathan E. Scalera, Mark Jones
    A Run-Time Reconfigurable Plug-In for the Winamp MP3 Player. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:319-320 [Conf]
  46. Jim Harkin, T. Martin McGinnity, Liam P. Maguire
    Accelerating Embedded Applications using Dynamically Reconfigurable Hardware and Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:321-322 [Conf]
  47. Maria Imecs, Péter Bikfalvi, Sergiu Nedevschi, Józef Vásárhelyi
    Implementation of a Configurable Controller for an AC Drive Control: A Case Study. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:323-324 [Conf]
  48. Reinhard Männer, M. Sessler, Harald Simmler
    Pattern Recognition and Reconstruction on an FPGA Coprocessor Board. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:325-328 [Conf]
  49. Steven Derrien, Sanjay V. Rajopadhye
    FCCMS and the Memory Wall. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:329-330 [Conf]
  50. Kia Bazargan, Ryan Kastner, Seda Ogrenci, Majid Sarrafzadeh
    A C to Hardware/Software Compiler. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:331-332 [Conf]
  51. Markus Weinhardt, Wayne Luk
    Evaluating Hardware Compilation Techniques. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:333-334 [Conf]
  52. Philip James-Roxby, Brandon Blodget
    Adapting Constant Multipliers in a Neural Network Implementation. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:335-336 [Conf]
  53. Héctor Fabio Restrepo, Ralph Hoffmann, Andrés Pérez-Uribe, Christof Teuscher, Eduardo Sanchez
    A Networked FPGA-Based Hardware Implementation of a Neural Network Application. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:337-338 [Conf]
  54. Katsuharu Suzuki, Michael X. Wang, Zhao Fang, Wayne Wei-Ming Dai
    Design of C++ Class Library and Bit-Serial Compiler for Variable-Precision Datapath Synthesis on Adaptive Computing Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:339-340 [Conf]
  55. Timothy Courtney, Richard H. Turner, Roger Woods
    An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:341-343 [Conf]
  56. Arran Derbyshire, Wayne Luk
    Combining Serialization and Reconfiguration for Convolver Designs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:344-346 [Conf]
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002