Conferences in DBLP
Steve Young , Peter Alfke , Colm Fewer , Scott McMillan , Brandon Blodget , Delon Levi A High I/O Reconfigurable Crossbar Switch. [Citation Graph (0, 0)][DBLP ] Conf ] Heather A. Wake , Duncan A. Buell Congruential Sieves on a Reconfigurable Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Apostolos Dollas , Christopher Kachris , Nikolaos G. Bourbakis Performance Analysis of Fixed, Reconfigurable, and Custom Architectures for the SCAN Image and Video Encryption Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] James Moscola , John W. Lockwood , Ronald Prescott Loui , Michael Pachos Implementation of a Content-Scanning Module for an Internet Firewall. [Citation Graph (0, 0)][DBLP ] Conf ] T. K. Lee , Sherif Yusuf , Wayne Luk , Morris Sloman , Emil Lupu , Naranker Dulay Compiling Policy Descriptions into Reconfigurable Firewall Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Kuen Hung Tsoi , K. H. Leung , Philip Heng Wai Leong Compact FPGA-based True and Pseudo Random Number Generators. [Citation Graph (0, 0)][DBLP ] Conf ] Vinay Singh , Ann Root , E. Hemphill , Nabeel Shirazi , James Hwang Accelerating Bit Error Rate Testing Using a System Level Design Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Dong-U Lee , Wayne Luk , John D. Villasenor , Peter Y. K. Cheung A Hardware Gaussian Noise Generator for Channel Code Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] George A. Constantinides Perturbation Analysis for Word-length Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] B. R. Lee , Neil Burgess Improved Small Multiplier Based Multiplication, Squaring and Division. [Citation Graph (0, 0)][DBLP ] Conf ] Benjamin A. Levine , Herman Schmit Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth Eguro , Scott Hauck Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroto Kagotani , Herman Schmit Asynchronous PipeRench: Architecture and Performance Estimations. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Wirthlin , Eric Johnson , Nathan Rollins , Michael Caffrey , Paul Graham The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets. [Citation Graph (0, 0)][DBLP ] Conf ] Weifeng Xu , Ramshankar Ramanarayanan , Russell Tessier Adaptive Fault Recovery for Networked Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Janette Frigo , David Palmer , Maya Gokhale , Marc Popkin-Paine Gamma-Ray Pulsar Detection using Reconfigurable Computing Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Abdsamad Benkrid , Khaled Benkrid , Danny Crookes Design and Implementation of a Generic 2-D Orthogonal Discrete Wavelet Transform on FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Heather Quinn , Laurie A. Smith King , Miriam Leeser , Waleed Meleis Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Jian Liang , Russell Tessier , Oskar Mencer Floating Point Unit Generation and Evaluation for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaojun Wang , Brent E. Nelson Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Pedro C. Diniz , Joonseok Park Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Preston A. Jackson , Brad L. Hutchings , Justin L. Tripp Simulation and Synthesis of CSP-based Interprocess Communication. [Citation Graph (0, 0)][DBLP ] Conf ] K. Scott Hemmert , Justin L. Tripp , Brad L. Hutchings , Preston A. Jackson Source Level Debugger for the Sea Cucumber Synthesizing Compiler. [Citation Graph (0, 0)][DBLP ] Conf ] Jingzhao Ou , Seonil Choi , Viktor K. Prasanna Performance Modeling of Reconfigurable SoC Architectures and Energy-Efficient Mapping of a Class of Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Anthony L. Slade , Brent E. Nelson , Brad L. Hutchings Reconfigurable Computing Application Frameworks. [Citation Graph (0, 0)][DBLP ] Conf ] Prithviraj Banerjee , Debabrata Bagchi , Malay Haldar , Anshuman Nayak , Victor Kim , R. Uribe Automatic Conversion of Floating Point MATLAB Programs into Fixed Point FPGA Based Hardware Design. [Citation Graph (0, 0)][DBLP ] Conf ] Irwin Kennedy Fast Reconfiguration Through Difference Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Stanley Y. C. Li , Gap C. K. Cheuk , Kin-Hong Lee , Philip Heng Wai Leong FPGA-based SIMD Processor. [Citation Graph (0, 0)][DBLP ] Conf ] James P. Durbano , Fernando E. Ortiz , John R. Humphrey , Dennis W. Prather , Mark S. Mirotznik Implementation of Three-Dimensional FPGA-Based FDTD Solvers: An Architectural Overview. [Citation Graph (0, 0)][DBLP ] Conf ] Ciaran Toal , Sakir Sezer , Xing Yu A Pipelined SoPC Architecture for 2.5 Gbps Network Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Abdsamad Benkrid , Khaled Benkrid , Danny Crookes A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Andrey Filippov Recon .gurable High Resolution Network Camera. [Citation Graph (0, 0)][DBLP ] Conf ] Javier Resano , Diederik Verkest , Daniel Mozos , Serge Vernalde , Francky Catthoor Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] S. Belkacemi , Khaled Benkrid , Danny Crookes A Logic Based Hardware Development Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Lesley Shannon , Paul Chow Standardizing the Performance Assessment of Reconfigurable Processor Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Alex K. Jones , Prithviraj Banerjee An Automated and Power-Aware Framework for Utilization of IP Cores in Hardware Generated from C Descriptions Targeting FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Ranjesh G. Jaganathan , Keith D. Underwood , Ron R. Sass A Configurable Network Protocol for Cluster Based Communications using Modular Hardware Primitives on an Intelligent NIC. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Wolinski , Maya Gokhale , Kevin McCabe Fabric-Based Systems: Model, Tools, Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Sumit Mohanty , Jingzhao Ou , Viktor K. Prasanna An Estimation and Simulation Framework for Energy Efficient Design using Platform FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Shaomeng Li , Jim Torresen , Oddvar Søråsen Exploiting Reconfigurable Hardware for Network Security. [Citation Graph (0, 0)][DBLP ] Conf ] Kyprianos Papademetriou , Apostolos Dollas , Stamatios Sotiropoulos A Second Generation Embedded Reconfigurable Input Device for Kinetically Challenged Persons. [Citation Graph (0, 0)][DBLP ] Conf ] K. R. Shesha Shayee , Joonseok Park , Pedro C. Diniz Performance and Area Modeling of Complete FPGA Designs in the presence of Loop Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Joonseok Park , Pedro C. Diniz Synthesis and Estimation of Memory Interfaces for FPGA-based Reconfigurable Computing Engines. [Citation Graph (0, 0)][DBLP ] Conf ] Vamsi Krishna Marreddy , Sharareh Noorbaloochi , Kia Bazargan Linear Placement for Static / Dynamic Reconfiguration in JBits. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Todman , Wayne Luk Real-time Extensions to a C-like Hardware Description Language. [Citation Graph (0, 0)][DBLP ] Conf ] Kiran Puttegowda , Peter Athanas RSA encryption using Extended Modular Arithmetic on the Quicksilver COSM Adaptive Computing Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Callahan Kernel Formation in Garpcc. [Citation Graph (0, 0)][DBLP ] Conf ] 