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Conferences in DBLP

Field-Programmable Custom Computing Machines (FCCM) (fccm)
2003 (conf/fccm/2003)

  1. Steve Young, Peter Alfke, Colm Fewer, Scott McMillan, Brandon Blodget, Delon Levi
    A High I/O Reconfigurable Crossbar Switch. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:3-10 [Conf]
  2. Heather A. Wake, Duncan A. Buell
    Congruential Sieves on a Reconfigurable Computer. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:11-18 [Conf]
  3. Apostolos Dollas, Christopher Kachris, Nikolaos G. Bourbakis
    Performance Analysis of Fixed, Reconfigurable, and Custom Architectures for the SCAN Image and Video Encryption Algorithm. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:19-0 [Conf]
  4. James Moscola, John W. Lockwood, Ronald Prescott Loui, Michael Pachos
    Implementation of a Content-Scanning Module for an Internet Firewall. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:31-38 [Conf]
  5. T. K. Lee, Sherif Yusuf, Wayne Luk, Morris Sloman, Emil Lupu, Naranker Dulay
    Compiling Policy Descriptions into Reconfigurable Firewall Processors. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:39-0 [Conf]
  6. Kuen Hung Tsoi, K. H. Leung, Philip Heng Wai Leong
    Compact FPGA-based True and Pseudo Random Number Generators. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:51-61 [Conf]
  7. Vinay Singh, Ann Root, E. Hemphill, Nabeel Shirazi, James Hwang
    Accelerating Bit Error Rate Testing Using a System Level Design Tool. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:62-68 [Conf]
  8. Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
    A Hardware Gaussian Noise Generator for Channel Code Evaluation. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:69-0 [Conf]
  9. George A. Constantinides
    Perturbation Analysis for Word-length Optimization. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:81-90 [Conf]
  10. B. R. Lee, Neil Burgess
    Improved Small Multiplier Based Multiplication, Squaring and Division. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:91-0 [Conf]
  11. Benjamin A. Levine, Herman Schmit
    Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:101-110 [Conf]
  12. Kenneth Eguro, Scott Hauck
    Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:111-120 [Conf]
  13. Hiroto Kagotani, Herman Schmit
    Asynchronous PipeRench: Architecture and Performance Estimations. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:121-0 [Conf]
  14. Michael J. Wirthlin, Eric Johnson, Nathan Rollins, Michael Caffrey, Paul Graham
    The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:133-142 [Conf]
  15. Weifeng Xu, Ramshankar Ramanarayanan, Russell Tessier
    Adaptive Fault Recovery for Networked Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:143-0 [Conf]
  16. Janette Frigo, David Palmer, Maya Gokhale, Marc Popkin-Paine
    Gamma-Ray Pulsar Detection using Reconfigurable Computing Hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:155-161 [Conf]
  17. Abdsamad Benkrid, Khaled Benkrid, Danny Crookes
    Design and Implementation of a Generic 2-D Orthogonal Discrete Wavelet Transform on FPGA. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:162-172 [Conf]
  18. Heather Quinn, Laurie A. Smith King, Miriam Leeser, Waleed Meleis
    Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:173-0 [Conf]
  19. Jian Liang, Russell Tessier, Oskar Mencer
    Floating Point Unit Generation and Evaluation for FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:185-194 [Conf]
  20. Xiaojun Wang, Brent E. Nelson
    Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:195-0 [Conf]
  21. Pedro C. Diniz, Joonseok Park
    Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:207-217 [Conf]
  22. Preston A. Jackson, Brad L. Hutchings, Justin L. Tripp
    Simulation and Synthesis of CSP-based Interprocess Communication. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:218-227 [Conf]
  23. K. Scott Hemmert, Justin L. Tripp, Brad L. Hutchings, Preston A. Jackson
    Source Level Debugger for the Sea Cucumber Synthesizing Compiler. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:228-0 [Conf]
  24. Jingzhao Ou, Seonil Choi, Viktor K. Prasanna
    Performance Modeling of Reconfigurable SoC Architectures and Energy-Efficient Mapping of a Class of Applications. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:241-250 [Conf]
  25. Anthony L. Slade, Brent E. Nelson, Brad L. Hutchings
    Reconfigurable Computing Application Frameworks. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:251-0 [Conf]
  26. Prithviraj Banerjee, Debabrata Bagchi, Malay Haldar, Anshuman Nayak, Victor Kim, R. Uribe
    Automatic Conversion of Floating Point MATLAB Programs into Fixed Point FPGA Based Hardware Design. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:263-264 [Conf]
  27. Irwin Kennedy
    Fast Reconfiguration Through Difference Compression. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:265-266 [Conf]
  28. Stanley Y. C. Li, Gap C. K. Cheuk, Kin-Hong Lee, Philip Heng Wai Leong
    FPGA-based SIMD Processor. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:267-268 [Conf]
  29. James P. Durbano, Fernando E. Ortiz, John R. Humphrey, Dennis W. Prather, Mark S. Mirotznik
    Implementation of Three-Dimensional FPGA-Based FDTD Solvers: An Architectural Overview. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:269-270 [Conf]
  30. Ciaran Toal, Sakir Sezer, Xing Yu
    A Pipelined SoPC Architecture for 2.5 Gbps Network Processing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:271-272 [Conf]
  31. Abdsamad Benkrid, Khaled Benkrid, Danny Crookes
    A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:273-275 [Conf]
  32. Andrey Filippov
    Recon .gurable High Resolution Network Camera. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:276-277 [Conf]
  33. Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor
    Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:278-279 [Conf]
  34. S. Belkacemi, Khaled Benkrid, Danny Crookes
    A Logic Based Hardware Development Environment. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:280-281 [Conf]
  35. Lesley Shannon, Paul Chow
    Standardizing the Performance Assessment of Reconfigurable Processor Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:282-283 [Conf]
  36. Alex K. Jones, Prithviraj Banerjee
    An Automated and Power-Aware Framework for Utilization of IP Cores in Hardware Generated from C Descriptions Targeting FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:284-285 [Conf]
  37. Ranjesh G. Jaganathan, Keith D. Underwood, Ron R. Sass
    A Configurable Network Protocol for Cluster Based Communications using Modular Hardware Primitives on an Intelligent NIC. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:286-287 [Conf]
  38. Christophe Wolinski, Maya Gokhale, Kevin McCabe
    Fabric-Based Systems: Model, Tools, Applications. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:288-289 [Conf]
  39. Sumit Mohanty, Jingzhao Ou, Viktor K. Prasanna
    An Estimation and Simulation Framework for Energy Efficient Design using Platform FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:290-291 [Conf]
  40. Shaomeng Li, Jim Torresen, Oddvar Søråsen
    Exploiting Reconfigurable Hardware for Network Security. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:292-293 [Conf]
  41. Kyprianos Papademetriou, Apostolos Dollas, Stamatios Sotiropoulos
    A Second Generation Embedded Reconfigurable Input Device for Kinetically Challenged Persons. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:294-295 [Conf]
  42. K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz
    Performance and Area Modeling of Complete FPGA Designs in the presence of Loop Transformations. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:296- [Conf]
  43. Joonseok Park, Pedro C. Diniz
    Synthesis and Estimation of Memory Interfaces for FPGA-based Reconfigurable Computing Engines. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:297-299 [Conf]
  44. Vamsi Krishna Marreddy, Sharareh Noorbaloochi, Kia Bazargan
    Linear Placement for Static / Dynamic Reconfiguration in JBits. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:300-301 [Conf]
  45. Tim Todman, Wayne Luk
    Real-time Extensions to a C-like Hardware Description Language. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:302-304 [Conf]
  46. Kiran Puttegowda, Peter Athanas
    RSA encryption using Extended Modular Arithmetic on the Quicksilver COSM Adaptive Computing Machine. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:305-307 [Conf]
  47. Tim Callahan
    Kernel Formation in Garpcc. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:308-0 [Conf]
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