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Conferences in DBLP

Field-Programmable Custom Computing Machines (FCCM) (fccm)
2006 (conf/fccm/2006)

  1. Gerald R. Morris, Viktor K. Prasanna, Richard D. Anderson
    A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:3-12 [Conf]
  2. Volodymyr V. Kindratenko, David Pointer
    A case study in porting a production scientific supercomputing application to a reconfigurable computer. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:13-22 [Conf]
  3. Ronald Scrofano, Maya Gokhale, Frans Trouw, Viktor K. Prasanna
    Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:23-34 [Conf]
  4. Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, S. Lopez-Buedo
    Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:35-44 [Conf]
  5. David J. Lau, Orion Pritchard, Philippe Molson
    Automated Generation of Hardware Accelerators with Direct Memory Access from ANSI/ISO Standard C Functions. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:45-56 [Conf]
  6. David B. Thomas, Wayne Luk
    Efficient Hardware Generation of Random Variates with Arbitrary Distributions. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:57-66 [Conf]
  7. Zachary K. Baker, Viktor K. Prasanna
    An Architecture for Efficient Hardware Data Mining using Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:67-75 [Conf]
  8. Haiqian Yu, Miriam Leeser
    Automatic Sliding Window Operation Optimization for FPGA-Based. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:76-88 [Conf]
  9. Erik Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp, Ron Sass, David L. Andrews
    Enabling a Uniform Programming Model Across the Software/Hardware Boundary. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:89-98 [Conf]
  10. Benjamin Ylvisaker, Brian Van Essen, Carl Ebeling
    A Type Architecture for Hybrid Micro-Parallel Computers. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:99-110 [Conf]
  11. Arun Patel, Christopher A. Madill, Manuel Saldaña, Chris Comis, Regis Pomes, Paul Chow
    A Scalable FPGA-based Multiprocessor. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:111-120 [Conf]
  12. Charles L. Cathey, Jason D. Bakos, Duncan A. Buell
    A Reconfigurable Distributed Computing Fabric Exploiting Multilevel Parallelism. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:121-130 [Conf]
  13. Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown
    A Multithreaded Soft Processor for SoPC Area Reduction. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:131-142 [Conf]
  14. Michael DeLorimier, Nachiket Kapre, Nikil Mehta, Dominic Rizzo, Ian Eslick, Raphael Rubin, Tomas E. Uribe, Thomas F. Knight Jr., André DeHon
    GraphStep: A System Architecture for Sparse-Graph Algorithms. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:143-151 [Conf]
  15. Uday Bondhugula, Ananth Devulapalli, James Dinan, Joseph Fernando, Pete Wyckoff, Eric Stahlberg, P. Sadayappan
    Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:152-164 [Conf]
  16. Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle
    A Field Programmable RFID Tag and Associated Design Flow. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:165-174 [Conf]
  17. Robert G. Dimond, Oskar Mencer, Wayne Luk
    Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:175-184 [Conf]
  18. Matthew French, Li Wang, Michael J. Wirthlin
    Power Visualization, Analysis, and Optimization Tools for FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:185-194 [Conf]
  19. Michael Attig, Gordon J. Brebner
    Systematic Characterization of Programmable Packet Processing Pipelines. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:195-204 [Conf]
  20. Nachiket Kapre, Nikil Mehta, Michael DeLorimier, Raphael Rubin, Henry Barnor, Michael J. Wilson, Michael G. Wrighton, André DeHon
    Packet Switched vs. Time Multiplexed FPGA Overlay Networks. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:205-216 [Conf]
  21. Martin C. Herbordt, Josh Model, Yongfeng Gu, Bharat Sukhwani, Tom Van Court
    Single Pass, BLAST-Like, Approximate String Matching on FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:217-226 [Conf]
  22. Kevin Whitton, Xiaobo Sharon Hu, Cedric X. Yu, Danny Z. Chen
    An FPGA Solution for Radiation Dose Calculation. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:227-236 [Conf]
  23. Andrey Bogdanov, M. C. Mertens
    A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2). [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:237-248 [Conf]
  24. Xiaojun Wang, Sherman Braganza, Miriam Leeser
    Advanced Components in the Variable Precision Floating-Point Library. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:249-258 [Conf]
  25. Robert Strzodka, Dominik Goddeke
    Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision Components. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:259-270 [Conf]
  26. Evgeny Fiksman, Yitzhak Birk, Oskar Mencer
    ASC-Based Acceleration in an FPGA with a Processor Core Using Software-Only Skills. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:271-272 [Conf]
  27. Shannon Koh, Oliver Diessel
    COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:273-274 [Conf]
  28. Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
    A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:275-276 [Conf]
  29. Gang Wang, Wenrui Gong, Ryan Kastner
    Defect-Tolerant Nanocomputing Using Bloom Filters. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:277-278 [Conf]
  30. Reid B. Porter, Jan R. Frigo, Maya Gokhale, Christophe Wolinski, François Charot, Charles Wagner
    A Programmable, Maximal Throughput Architecture for Neighborhood Image Processing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:279-280 [Conf]
  31. Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann, John A. Williams
    VPN Acceleration Using Reconfigurable System-On-Chip Technology. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:281-282 [Conf]
  32. Chuan He, Guan Qin, Mi Lu, Wei Zhao
    An Optimized Finite Difference Computing Engine on FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:283-284 [Conf]
  33. Toshihiro Katashita, Atusi Maeda, Kenji Toda, Yoshinori Yamaguchi
    Highly Efficient String Matching Circuit for IDS with FPGA. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:285-286 [Conf]
  34. Rafael A. Arce-Nazario, Manuel Jimenez, Domingo Rodriguez
    Effects of High-Level Discrete Signal Transform Formulations on Partitioning for Multi-FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:287-288 [Conf]
  35. K. N. Vikram, V. Vasudevan
    Scheduling divisible loads on partially reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:289-290 [Conf]
  36. Tatsuhiro Tachibana, Yoshihiro Murata, Naoki Shibata, Keiichi Yasumoto, Minoru Ito
    General Architecture for Hardware Implementation of Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:291-292 [Conf]
  37. Yousef El-Kurdi, Warren J. Gross, Dennis Giannacopoulos
    Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:293-294 [Conf]
  38. Arpith C. Jacob, Brandon Harris, Jeremy Buhler, Roger D. Chamberlain, Young H. Cho
    Scalable Softcore Vector Processor for Biosequence Applications. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:295-296 [Conf]
  39. Oliver Pell, Wayne Luk
    Generating Parametrised Hardware Libraries from Higher-Order Descriptions. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:297-298 [Conf]
  40. Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones
    Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:299-300 [Conf]
  41. Gerhard Lienhart, Guillermo Marcus Martinez, Andreas Kugel, Reinhard Männer
    Rapid Design of Special-Purpose Pipeline Processors with FPGAs and its Application to Computational Fluid Dynamics. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:301-302 [Conf]
  42. Michael R. Bodnar, John R. Humphrey, Petersen F. Curt, James P. Durbano, Dennis W. Prather
    Floating-Point Accumulation Circuit for Matrix Applications. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:303-304 [Conf]
  43. Tom Van Court, Martin C. Herbordt
    Application-Specific Memory Interleaving Enables High Performance in FPGA-based Grid Computations. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:305-306 [Conf]
  44. Kyprianos Papademetriou, Apostolos Dollas
    A Task Graph Approach for Efficient Exploitation of Reconfiguration in Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:307-308 [Conf]
  45. Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones
    A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:309-310 [Conf]
  46. Sandeep Kumar, Christof Paar, Jan Pelzl, Gerd Pfeiffer, Manfred Schimmler
    COPACOBANA A Cost-Optimized Special-Purpose Hardware for Code-Breaking. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:311-312 [Conf]
  47. Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckmann
    FPGAs, GPUs and the PS2 - A Single Programming Methodology. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:313-314 [Conf]
  48. Yongfeng Gu, Tom Van Court, Martin C. Herbordt
    Integrating FPGA Acceleration into the Protomol Molecular Dynamics Code: Preliminary Report. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:315-316 [Conf]
  49. Charlie Ross, A. P. Wim Böhm
    A Co-Verification Tool for a High Level Language Compiler for FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:317-318 [Conf]
  50. Dionissios Efstathiou, Konstantinos Kazakos, Apostolos Dollas
    Parrotfish: Task Distribution in a Low Cost Autonomous ad hoc Sensor Network through Dynamic Runtime Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:319-320 [Conf]
  51. John Maher, Brian McGinley, Patrick Rocke, Fearghal Morgan
    Intrinsic Hardware Evolution of Neural Networks in Reconfigurable Analogue and Digital Devices. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:321-322 [Conf]
  52. Heather Quinn, Debayan Bhaduri, Christof Teuscher, Paul Graham, Maya Gokhale
    The STAR-C Truth: Analyzing Reconfigurable Supercomputing Reliability. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:323-324 [Conf]
  53. Somsubhra Mondal, Seda Ogrenci Memik, Nikolaos Bellas
    Pre-synthesis Queue Size Estimation of Streaming Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:325-326 [Conf]
  54. Shobana Padmanabhan, Moshe Looks, Dan Legorreta, Young Cho, John W. Lockwood
    Hierarchical Clustering using Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:327-328 [Conf]
  55. S. Dai, E. Bozorgzadeh
    CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:329-330 [Conf]
  56. Allen Michalski, Duncan A. Buell
    A Scalable Architecture for RSA Cryptography on Large FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:331-332 [Conf]
  57. Kendall Ananyi, Daler N. Rakhmatov
    Design of a Reconfigurable Processor for NIST Prime Field ECC. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:333-334 [Conf]
  58. Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arif Rahman
    Switch Box Architectures for Three-Dimensional FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:335-336 [Conf]
  59. James Moscola, Young H. Cho, John W. Lockwood
    A Scalable Hybrid Regular Expression Pattern Matcher. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:337-338 [Conf]
  60. Cao Liang, Jing Ma, Xin-Ming Huang
    Hardware/Software Co-Design Architecture for Lattice Decoding Algorithms. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:339-340 [Conf]
  61. Jia Ming Mar, Alessandro Bissacco, Stefano Soatto, Soheil Ghiasi
    High Performance Feature Detection on a Reconfigurable Co-Processor. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:341-342 [Conf]
  62. Michael J. Wirthlin, Welson Sun
    DSynth: A Pipeline Synthesis Environment for FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:343-344 [Conf]
  63. Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier
    Template-Based Generation of Streaming Accelators from a High Level Presentation. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:345-346 [Conf]
  64. Brad Matthews, Itamar Elhanany
    Scalable Hardware Architecture for Real-Time Dynamic Programming Applications. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:347-348 [Conf]
  65. K. Scott Hemmert, Keith D. Underwood
    Open Source High Performance Floating-Point Modules. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:349-350 [Conf]
  66. John A. Williams, I. Syed, J. Wu, Neil W. Bergmann
    A Reconfigurable Cluster-on-Chip Architecture with MPI Communication Layer. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:351-352 [Conf]
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002