Conferences in DBLP
Gerald R. Morris , Viktor K. Prasanna , Richard D. Anderson A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer. [Citation Graph (0, 0)][DBLP ] Conf ] Volodymyr V. Kindratenko , David Pointer A case study in porting a production scientific supercomputing application to a reconfigurable computer. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald Scrofano , Maya Gokhale , Frans Trouw , Viktor K. Prasanna Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Chun Hok Ho , Philip Heng Wai Leong , Wayne Luk , Steven J. E. Wilton , S. Lopez-Buedo Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] David J. Lau , Orion Pritchard , Philippe Molson Automated Generation of Hardware Accelerators with Direct Memory Access from ANSI/ISO Standard C Functions. [Citation Graph (0, 0)][DBLP ] Conf ] David B. Thomas , Wayne Luk Efficient Hardware Generation of Random Variates with Arbitrary Distributions. [Citation Graph (0, 0)][DBLP ] Conf ] Zachary K. Baker , Viktor K. Prasanna An Architecture for Efficient Hardware Data Mining using Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Haiqian Yu , Miriam Leeser Automatic Sliding Window Operation Optimization for FPGA-Based. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Anderson , Jason Agron , Wesley Peck , Jim Stevens , Fabrice Baijot , Ed Komp , Ron Sass , David L. Andrews Enabling a Uniform Programming Model Across the Software/Hardware Boundary. [Citation Graph (0, 0)][DBLP ] Conf ] Benjamin Ylvisaker , Brian Van Essen , Carl Ebeling A Type Architecture for Hybrid Micro-Parallel Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Arun Patel , Christopher A. Madill , Manuel Saldaña , Chris Comis , Regis Pomes , Paul Chow A Scalable FPGA-based Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Charles L. Cathey , Jason D. Bakos , Duncan A. Buell A Reconfigurable Distributed Computing Fabric Exploiting Multilevel Parallelism. [Citation Graph (0, 0)][DBLP ] Conf ] Blair Fort , Davor Capalija , Zvonko G. Vranesic , Stephen Dean Brown A Multithreaded Soft Processor for SoPC Area Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Michael DeLorimier , Nachiket Kapre , Nikil Mehta , Dominic Rizzo , Ian Eslick , Raphael Rubin , Tomas E. Uribe , Thomas F. Knight Jr. , André DeHon GraphStep: A System Architecture for Sparse-Graph Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Uday Bondhugula , Ananth Devulapalli , James Dinan , Joseph Fernando , Pete Wyckoff , Eric Stahlberg , P. Sadayappan Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Alex K. Jones , Raymond R. Hoare , Swapna R. Dontharaju , Shen Chih Tung , Ralph Sprang , Joshua Fazekas , James T. Cain , Marlin H. Mickle A Field Programmable RFID Tag and Associated Design Flow. [Citation Graph (0, 0)][DBLP ] Conf ] Robert G. Dimond , Oskar Mencer , Wayne Luk Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew French , Li Wang , Michael J. Wirthlin Power Visualization, Analysis, and Optimization Tools for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Attig , Gordon J. Brebner Systematic Characterization of Programmable Packet Processing Pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Nachiket Kapre , Nikil Mehta , Michael DeLorimier , Raphael Rubin , Henry Barnor , Michael J. Wilson , Michael G. Wrighton , André DeHon Packet Switched vs. Time Multiplexed FPGA Overlay Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Martin C. Herbordt , Josh Model , Yongfeng Gu , Bharat Sukhwani , Tom Van Court Single Pass, BLAST-Like, Approximate String Matching on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin Whitton , Xiaobo Sharon Hu , Cedric X. Yu , Danny Z. Chen An FPGA Solution for Radiation Dose Calculation. [Citation Graph (0, 0)][DBLP ] Conf ] Andrey Bogdanov , M. C. Mertens A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2). [Citation Graph (0, 0)][DBLP ] Conf ] Xiaojun Wang , Sherman Braganza , Miriam Leeser Advanced Components in the Variable Precision Floating-Point Library. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Strzodka , Dominik Goddeke Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision Components. [Citation Graph (0, 0)][DBLP ] Conf ] Evgeny Fiksman , Yitzhak Birk , Oskar Mencer ASC-Based Acceleration in an FPGA with a Processor Core Using Software-Only Skills. [Citation Graph (0, 0)][DBLP ] Conf ] Shannon Koh , Oliver Diessel COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Alastair M. Smith , George A. Constantinides , Peter Y. K. Cheung A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Wang , Wenrui Gong , Ryan Kastner Defect-Tolerant Nanocomputing Using Bloom Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Reid B. Porter , Jan R. Frigo , Maya Gokhale , Christophe Wolinski , François Charot , Charles Wagner A Programmable, Maximal Throughput Architecture for Neighborhood Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Chin Mun Wee , Peter R. Sutton , Neil W. Bergmann , John A. Williams VPN Acceleration Using Reconfigurable System-On-Chip Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Chuan He , Guan Qin , Mi Lu , Wei Zhao An Optimized Finite Difference Computing Engine on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Toshihiro Katashita , Atusi Maeda , Kenji Toda , Yoshinori Yamaguchi Highly Efficient String Matching Circuit for IDS with FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Rafael A. Arce-Nazario , Manuel Jimenez , Domingo Rodriguez Effects of High-Level Discrete Signal Transform Formulations on Partitioning for Multi-FPGA Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] K. N. Vikram , V. Vasudevan Scheduling divisible loads on partially reconfigurable hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Tatsuhiro Tachibana , Yoshihiro Murata , Naoki Shibata , Keiichi Yasumoto , Minoru Ito General Architecture for Hardware Implementation of Genetic Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Yousef El-Kurdi , Warren J. Gross , Dennis Giannacopoulos Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Arpith C. Jacob , Brandon Harris , Jeremy Buhler , Roger D. Chamberlain , Young H. Cho Scalable Softcore Vector Processor for Biosequence Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver Pell , Wayne Luk Generating Parametrised Hardware Libraries from Higher-Order Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Raymond R. Hoare , Ivan S. Kourtev , Alex K. Jones Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). [Citation Graph (0, 0)][DBLP ] Conf ] Gerhard Lienhart , Guillermo Marcus Martinez , Andreas Kugel , Reinhard Männer Rapid Design of Special-Purpose Pipeline Processors with FPGAs and its Application to Computational Fluid Dynamics. [Citation Graph (0, 0)][DBLP ] Conf ] Michael R. Bodnar , John R. Humphrey , Petersen F. Curt , James P. Durbano , Dennis W. Prather Floating-Point Accumulation Circuit for Matrix Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Van Court , Martin C. Herbordt Application-Specific Memory Interleaving Enables High Performance in FPGA-based Grid Computations. [Citation Graph (0, 0)][DBLP ] Conf ] Kyprianos Papademetriou , Apostolos Dollas A Task Graph Approach for Efficient Exploitation of Reconfiguration in Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Gayatri Mehta , Raymond R. Hoare , Justin Stander , Alex K. Jones A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep Kumar , Christof Paar , Jan Pelzl , Gerd Pfeiffer , Manfred Schimmler COPACOBANA A Cost-Optimized Special-Purpose Hardware for Code-Breaking. [Citation Graph (0, 0)][DBLP ] Conf ] Lee W. Howes , Paul Price , Oskar Mencer , Olav Beckmann FPGAs, GPUs and the PS2 - A Single Programming Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Yongfeng Gu , Tom Van Court , Martin C. Herbordt Integrating FPGA Acceleration into the Protomol Molecular Dynamics Code: Preliminary Report. [Citation Graph (0, 0)][DBLP ] Conf ] Charlie Ross , A. P. Wim Böhm A Co-Verification Tool for a High Level Language Compiler for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Dionissios Efstathiou , Konstantinos Kazakos , Apostolos Dollas Parrotfish: Task Distribution in a Low Cost Autonomous ad hoc Sensor Network through Dynamic Runtime Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] John Maher , Brian McGinley , Patrick Rocke , Fearghal Morgan Intrinsic Hardware Evolution of Neural Networks in Reconfigurable Analogue and Digital Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Heather Quinn , Debayan Bhaduri , Christof Teuscher , Paul Graham , Maya Gokhale The STAR-C Truth: Analyzing Reconfigurable Supercomputing Reliability. [Citation Graph (0, 0)][DBLP ] Conf ] Somsubhra Mondal , Seda Ogrenci Memik , Nikolaos Bellas Pre-synthesis Queue Size Estimation of Streaming Data Flow Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Shobana Padmanabhan , Moshe Looks , Dan Legorreta , Young Cho , John W. Lockwood Hierarchical Clustering using Reconfigurable Devices. [Citation Graph (0, 0)][DBLP ] Conf ] S. Dai , E. Bozorgzadeh CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Allen Michalski , Duncan A. Buell A Scalable Architecture for RSA Cryptography on Large FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Kendall Ananyi , Daler N. Rakhmatov Design of a Reconfigurable Processor for NIST Prime Field ECC. [Citation Graph (0, 0)][DBLP ] Conf ] Aman Gayasen , Narayanan Vijaykrishnan , Mahmut T. Kandemir , Arif Rahman Switch Box Architectures for Three-Dimensional FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] James Moscola , Young H. Cho , John W. Lockwood A Scalable Hybrid Regular Expression Pattern Matcher. [Citation Graph (0, 0)][DBLP ] Conf ] Cao Liang , Jing Ma , Xin-Ming Huang Hardware/Software Co-Design Architecture for Lattice Decoding Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Jia Ming Mar , Alessandro Bissacco , Stefano Soatto , Soheil Ghiasi High Performance Feature Detection on a Reconfigurable Co-Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Wirthlin , Welson Sun DSynth: A Pipeline Synthesis Environment for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaos Bellas , Sek M. Chai , Malcolm Dwyer , Dan Linzmeier Template-Based Generation of Streaming Accelators from a High Level Presentation. [Citation Graph (0, 0)][DBLP ] Conf ] Brad Matthews , Itamar Elhanany Scalable Hardware Architecture for Real-Time Dynamic Programming Applications. [Citation Graph (0, 0)][DBLP ] Conf ] K. Scott Hemmert , Keith D. Underwood Open Source High Performance Floating-Point Modules. [Citation Graph (0, 0)][DBLP ] Conf ] John A. Williams , I. Syed , J. Wu , Neil W. Bergmann A Reconfigurable Cluster-on-Chip Architecture with MPI Communication Layer. [Citation Graph (0, 0)][DBLP ] Conf ] 