Conferences in DBLP
C. A. R. Hoare How Did Software Get So Reliable Without Proof? [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:1-17 [Conf ] Terje Sivertsen A Case Study on the Formal Development of a Reactor Safety System. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:18-38 [Conf ] Jan Peleska Test Automation for Safety-Critical Systems: Industrial Application and Future Developments. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:39-59 [Conf ] Juan Bicarregui , Jeremy Dick , Eoin Woods Quantitative Analysis of an Application of Formal Methods. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:60-73 [Conf ] Jonathan Hoare , Jeremy Dick , David Neilson , Ib Holm Sørensen Applying the B Technologies on CICS. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:74-84 [Conf ] Marina A. Waldén , Kaisa Sere Refining Action Systems within B-Tool. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:85-104 [Conf ] V. Kasurinen , Kaisa Sere Integrating Action Systems and Z in a Medical System Specification. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:105-119 [Conf ] Rix Groenboom , Erik Saaman , Ernest Rotterdam , Gerard R. Renardel de Lavalette Formalizing Anaesthesia: a case study in formal specification. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:120-139 [Conf ] Juan-José Martins , Jean-Pierre Hubaux A New System Engineering Methodology Coupling Formal Specification and Performance Evaluation. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:140-159 [Conf ] Ben L. Di Vito Formalizing New Navigation Requirements for NASA's Space Shuttle. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:160-178 [Conf ] Brigitte Fröhlich , Peter Gorm Larsen Combining VDM-SL Specifications with C++ Code. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:179-194 [Conf ] Tim Clement Data Reification without Explicit Abstraction Functions. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:195-213 [Conf ] T. M. Brookes , John S. Fitzgerald , Peter Gorm Larsen Formal and Informal Specifications of a Secure System Component: Final Results in a Comparative Study. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:214-227 [Conf ] Antti Valmari , Manu Setälä Visual Verification of Safety and Liveness. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:228-247 [Conf ] Bernhard Schätz , Heinrich Hußmann , Manfred Broy Graphical Development of Consistent System Specifications. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:248-267 [Conf ] Dieter Hutter , Bruno Langenstein , Claus Sengler , Jörg H. Siekmann , Werner Stephan , Andreas Wolpers Deduction in the Verification Support Environment (VSE). [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:268-286 [Conf ] Eerke A. Boiten , John Derrick , Howard Bowman , Maarten Steen Consistency and Refinement for Partial Specification in Z. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:287-306 [Conf ] Matthias Weber Combining Statecharts and Z for the Design of Safety-Critical Control Systems. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:307-326 [Conf ] Colin J. Fidge , Mark Utting , Peter Kearney , Ian J. Hayes Integrating Real-Time Scheduling Theory and Program Refinement. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:327-346 [Conf ] Christel Seguin , Virginie Wiels Using a Logical and Categorical Approach for the Validation of Fault-Tolerant Systems. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:347-366 [Conf ] Frank S. de Boer , M. van Hulst Local Nondeterminism in Asynchronously Communicating Processes. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:367-384 [Conf ] Patrice Chalin , Peter Grogono , Thiruvengadam Radhakrishnan Identification of and Solutions to Shortcomings of LCL, a Larch/C Interface Specification Language. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:385-404 [Conf ] Balakrishnan Kannikeswaran , Radharamanan Radhakrishnan , Peter Frey , Perry Alexander , Philip A. Wilsey Formal Specification and Verification of the pGVT Algorithm. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:405-424 [Conf ] Rosario Pugliese , Enrico Tronci Automatic Verification of a Hydroelectric Power Plant. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:425-444 [Conf ] David M. Jackson Experiences in Embedded Scheduling. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:445-464 [Conf ] Bernard Boigelot , Patrice Godefroid Model Checking in Practice: An Analysis of the ACCESS.bus Protocol using SPIN. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:465-478 [Conf ] Stephan Kleuker , Hermann Tjabben The Incremental Development of Correct Specifications for Distributed Systems. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:479-498 [Conf ] Chris George A Theory of Distributing Train Rescheduling. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:499-517 [Conf ] Lihua Shi , Paddy Nixon An Improved Translation of SA/RT Specification Model to High-Level Timed Petri Nets. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:518-537 [Conf ] Jan Peleska , Michael Siegel From Testing Theory to Test Driver Implementation. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:538-556 [Conf ] Joseph J. Comuzzi , Johnson M. Hart Program Slicing Using Weakest Preconditions. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:557-575 [Conf ] Paulo S. C. Alencar , Donald D. Cowan , Carlos José Pereira de Lucena A Formal Approach to Architectural Design Patterns. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:576-594 [Conf ] Job Zwiers , Ulrich Hannemann , Yassine Lakhnech , Willem P. de Roever , Frank A. Stomp Modular Completeness: Integrating the Reuse of Specified Software in Top-down Program Development. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:595-608 [Conf ] Jürgen Bohn , Wil Janssen A Strategic Approach to Transformational Design. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:609-628 [Conf ] Kolyang , Thomas Santen , Burkhart Wolff Correct and User-Friendly Implementations of Transformation Systems. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:629-648 [Conf ] André Arnold , Didier Bégay , Jean-Pierre Radoux An Example of Use of Formal Methods to Debug an Embedded Software. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:649-661 [Conf ] Klaus Havelund , Natarajan Shankar Experiments in Theorem Proving and Model Checking for Protocol Verification. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:662-681 [Conf ] Farn Wang , Chia-Tien Dan Lo Procedure-Level Verification of Real-time Concurrent Systems. [Citation Graph (0, 0)][DBLP ] FME, 1996, pp:682-701 [Conf ]