Conferences in DBLP
Kurt Keutzer The Need for Formal Methods for Integrated Circuit Design. [Citation Graph (0, 0)][DBLP ] Conf ] Yirng-An Chen , Edmund M. Clarke , Pei-Hsin Ho , Yatin Vasant Hoskote , Timothy Kam , Manpreet Khaira , John W. O'Leary , Xudong Zhao Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Laurent Arditi BMDs Can Delay the Use of Theorem Proving for Verifying Arithmetic Assembly Instructions. [Citation Graph (0, 0)][DBLP ] Conf ] Kavita Ravi , Abelardo Pardo , Gary D. Hachtel , Fabio Somenzi Modular Verification of Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Paul S. Miner , James F. Leathrum Verification of IEEE Compliant Subtractive Division Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Harald Rueß Hierarchical Verification of Two-Dimensional High-Speed Multiplication in PVS: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco J. Cantu , Alan Bundy , Alan Smaill , David A. Basin Experiments in Automating Hardware Verification Using Inductive Proof Planning. [Citation Graph (0, 0)][DBLP ] Conf ] Alok Jain , Kyle L. Nelson , Randal E. Bryant Verifying Nondeterministic Implementations of Deterministic Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Lewin , Dean H. Lorenz , Shmuel Ur A Methodology for Processor Implementation Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Geist , Monica Farkas , Avner Landver , Yossi Lichtenstein , Shmuel Ur , Yaron Wolfsthal Coverage-Directed Test Generation Using Symbolic Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Robert B. Jones , Carl-Johan H. Seger , David L. Dill Self-Consistency Checking. [Citation Graph (0, 0)][DBLP ] Conf ] David Cyrluk Inverting the Abstraction Mapping: A Methodology for Hardware Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Clark W. Barrett , David L. Dill , Jeremy R. Levitt Validity Checking for Combinations of Theories with Equality. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Schneider , Thomas Kropf A Unified Approach for Combining Different Formalisms for Hardware Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Ramin Hojati , Adrian J. Isles , Desmond Kirkpatrick , Robert K. Brayton Verification Using Uninterpreted Functions and Finite Instantiations. [Citation Graph (0, 0)][DBLP ] Conf ] Zijian Zhou , Xiaoyu Song , Sofiène Tahar , Eduard Cerny , Francisco Corella , Michel Langevin Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Robert K. Brayton , Gary D. Hachtel , Alberto L. Sangiovanni-Vincentelli , Fabio Somenzi , Adnan Aziz , Szu-Tsung Cheng , Stephen A. Edwards , Sunil P. Khatri , Yuji Kukimoto , Abelardo Pardo , Shaz Qadeer , Rajeev K. Ranjan , Shaker Sarwary , Thomas R. Shiple , Gitanjali Swamy , Tiziano Villa VIS. [Citation Graph (0, 0)][DBLP ] Conf ] Natarajan Shankar PVS: Combining Specification, Proof Checking, and Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] John Harrison HOL Light: A Tutorial Introduction. [Citation Graph (0, 0)][DBLP ] Conf ] Bhaskar Bose , M. Esen Tuna , Venkatesh Choppella A Tutorial on Digital Design Derivation Using DRS. [Citation Graph (0, 0)][DBLP ] Conf ] Bishop Brock , Matt Kaufmann , J. Strother Moore ACL2 Theorems About Commercial Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Ramayya Kumar , Christian Blumenröhr , Dirk Eisenbiegler , Detlef Schmid Formal Synthesis in Circuit Design - A Classification and Survey. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Bickford , Damir Jamsek Formal Specification and Verification of VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] Naren Narasimhan , Ranga Vemuri Specification of Control Flow Properties for Verification of Synthesized VHDL Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Anthony C. J. Fox , Neal A. Harman An Algebraic Model of Correctness for Superscalar Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Phillip J. Windley , Jerry R. Burch Mechanically Checking a Lemma Used in an Automatic Verification Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey X. Su , David L. Dill , Clark W. Barrett Automatic Generation of Invariants in Processor Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Ellen Sentovich A Brief Study of BDD Package Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Meinel , Thorsten Theobald Local Encoding Transformations for Optimizing OBDD-Representations of Finite State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Jawahar Jain , Amit Narayan , C. Coelho , Sunil P. Khatri , Alberto L. Sangiovanni-Vincentelli , Robert K. Brayton , Masahiro Fujita Decomposition Techniques for Efficient ROBDD Construction. [Citation Graph (0, 0)][DBLP ] Conf ] Tomohiro Yoneda , Hideyuki Hatori , Atsushi Takahara , Shin-ichi Minato BDDs vs. Zero-Suppressed BDDs: for CTL Symbolic Model Checking of Petri Nets. [Citation Graph (0, 0)][DBLP ] Conf ] Dominique Borrione , H. Bouamama , David Déharbe , C. Le Faou , Ayman Wahba HDL-Based Integration of Formal Methods and CAD Tools in the PREVAIL Environment. [Citation Graph (0, 0)][DBLP ] Conf ] 