Conferences in DBLP
Kenneth L. McMillan Minimalist Proof Assistants: Interactions of Technology and Methodology in Formal System Level Verification (abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Robert B. Jones , Jens U. Skakkebæk , David L. Dill Reducing Manual Abstraction in Formal Verification of Out-of-Order Execution. [Citation Graph (0, 0)][DBLP ] Conf ] Miroslav N. Velev , Randal E. Bryant Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking. [Citation Graph (0, 0)][DBLP ] Conf ] M. Oliver Möller , Harald Rueß Solving Bit-Vector Equations. [Citation Graph (0, 0)][DBLP ] Conf ] Ásgeir Th. Eiríksson The Formal Design of 1M-gate ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Justin E. Harlow III , Franc Brglez Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations. [Citation Graph (0, 0)][DBLP ] Conf ] Mary Sheeran , Gunnar Stålmarck A Tutorial on Stålmarcks's Proof Procedure for Propositional Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Macha Nikolskaïa , Antoine Rauzy , David James Sherman Almana: A BDD Minimization Tool Integrating Heuristic and Rewriting Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Kathi Fisler , Moshe Y. Vardi Bisimulation Minimization in an Automata-Theoretic Verification Framework. [Citation Graph (0, 0)][DBLP ] Conf ] F. Keith Hanna Automatic Verification of Mixed-Level Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Fen Jin , Henrik Hulgaard , Eduard Cerny Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Jürgen Ruf , Thomas Kropf Using MTBDDs for Compostion and Model Checking of Real-Time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Carl-Johan H. Seger Formal Methods in CAD from an Industrial Perspective (abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Nazanin Mansouri , Ranga Vemuri A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Lock , Michael Mendler , Matthias Mutz Combined Formal Post- and Presynthesis Verification in High Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Abdelillah Mokkedem , Ravi Hosabettu , Ganesh Gopalakrishnan Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Bwolen Yang , Randal E. Bryant , David R. O'Hallaron , Armin Biere , Olivier Coudert , Geert Janssen , Rajeev K. Ranjan , Fabio Somenzi A Performance Study of BDD-Based Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Gila Kamhi , Limor Fix , Ziv Binyamini Symbolic Model Checking Visualization. [Citation Graph (0, 0)][DBLP ] Conf ] Sela Mador-Haim , Limor Fix Input Elimination and Abstraction in Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] David A. Greve Symbolic Simulation of the JEM1 Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] J. Strother Moore Symbolic Simulation: An ACL2 Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Amir Pnueli , Tamarah Arons Verification of Data-Insensitive CIrcuits: An In-Order-Retirement Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Sergey Berezin , Armin Biere , Edmund M. Clarke , Yunshan Zhu Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey X. Su , David L. Dill , Jens U. Skakkebæk Formally Verifying Data and Control with Weak Reachability Invariants. [Citation Graph (0, 0)][DBLP ] Conf ] C. Norris Ip Generalized Reversible Rules. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas A. Henzinger , Shaz Qadeer , Sriram K. Rajamani , Serdar Tasiran An Assume-Guarantee Rule for Checking Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Sofiène Tahar , Paul Curzon , Jianping Lu Three Approaches to Hardware Verification: HOL, MDG and VIS Compared. [Citation Graph (0, 0)][DBLP ] Conf ] Shiu-Kai Chin , Jang Dae Kim An Instruction Set Process Calculus. [Citation Graph (0, 0)][DBLP ] Conf ] James H. Kukula , Thomas R. Shiple , Adnan Aziz Techniques for Implicit State Enumeration of EFSMs. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Schneider Model Checking on Product Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Kim Milvang-Jensen , Alan J. Hu BDDNOW: A Parallel BDD Package. [Citation Graph (0, 0)][DBLP ] Conf ] David Déharbe , Subash Shankar , Edmund M. Clarke Model Checking VHDL with CV. [Citation Graph (0, 0)][DBLP ] Conf ] Annette Bunker , Trent N. Larson , Michael D. Jones , Phillip J. Windley Alexandria: A Tool for Hierarchical Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Ratan Nalumasu , Ganesh Gopalakrishnan PV: An Explicit Enumeration Model-Checker. [Citation Graph (0, 0)][DBLP ] Conf ] 