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Conferences in DBLP
- Wayne Wolf
Challenges in System-Level Design. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:1-5 [Conf]
- Mary Sheeran
Generating Fast Multipliers Using Clever Circuits. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:6-20 [Conf]
- Thao Dang, Alexandre Donzé, Oded Maler
Verification of Analog and Mixed-Signal Circuits Using Hybrid System Techniques. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:21-36 [Conf]
- Behzad Akbarpour, Sofiène Tahar
A Methodology for the Formal Verification of FFT Algorithms in HOL. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:37-51 [Conf]
- Julien Schmaltz, Dominique Borrione
A Functional Approach to the Formal Specification of Networks on Chip. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:52-66 [Conf]
- Sandip Ray, J. Strother Moore
Proof Styles in Operational Semantics. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:67-81 [Conf]
- Panagiotis Manolios, Daron Vroon
Integrating Reasoning About Ordinal Arithmetic into ACL2. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:82-97 [Conf]
- Mark Aagaard, Vlad C. Ciubotariu, Jason T. Higgins, Farzad Khalvati
Combining Equivalence Verification and Completion Functions. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:98-112 [Conf]
- Mark Aagaard, Nancy A. Day, Robert B. Jones
Synchronization-at-Retirement for Pipeline Verification. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:113-127 [Conf]
- Laurent Arditi, Gérard Berry, Michael Kishinevsky
Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:128-143 [Conf]
- In-Ho Moon, Carl Pixley
Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:144-158 [Conf]
- Hari Mony, Jason Baumgartner, Viresh Paruthi, Robert Kanzelman, Andreas Kuehlmann
Scalable Automated Verification via Expert-System Guided Transformations. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:159-173 [Conf]
- Emmanuel Zarpas
Simple Yet Efficient Improvements of SAT Based Bounded Model Checking. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:174-185 [Conf]
- Timo Latvala, Armin Biere, Keijo Heljanko, Tommi A. Junttila
Simple Bounded LTL Model Checking. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:186-200 [Conf]
- Enrico Giunchiglia, Massimo Narizzano, Armando Tacchella
QuBE++: An Efficient QBF Solver. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:201-213 [Conf]
- Giuseppe Della Penna, Benedetto Intrigila, Igor Melatti, Enrico Tronci, Marisa Venturini Zilli
Bounded Probabilistic Model Checking with the Muralpha Verifier. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:214-229 [Conf]
- Mohammad Awedh, Fabio Somenzi
Increasing the Robustness of Bounded Model Checking by Computing Lower Bounds on the Reachable States. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:230-244 [Conf]
- Alessandro Cimatti, Marco Roveri, Daniel Sheridan
Bounded Verification of Past LTL. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:245-259 [Conf]
- Nina Amla, Kenneth L. McMillan
A Hybrid of Counterexample-Based and Proof-Based Abstraction. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:260-274 [Conf]
- Orna Grumberg, Assaf Schuster, Avi Yadgar
Memory Efficient All-Solutions SAT Solver and Its Application for Reachability Analysis. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:275-289 [Conf]
- Tobias Nopper, Christoph Scholl
Approximate Symbolic Model Checking for Incomplete Designs. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:290-305 [Conf]
- Arie Gurfinkel, Marsha Chechik
Extending Extended Vacuity. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:306-321 [Conf]
- Marko Samer, Helmut Veith
Parameterized Vacuity. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:322-336 [Conf]
- Koen Claessen, Johan Mårtensson
An Operational Semantics for Weak PSL. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:337-351 [Conf]
- Lubos Brim, Ivana Cerná, Pavel Moravec 0002, Jirí Simsa
Accepting Predecessors Are Better than Back Edges in Distributed LTL Model-Checking. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:352-366 [Conf]
- Peter C. Dillinger, Panagiotis Manolios
Bloom Filters in Probabilistic Verification. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:367-381 [Conf]
- Ching-Tsun Chou, Phanindra K. Mannava, Seungjoon Park
A Simple Method for Parameterized Verification of Cache Coherence Protocols. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:382-398 [Conf]
- Debashis Sahoo, Subramanian K. Iyer, Jawahar Jain, Christian Stangier, Amit Narayan, David L. Dill, E. Allen Emerson
A Partitioning Methodology for BDD-Based Verification. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:399-413 [Conf]
- Christian Stangier, Thomas Sidle
Invariant Checking Combining Forward and Backward Traversal. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:414-429 [Conf]
- Zijiang Yang, Rajeev Alur
Variable Reuse for Efficient Image Computation. [Citation Graph (0, 0)][DBLP]
FMCAD, 2004, pp:430-444 [Conf]
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