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Conferences in DBLP

Formal Methods in Computer-Aided Design (FMCAD) (fmcad)
2000 (conf/fmcad/2000)

  1. Robert Beers, Rajnish Ghughal, Mark Aagaard
    Applications of Hierarchical Verification in Model Checking. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:- [Conf]
  2. Mark E. Dean
    Trends in Computing. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:1-2 [Conf]
  3. David M. Russinoff
    A Case Study in Fomal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD AthlonTM Processor. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:3-36 [Conf]
  4. Roderick Bloem, Harold N. Gabow, Fabio Somenzi
    An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:37-54 [Conf]
  5. Rajeev Alur, Radu Grosu, Bow-Yaw Wang
    Automated Refinement Checking for Asynchronous Processes. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:55-72 [Conf]
  6. In-Ho Moon, Gary D. Hachtel, Fabio Somenzi
    Border-Block Triangular Form and Conjunction Schedule in Image Computation. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:73-90 [Conf]
  7. David A. Basin, Stefan Friedrich, Sebastian Mödersheim
    B2M: A Semantic Based Tool for BLIF Hardware Descriptions. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:91-107 [Conf]
  8. Mary Sheeran, Satnam Singh, Gunnar Stålmarck
    Checking Safety Properties Using Induction and a SAT-Solver. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:108-125 [Conf]
  9. Nancy A. Day, Mark Aagaard, Byron Cook
    Combining Stream-Based and State-Based Verification Techniques. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:126-142 [Conf]
  10. Kavita Ravi, Roderick Bloem, Fabio Somenzi
    A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:143-160 [Conf]
  11. Panagiotis Manolios
    Correctness of Pipelined Machines. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:161-178 [Conf]
  12. Wolfgang Reif, Jürgen Ruf, Gerhard Schellhorn, Tobias Vollmer
    Do You Trust Your Model Checker? [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:179-196 [Conf]
  13. Edmund M. Clarke, Steven M. German, Yuan Lu, Helmut Veith, Dong Wang
    Executable Protocol Specification in ESL. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:197-216 [Conf]
  14. John Harrison
    Formal Verification of Floating Point Trigonometric Functions. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:217-233 [Conf]
  15. Jun Sawada, Warren A. Hunt Jr.
    Hardware Modeling Using Function Encapsulation. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:234-245 [Conf]
  16. Antonio Cerone, George J. Milne
    A Methodology for the Formal Analysis of Asynchronous Micropipelines. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:246-262 [Conf]
  17. Mark Aagaard, Robert B. Jones, Thomas F. Melham, John W. O'Leary, Carl-Johan H. Seger
    A Methodology for Large-Scale Hardware Verification. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:263-282 [Conf]
  18. Nina Amla, E. Allen Emerson, Robert P. Kurshan, Kedar S. Namjoshi
    Model Checking Synchronous Timing Diagrams. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:283-298 [Conf]
  19. Jin Hou, Eduard Cerny
    Model Reductions and a Case Study. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:299-315 [Conf]
  20. Adilson Luiz Bonifácio, Arnaldo V. Moura
    Modeling and Parameters Synthesis for an Air Traffic Management System. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:316-334 [Conf]
  21. Kanna Shimizu, David L. Dill, Alan J. Hu
    Monitor-Based Formal Specification of PCI. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:335-353 [Conf]
  22. Aarti Gupta, Zijiang Yang, Pranav Ashar, Anubhav Gupta
    SAT-Based Image Computation with Application in Reachability Analysis. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:354-371 [Conf]
  23. Per Bjesse, Koen Claessen
    SAT-Based Verification without State Space Traversal. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:372-389 [Conf]
  24. Shoham Ben-David, Tamir Heyman, Orna Grumberg, Assaf Schuster
    Scalable Distributed On-the-Fly Symbolic Model Checking. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:390-404 [Conf]
  25. Gordon J. Pace
    The Semantics of Verilog Using Transition System Combinators. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:405-422 [Conf]
  26. Gerd Ritter
    Sequential Equivalence Checking by Symbolic Simulation. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:423-442 [Conf]
  27. Christoph Meinel, Christian Stangier
    Speeding Up Image Computation by Using RTL Information. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:443-454 [Conf]
  28. Kiyoharu Hamaguchi, Hidekazu Urushihara, Toshinobu Kashiwabara
    Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:455-469 [Conf]
  29. Chris Wilson, David L. Dill, Randal E. Bryant
    Symbolic Simulation with Approximate Values. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:470-485 [Conf]
  30. Randal E. Bryant, Pankaj Chauhan, Edmund M. Clarke, Amit Goel
    A Theory of Consistency for Modular Synchronous Systems. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:486-504 [Conf]
  31. Michael D. Jones, Ganesh Gopalakrishnan
    Verifying Transaction Ordering Properties in Unbounded Bus Networks through Combined Deductive/Algorithmic Methods. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:505-519 [Conf]
  32. Alex Tsow, Steven D. Johnson
    Visualizing System Factorizations with Behavior Tables. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:520-537 [Conf]
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