Conferences in DBLP
Andy Gean Ye , Jonathan Rose Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits. [Citation Graph (0, 0)][DBLP ] Conf ] David M. Lewis , Elias Ahmed , Gregg Baeckler , Vaughn Betz , Mark Bourgeault , David Cashman , David R. Galloway , Mike Hutton , Christopher Lane , Andy Lee , Paul Leventis , Sandy Marquardt , Cameron McClintock , Ketan Padalia , Bruce Pedersen , Giles Powell , Boris Ratchev , Srinivas Reddy , Jay Schleicher , Kevin Stevens , Richard Yuan , Richard Cliff , Jonathan Rose The Stratix II logic and routing architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Satish Sivaswamy , Gang Wang , Cristinel Ababei , Kia Bazargan , Ryan Kastner , Eli Bozorgzadeh HARP: hard-wired routing pattern FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Chao-Yang Yeh , Malgorzata Marek-Sadowska Skew-programmable clock design for FPGA and skew-aware placement. [Citation Graph (0, 0)][DBLP ] Conf ] Yuzheng Ding , Peter Suaris , Nan-Chi Chou The effect of post-layout pin permutation on timing. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Chen , Jason Cong Simultaneous timing-driven placement and duplication. [Citation Graph (0, 0)][DBLP ] Conf ] Ling Zhuo , Viktor K. Prasanna Sparse Matrix-Vector multiplication on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Michael DeLorimier , André DeHon Floating-point sparse matrix-vector multiply for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Yong Dou , Stamatis Vassiliadis , Georgi Kuzmanov , G. N. Gaydadjiev 64-bit floating-point FPGA matrix multiplication. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Yiping Fan , Guoling Han , Ashok Jagannathan , Glenn Reinman , Zhiru Zhang Instruction set extension with shadow registers for configurable processors. [Citation Graph (0, 0)][DBLP ] Conf ] Alex K. Jones , Raymond Hoare , Dara Kusic , Joshua Fazekas , John Foster An FPGA-based VLIW processor with custom hardware execution. [Citation Graph (0, 0)][DBLP ] Conf ] Greg Stitt , Zhi Guo , Walid A. Najjar , Frank Vahid Techniques for synthesizing binaries to an advanced register/memory structure. [Citation Graph (0, 0)][DBLP ] Conf ] André DeHon Design of programmable interconnect for sublithographic programmable logic arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Nicola Campregher , Peter Y. K. Cheung , George A. Constantinides , Milan Vasilko Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Ghazanfar Asadi , Mehdi Baradaran Tahoori Soft error rate estimation and mitigation for SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Song Peng , David Fang , John Teifel , Rajit Manohar Automated synthesis for asynchronous FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Hutton , David Karchmer , Bryan Archell , Jason Govig Efficient static timing analysis and applications using edge masks. [Citation Graph (0, 0)][DBLP ] Conf ] Heidi E. Ziegler , Mary W. Hall Evaluating heuristics in automatically mapping multi-loop applications to FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Yan Lin , Fei Li , Lei He Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Lodi , Luca Ciccarelli , Roberto Giansante Combining low-leakage techniques for FPGA routing design. [Citation Graph (0, 0)][DBLP ] Conf ] Ian Kuon , Aaron Egier , Jonathan Rose Design, layout and verification of an FPGA using automated tools. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy F. Oliver , Bertil Schmidt , Douglas L. Maskell Hyper customized processors for bio-sequence database scanning on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Haoyu Song , John W. Lockwood Efficient packet classification for network intrusion detection using FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Graham Schelle , Dirk Grunwald CUSP: a modular framework for high speed network applications on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Remy Eskinazi Sant'Anna , Manoel Eusebio de Lima , Paulo Romero Martins Maciel , Carlos A. Valderrama , Abel Guilhermino S. Filho , Paulo Sérgio B. do Nascimento A petri-net based Pre-runtime scheduler for dynamically self-reconfiguration of FPGAs (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Kelly Nasi , Martin Danek , Theodoros Karoubalis , Zdenek Pohl Figaro: an automatic tool flow for designs with dynamic reconfiguration (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Yirong OuYang , Jiarong Tong A New Universal Test Pattern Auto-generating Approach for FPGA Logic Resources (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Leos Kafka , Rafal Kielbik , Rudolf Matousek , Juan Manuel Moreno VPart: an automatic partitioning tool for dynamic reconfiguration (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Cristinel Ababei , Hushrav Mogal , Kia Bazargan 3D FPGAs: placement, routing, and architecture evaluation (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Deepak Rautela , Rajendra Katti Efficient utilization of heterogeneous routing resources for FPGAs (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Ben Cordes , Jennifer G. Dy , Miriam Leeser , James Goebel Enabling a RealTime Solution for Neuron Detection with Reconfigurable Hardware (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Yohei Hasegawa , Shohei Abe , Katsuaki Deguchi , Masayasu Suzuki , Hideharu Amano Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] E. Syam Sundar Reddy , Vikram Chandrasekhar , Milagros Sashikánth , V. Kamakoti , Narayanan Vijaykrishnan Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Akshay Sharma , Carl Ebeling , Scott Hauck Architecture Adaptive Routability-Driven Placement for FPGAs (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Taraneh Taghavi , Soheil Ghiasi , Majid Sarrafzadeh Routing algorithms: enhancing routability & enabling ECO (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Wenyin Fu , Katherine Compton An execution environment for reconfigurable computing (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Hassan Hassan , Mohab Anis , Mohamed I. Elmasry A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Rohini Krishnan , R. I. M. P. Meijer , Durand Guillaume Energy-efficient FPGA interconnect architecture design (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Alastair M. Smith , George A. Constantinides , Peter Y. K. Cheung Exploration of heterogeneous reconfigurable architectures (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Wen Yujie , Jiarong Tong , Charles Chiang Domain Specific Non-Uniform Routing Architecture for Embedded Programmable IP Core (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Mehrdad Najibi , Kamran Saleh , Mohsen Naderi , Hossein Pedram , Mehdi Sedighi Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Pascal Benoit , Lionel Torres , Gilles Sassatelli , Michel Robert , Gaston Cambon Dynamic hardware multiplexing for coarse grain reconfigurable architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Chul Kim , A. M. Rassau , Mike Myung-Ok Lee 3D-SoftChip: a novel 3D vertically integrated adaptive computing system (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Roman L. Lysecky , Kris Miller , Frank Vahid , Kees A. Vissers Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Yujia Jin , William Plishker , Kaushik Ravindran , Nadathur Satish , Kurt Keutzer Soft multiprocessor systems for network applications (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Somsubhra Mondal , Seda Ogrenci Memik , Debasish Das Hierarchical LUT structures for leakage power reduction (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Akhilesh Kumar , Mohab Anis Dual-Vt FPGA design for leakage power reduction (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Ankit Mathur , Mayank Agarwal , Soumyadeb Mitra , Anup Gangwar , M. Balakrishnan , Subhashis Banerjee SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Roman Bartosinski , Martin Danek , Petr Honzík , Rudolf Matousek Dynamic reconfiguration in FPGA-based SoC designs (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Jacqueline E. Rice , Kenneth B. Kent , Troy Ronda , Zhao Yong Configurable hardware solutions for computing autocorrelation coefficients: a case study (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Paulo Sérgio B. do Nascimento , Paulo Romero Martins Maciel , Manoel Eusebio de Lima , Remy Eskinazi Sant'Anna , Abel Guilhermino S. Filho A partial reconfigurable FPGA implementation for industrial controllers using SFC-petri net description (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Wang Yong-Gang , Yan Tian-xin Design and implementation of packet classification with FPGA (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Edward Brown , James Irvine , Bill Wilkie Rapid prototyping of a test harness for forward error correcting codes (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Stéphane Simard , Rachid Beguenane , Éric Larouche , Luc Morin A 2005 review of FPGA arithmetic (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed Taher , Esam El-Araby , Tarek A. El-Ghazawi , Kris Gaj Image processing library for reconfigurable computers (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Sven Heithecker , Rolf Ernst An FPGA based SDRAM controller with complex QoS scheduling and traffic shaping (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Michael Attig , John W. Lockwood A framework for rule processing in reconfigurable network systems (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Edward D. Moreno , Fábio Dacêncio Pereira , Rodolfo B. Chiaramonte A VLIW-based cryptoprocessor on FPGAs architecture and performance issues (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Khaled Benkrid , S. Belkacemi An integrated framework for the high level design of high performance signal processing circuits on FPGAs (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Tarek A. El-Ghazawi , Kris Gaj , Nikitas A. Alexandridis , Allen Michalski , Osman Devrim Fidanci , Mohamed Taher , Esam El-Araby , Esmail Chitalwala , Proshanta Saha Reconfigurable computers: an empirical analysis (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Bryan C. Catanzaro , Brent E. Nelson Choice of base revisited: higher radices for FPGA-based floating-point computation (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Jianchun Li , Christos A. Papachristou , Raj Shekhar Accelerating mutual information-based 3D medical image registration with An FPGA computing platform (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Nicola Bruti Liberati , Eckhard Platen , Filippo Martini , Massimo Piccardi An FPGA generator for multipoint distributed random variables (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] Bo Yang , Nikhil Joshi , Ramesh Karri A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only). [Citation Graph (0, 0)][DBLP ] Conf ] 