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Conferences in DBLP

Symposium on Field Programmable Gate Arrays (FPGA) (fpga)
1992 (conf/fpga/1992)

  1. Günter Biehl
    Overview of Complex Array-Based PLDs. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:1-10 [Conf]
  2. Jouni Isoaho, Arto Nummela, Hannu Tenhunen
    Technologies and Utilization fo Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:11-25 [Conf]
  3. Alberto L. Sangiovanni-Vincentelli
    Some Considerations on Field-Programmable Gate Arrays and Their Impact on System Design. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:26-34 [Conf]
  4. Bradly K. Fawcett
    SRAM-Based FPLs Ease System Verification. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:35-43 [Conf]
  5. Scott Hauck, Gaetano Borriello, Steven M. Burns, Carl Ebeling
    MONTAGNE: An FPL for Synchronous and Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:44-51 [Conf]
  6. Dwight D. Hill, Barry K. Britton, William Oswald, Nam Sung Woo, Satwant Singh, Che-Tsung Chen, Bob Krambeck
    ORCA: A New Architecture for High-Performance FPLs. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:52-60 [Conf]
  7. Masahiro Fujita, Yuji Kukimoto
    Patching Method for Lookup-Table Type FPLs. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:61-70 [Conf]
  8. Dave Allen
    Automatic One-Hot Re-Encoding for FPLs. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:71-77 [Conf]
  9. Li-Fei Wu, Marek A. Perkowski
    Minimization of Permuted Reed-Muller Trees for Cellular Logic. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:78-87 [Conf]
  10. David C. Blight, Robert D. McLeod
    Self-Organizing Kohonen Maps for FPL Placement. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:88-95 [Conf]
  11. Peter Poechmueller, Hans-Jürgen Herpel, Manfred Glesner, Fang Longsen
    High Level Synthesis in an FPL-Based Computer Aided Prototyping Environment. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:96-105 [Conf]
  12. Naohisa Ohta, Kazuhisa Yamada, Akihiro Tsutsui, Hiroshi Nakada
    New Application of FPLs to Programmable Digital Communication Cirucits. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:106-111 [Conf]
  13. Georg J. Kempa, Peter Jung
    FPL Based Logic Synthesis of Squarers Using VHDL. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:112-123 [Conf]
  14. Hartmut Surmann, Ansgar Ungering, Karl Goser
    Optimized Fuzzy Controller Architecture for Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:124-133 [Conf]
  15. Lennart Lindh, Klaus D. Müller-Glaser, Hans Rauch, Frank Stanischewski
    A Real-Time Kernel - Rapid Prototyping with VHDL and FPLs. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:134-145 [Conf]
  16. Herbert Grünbacher, Alexander Jaud
    JAPROC - An 8 bit Micro Controller Design and Its Test Environment. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:146-151 [Conf]
  17. Beat Heeb, Cuno Pfister
    Chameleon: A Workstation of a Different Colour. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:152-161 [Conf]
  18. Paul Shaw, George J. Milne
    A Highly Parallel FPL-Based Machine and Its Formal Verification. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:162-173 [Conf]
  19. Arno Kunzmann
    FPL Based Self-Test with Deterministic Test Patterns. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:174-182 [Conf]
  20. Dzung T. Hoang, Daniel P. Lopresti
    FPL Implementation of Systolic Sequence Alignment. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:183-191 [Conf]
  21. Erik Brunvand
    Using FPLs to Prototoype a Self-Timed Computer. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:192-198 [Conf]
  22. Arne Linde, Tomas Nordström, Mikael Taveniku
    Using FPLs to Implement a Reconfigurable Highly Parallel Computer. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:199-210 [Conf]
  23. Andreas Ast, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt
    Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design Methods. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:211-217 [Conf]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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