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Conferences in DBLP
- Tim Tuan, Sean Kao, Ahmad Arif Rahman, Satyaki Das, Steven Trimberger
A 90nm low-power FPGA for battery-powered applications. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:3-11 [Conf]
- Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert
Embedded floating-point units in FPGAs. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:12-20 [Conf]
- Ian Kuon, Jonathan Rose
Measuring the gap between FPGAs and ASICs. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:21-30 [Conf]
- Jason Cong, Kirill Minkovich
Optimality study of logic synthesis for LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:33-40 [Conf]
- Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
Improvements to technology mapping for LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:41-49 [Conf]
- Mark Holland, Scott Hauck
Improving performance and robustness of domain-specific CPLDs. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:50-59 [Conf]
- Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu
Design, implementation, and verification of active cache emulator (ACE). [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:63-72 [Conf]
- Christopher R. Clark, David E. Schimmel
Modeling the data-dependent performance of pattern-matching architectures. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:73-82 [Conf]
- Jianhua Liu, Michael Chang, Chung-Kuan Cheng
An iterative division algorithm for FPGAs. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:83-89 [Conf]
- Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
Yield enhancements of design-specific FPGAs. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:93-100 [Conf]
- Julien Lamoureux, Steven J. E. Wilton
FPGA clock network architecture: flexibility vs. area and power. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:101-108 [Conf]
- Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, Simon Wong
Performance benefits of monolithically stacked 3D-FPGA. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:113-122 [Conf]
- Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon
Magnetic tunnelling junction based FPGA. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:123-130 [Conf]
- Dmitri B. Strukov, Konstantin Likharev
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:131-140 [Conf]
- Lotfi Mhamdi, Christopher Kachris, Stamatis Vassiliadis
A reconfigurable hardware based embedded scheduler for buffered crossbar switches. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:143-149 [Conf]
- Lilian Atieno, Jonathan Allen, Dennis Goeckel, Russell Tessier
An adaptive Reed-Solomon errors-and-erasures decoder. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:150-158 [Conf]
- Norbert Pramstaller, Christian Rechberger, Vincent Rijmen
A compact FPGA implementation of the hash function whirlpool. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:159-166 [Conf]
- Kenneth Eguro, Scott Hauck
Armada: timing-driven pipeline-aware routing for FPGAs. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:169-178 [Conf]
- Welson Sun, Michael J. Wirthlin, Stephen Neuendorffer
Combining module selection and resource sharing for efficient FPGA pipeline synthesis. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:179-188 [Conf]
- Russell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy
Power-aware RAM mapping for FPGA embedded memory blocks. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:189-198 [Conf]
- Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
Application-specific customization of soft processor microarchitecture. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:201-210 [Conf]
- Peter A. Milder, Mohammad Ahmad, James C. Hoe, Markus Püschel
Fast and accurate resource estimation of automatically generated custom DFT IP cores. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:211-220 [Conf]
- Yohei Matsumoto, Hanpei Koike, Akira Masaki
FPGAs with multidimensional mesh topology. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:223- [Conf]
- Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
Evaluation of granularity on threshold voltage control in flex power FPGA. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:223- [Conf]
- K. Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis
A novel methodology for designing high-performance and low-energy FPGA routing architecture. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:224- [Conf]
- Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura
Autonomous-repair cell for fault tolerant dynamic-reconfigurable devices. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:224- [Conf]
- Garrett S. Rose, Mircea R. Stan
A programmable majority logic array using molecular scale electronics. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:225- [Conf]
- Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez
A multilevel hierarchical interconnection structure for FPGA. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:225- [Conf]
- Mohammad Tehranipoor, Reza M. Rad
Test and recovery for fine-grained nanoscale architectures. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:226- [Conf]
- Mohammad Tehranipoor, Reza M. Rad
Fine-grained island style architecture for molecular electronic devices. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:226- [Conf]
- Benjamin Ylvisaker, Brian Van Essen, Carl Ebeling
A type architecture for hybrid micro-parallel computers. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:227- [Conf]
- Wenyi Feng, Jonathan Greene
Post-placement interconnect entropy. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:227- [Conf]
- Youngsun Han, Seokjoong Hwang, Seon Wook Kim
Jaguar: a compiler infrastructure for Java reconfigurable computing. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:228- [Conf]
- Mohammed Y. Niamat, Dinesh Nemade, Mohsin M. Jamali
Testing embedded RAM modules in SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:228- [Conf]
- Zied Marrakchi, Hayder Mrabet, Habib Mehrez
Configuration tools for a new multilevel hierarchical FPGA. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:229- [Conf]
- Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi
Effective clustering technique to optimize routability of outer cluster nets. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:229- [Conf]
- Rajagopal Subramaniyan, Ian A. Troxel, Alan D. George, Melissa Smith
Simulative analysis of dynamic scheduling heuristics for reconfigurable computing of parallel applications. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:230- [Conf]
- Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner
High speed FIR filter implementation using add and shift method. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:231- [Conf]
- Thinh Ngoc Tran, Surin Kittitornkun, Shigenori Tomiyama
Manifold similarity search of DNA sequences with reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:231- [Conf]
- Manuel Saldaña, Lesley Shannon, Paul Chow
The routability of multiprocessor network topologies in FPGAs. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:232- [Conf]
- Oliver Sims, James Irvine
A real-time implementation of Richardson-Lucy deconvolution. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:232- [Conf]
- Michael Gilroy, James Irvine, William Berrie
FPGA based RAID 6 hardware accelerator. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:232- [Conf]
- Jike Chong, Chidamber Kulkarni, Gordon J. Brebner
Building a flexible and scalable DRAM interface for networking applications on FPGAs. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:233- [Conf]
- Janardhan Singaraju, John A. Chandy
A generic lookup cache architecture for network processing applications. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:233- [Conf]
- Joshua Noseworthy, Miriam Leeser
Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:233- [Conf]
- Ronald Scrofano, Viktor K. Prasanna
A Performance model for accelerating scientific applications on reconfigurable computers. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:234- [Conf]
- Nathaniel Couture, Kenneth B. Kent
Periodic licensing of FPGA based intellectual property. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:234- [Conf]
- Vikas Aggarwal, Alan D. George, K. Clint Slatton
Reconfigurable computing with multiscale data fusion for remote sensing. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:235- [Conf]
- David T. Nguyen, Gokhan Memik, Alok N. Choudhary
A reconfigurable architecture for network intrusion detection using principal component analysis. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:235- [Conf]
- Milan Tichý, Andy Nisbet, David Gregg
GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:236- [Conf]
- Tatsuhiro Tachibana, Yoshihiro Murata, Naoki Shibata, Keiichi Yasumoto, Minoru Ito
Flexible implementation of genetic algorithms on FPGAs. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:236- [Conf]
- Young H. Cho, James Moscola, John W. Lockwood
Context-free-grammar based token tagger in reconfigurable devices. [Citation Graph (0, 0)][DBLP]
FPGA, 2006, pp:237- [Conf]
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