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Conferences in DBLP

Symposium on Field Programmable Gate Arrays (FPGA) (fpga)
2004 (conf/fpga/2004)

  1. Nicholas Weaver, John R. Hauser, John Wawrzynek
    The SFRA: a corner-turn FPGA architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:3-12 [Conf]
  2. Akshay Sharma, Katherine Compton, Carl Ebeling, Scott Hauck
    Exploration of pipelined FPGA interconnect structures. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:13-22 [Conf]
  3. Arifur Rahman, Vijay Polavarapuv
    Evaluation of low-leakage design techniques for field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:23-30 [Conf]
  4. Jason Helge Anderson, Farid N. Najm, Tim Tuan
    Active leakage power optimization for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:33-41 [Conf]
  5. Fei Li, Yan Lin, Lei He, Jason Cong
    Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:42-50 [Conf]
  6. Aman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan
    Reducing leakage energy in FPGAs using region-constrained placement. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:51-58 [Conf]
  7. Paul Metzgen
    A high performance 32-bit ALU for programmable logic. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:61-70 [Conf]
  8. Paul Kohlbrenner, Kris Gaj
    An embedded true random number generator for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:71-78 [Conf]
  9. Sergio López-Buedo, Eduardo I. Boemo
    Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:79-86 [Conf]
  10. Tomasz S. Czajkowski, Jonathan Rose
    A synthesis oriented omniscient manual editor. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:89-98 [Conf]
  11. Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou
    Incremental physical resynthesis for timing optimization. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:99-108 [Conf]
  12. Deming Chen, Jason Cong, Fei Li, Lei He
    Low-power technology mapping for FPGA architectures with dual supply voltages. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:109-117 [Conf]
  13. André DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica
    What is the right model for programming and using modern FPGAs? [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:119- [Conf]
  14. André DeHon, Michael J. Wilson
    Nanowire-based sublithographic programmable logic arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:123-132 [Conf]
  15. John Teifel, Rajit Manohar
    Highly pipelined asynchronous FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:133-142 [Conf]
  16. Steve Ferrera, Nicholas P. Carter
    A magnetoelectronic macrocell employing reconfigurable threshold logic. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:143-151 [Conf]
  17. Katherine Compton, Scott Hauck
    Flexibility measurement of domain-specific reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:155-161 [Conf]
  18. Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers
    A quantitative analysis of the speedup factors of FPGAs over processors. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:162-170 [Conf]
  19. Keith D. Underwood
    FPGAs vs. CPUs: trends in peak floating-point performance. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:171-180 [Conf]
  20. Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang
    Application-specific instruction generation for configurable processor architectures. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:183-189 [Conf]
  21. Lesley Shannon, Paul Chow
    Using reconfigurability to achieve real-time profiling for hardware/software codesign. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:190-199 [Conf]
  22. Richard B. Kujoth, Chi-Wei Wang, Derek B. Gottlieb, Jeffrey J. Cook, Nicholas P. Carter
    A reconfigurable unit for a clustered programmable-reconfigurable processor. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:200-209 [Conf]
  23. Wang Chen, Panos Kosmas, Miriam Leeser, Carey Rappaport
    An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:213-222 [Conf]
  24. Zachary K. Baker, Viktor K. Prasanna
    Time and area efficient pattern matching on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:223-232 [Conf]
  25. John F. Keane, Christopher Bradley, Carl Ebeling
    A compiled accelerator for biological cell signaling simulations. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:233-241 [Conf]
  26. Sherif M. Saif, Hazem M. Abbas, Salwa M. Nassar
    An FPGA implementation of block truncation coding for gray and color images. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:245- [Conf]
  27. Anatole D. Ruslanov, Jeremy R. Johnson
    An FPGA implementation of bene permutation networks. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:245- [Conf]
  28. Erik Chmelar
    Subframe multiplexing for FPGA manufacturing test configuration. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:245- [Conf]
  29. Bret Woz, Andreas E. Savakis
    A VHDL MPEG-7 shape descriptor extractor. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:246- [Conf]
  30. Andrea Lodi, Roberto Giansante, Carlo Chiesa, Luca Ciccarelli, Mario Toma, Fabio Campi
    Routing architecture for multi-context FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:246- [Conf]
  31. Richard Carbone, Andreas E. Savakis
    A flexible hardware architecture for 2-D discrete wavelet transform. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:246- [Conf]
  32. Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller
    Using an FPGA coprocessor for improving execution speed of TRT-LUT: one of the feature extraction algorithms for ATLAS LVL2 trigger. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:247- [Conf]
  33. Helmut Steckenbiller, Rudi Knorr
    Buffer schemes for runtime reconfiguration of function variants in communication systems. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:247- [Conf]
  34. Daniel Denning, Malachy Devlin, James Irvine
    Hardware co-simulation in system generator of the AES-128 encryption algorithm. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:247- [Conf]
  35. Jong-Ru Guo, Chao You, Michael Chu, Robert W. Heikaus, Kuan Zhou, Okan Erdogan, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald
    The gigahertz FPGA: design consideration and applications. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:248- [Conf]
  36. Gabriel Caffarena, Slobodan Bojanic, Juan A. López, Carlos E. Pedreira, Octavio Nieto-Taladriz
    High-speed systolic array for gene matching. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:248- [Conf]
  37. Christopher C. Doss, Robert L. Riley Jr.
    FPGA-based implementation of single-precision exponential unit. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:248- [Conf]
  38. Jae-Jin Lee, Gi-Yong Song
    Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:249- [Conf]
  39. Ian Kuon, Aaron Egier, Jonathan Rose
    Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:249- [Conf]
  40. Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee
    High level area, delay and power estimation for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:249- [Conf]
  41. Joseph Zambreno, Rahul Simha, Alok N. Choudhary
    Addressing application integrity attacks using a reconfigurable architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:250- [Conf]
  42. Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris
    Fast adders in modern FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:250- [Conf]
  43. Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi
    SPFD-based one-to-many rewiring. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:250- [Conf]
  44. Mark L. Chang, Scott Hauck
    Least-significant bit optimization techniques for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:251- [Conf]
  45. A. Manoj Kumar, B. Jayaram, V. Kamakoti
    SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:251- [Conf]
  46. Martin Danek, Josef Kolar
    FPGA modelling for high-performance algorithms. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:251- [Conf]
  47. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
    A novel coarse-grain reconfigurable data-path for accelerating DSP kernels. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:252- [Conf]
  48. Christophe Wolinski, Krzysztof Kuchcinski, Maya Gokhale
    A constraints programming approach to communication scheduling on SoPC architectures. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:252- [Conf]
  49. Michael J. Wirthlin
    Improving the reliability of FPGA circuits using triple-modular redundancy (TMR) & efficient voter placement. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:252- [Conf]
  50. Paul Berube, José Nelson Amaral, Mike MacGregor
    An FPGA prototype for the experimental evaluation of a multizone network cache. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:253- [Conf]
  51. Ian Kuon, Navid Azizi, Ahmad Darabiha, Aaron Egier, Paul Chow
    FPGA-based supercomputing: an implementation for molecular dynamics. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:253- [Conf]
  52. Navaratnasothie Selvakkumaran, Abhishek Ranjan, Salil Raje, George Karypis
    Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:253- [Conf]
  53. Magesh Sadasivam, Sangjin Hong
    Dynamically reconfigurable architecture for high-throughput processing of data centric applications. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:254- [Conf]
  54. Phan C. Vinh, Jonathan P. Bowen
    An algorithmic approach by heuristics to dynamical reconfiguration of logic resources on reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:254- [Conf]
  55. Pronita Mehrotra, Mrugendra Singhai, Mike Pratt, Mark Cassada, Patrick Hamilton
    FPGA implementation of a high speed network interface card for optical burst switched networks. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:255- [Conf]
  56. Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek
    Low energy FPGA interconnect design. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:255- [Conf]
  57. Roland E. Wunderlich, James C. Hoe
    In-system FPGA prototyping of an itanium microarchitecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:255- [Conf]
  58. Ranjesh G. Jaganathan, Matthew Simpson, Ron Sass
    Automatic discovery, selection, and specialization of modules in RCADE. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:256- [Conf]
  59. Sanghamitra Roy, Debjit Sinha, Prithviraj Banerjee
    An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:256- [Conf]
  60. Brian Leonard, Jeff Young, Ron Sass
    Online placement infrastructure to support run-time reconfiguration. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:256- [Conf]
  61. Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
    Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:257- [Conf]
  62. Vinay Verma, Shantanu Dutt
    Roving testing using new built-in-self-tester designs for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:257- [Conf]
  63. Thilo Pionteck, Thorsten Staake, Thomas Stiefmeier, Lukusa D. Kabulepa, Manfred Glesner
    On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:258- [Conf]
  64. Bo Yang, Ramesh Karri, David A. McGrew
    Divide and concatenate: a scalable hardware architecture for universal MAC. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:258- [Conf]
  65. Elias Todorovich, Eduardo I. Boemo, F. Cardells, J. Valls
    Power analysis and estimation tool integrated with XPOWER. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:259- [Conf]
  66. Sashisu Bajracharya, Chang Shu, Kris Gaj, Tarek A. El-Ghazawi
    Implementation of elliptic curve cryptosystems over GF(2n) in optimal normal basis on a reconfigurable computer. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:259- [Conf]
  67. Remy Eskinazi Sant'Anna, Manoel Eusebio de Lima, Paulo Romero Martins Maciel
    A left-edge algorithm approach for scheduling and allocation of hardware contexts in dynamically reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:259- [Conf]
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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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